Registers and MAL

Lecture 12

The MAL Architecture

MAL is a load/store architecture. MAL supports only those addressing modes

supported by the MIPS RISC assembler. SAL is both a memory-to-memory

architecture and load/store architecture. SAL does not have indirect addressing mode.

The MAL architecture has two distinct register files: 32 general registers and 16 floating point registers

SAL is implemented by synthesizing its instructions from a sequence of MAL instructions.

lw $8,xlw $9,yadd $10,$8,$9sw $10,z

add z,x,y

SAL MAL

General Registers

Numbered $0 to $31 Not all registers are used for programming $0 always contains zero; $0 may be specified as

destination but any value calculated is lost $1 is used by the assembler $2, $4 are used for syscalls $26 and $27 are used by the operating system $28,$29, and $31are used in procedures

Floating Point Registers Floating point operands can be either single-

precision(32 bits) or double-precision(64 bits) MAL floating point registers are 64 bits long Each register is two words long (two 32-bit words) The words are numbered 0 to 31. Each pair (e.g., word

0 and word 1) represents one floating point register Floating point register are numbered $f0,$f2,$f4,…,

$f30 Only the even-numbered registers are used for single-

precision representation

MAL Load and Store Instructions

lw R, address

R is the register. In its most general form the address can include both a constant (which can be a label) and a base register. For example,

lw $22, 12($25)

The effective address is computed by adding 12 to the contents of the base register $25. Note that ($25) means the contents of register 25. The word at the effective address is loaded into register 22. Make sure that the effective address is a multiple of 4.

The immediate addressing mode is supported by

li R, constant

The constant operand is loaded into register R. A variant of li is the load address instruction.

la R, label

In the above instruction, the address bound to label is loaded into register R.

la $8, var_namelw $8,($8)

lw $8, var_name

equivalent

Example 14.1

We can access an element of an array ar of integers in the following manner:

la $8, aradd $8,$8,20 #offset is 5 words

lw $8,($8)

Data can be copied from the register R to the memory location specified by address

sw R, address Similar to the load instruction the address can

include both a constant and a base register specification.

sw, $13, 4($9)

The effective address is computed by adding 4 to the contents of register 9.

The sb is equivalent to the store word instruction, sw, only that it stores 1 byte instead of 4 bytes to the effective address.

Only the least significant byte of the register is used.

The lb and lbu instructions load the byte into the least significant byte of the register. lbu loads the byte as unsigned, i.e. the other three

bytes in the register are set to 0 lb sign-extends the byte -- the other three bytes are

set to whatever the sign of the byte is.

Arithmetic and Logical Instructions

Arithmetic and logical instructions come in the following format:

instruction_mnemonic D,S1,S2

where D is the destination register and registers S1 and S2 specify the source of operands

If source register S1 is not specified, it is implied to be the same as D

S2 must be present; it can either be a register or a constant

Example 14.2

add $9,$8,0xabcd #S1 is $8, S2 is 0xabcd

mul $9,0xabcd#S1 the same as D = $9

mul $9,$9,0xabcd

sub $5,$21,16

and $4,$8,1

move instruction

The move instruction is restricted to register operands

move $4, $8

move $6, $0 # $0 is always zero

Shift Instructions

There are three shift instructions: sll, srl, sra These instructions are the same as the SAL

instructions only that registers are specified as source and destination

The amount of shift can either be specified as a constant or as contents to the register. In this case the least 5 (note that log2 32 = 5)significant bits are interpreted as unsigned integer

Example 14.3

Sll $8, $9, 5

The contents of register 9 is shifted to the left 5 timesand the result is placed into register 8

Floating Point Instructions

To load a single-precision number usel.s F, address

where F specifies one of the 32 words making up the 16 floating point registers and from an address in memory

It takes two load instructions to load a double-precision floating point register

The register specified as address is a general-purpose register

To store floating point uses.s F, address

where address like the load instruction is a multiple of four

There are no byte operations for floating point registers

The following loads an immediate single-precision floating point operand

li.s $f6, 1.0

The move instructionmov.s $f4,$f0

copies value from $f0 to $f4 The register $f0 does not necessarily

have a value of zero, unlike the general-purpose registers

Other instructions:add.s, sub.s, mul.s, and div.s

Double-precision operations can be specified by using the suffix .d instead of .s

I/O instructions

A conversion is necessary if the type to be displayed or input is either .word or .float

getc R

where R is a general registerputc R

puts S

where S can either be a general register or a label

Example 14.4

.data

ar: .word 0:50

# $8 - flag, 1 algorithm is done

# 0 another iteration needed

# $9 - offset to the correct element

# $10 - address of element to compare

# $11 - array element for comparison

# $12 - neighbor of element in $11

# $14 - base address of array ar

21

. . .

la $14,ar

loop: li $8,1

li $9,0 #offset

for: add $10,$14,$9

lw $11,($10)

lw $12,4($10)

sub $13,$11,$12

blez $13,noswap

li $8,0 #another iteration needed

sw $11,4($10)

sw $12,($10)

noswap:add $9,$9,4

sub $13,$9,196 #check if end is reached

bltz $13,for #check end of one iteration

beq $8,$0,loop #$8 is 0 if a swap was done

done