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Registers and Counters
Adapted from slides b y R. H. Katz
RegistersStorage Register
Group of storage elements read/written as a unit
4-bit register constructed from 4 D FFsShared clock and clear lines
TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)
Schematic Shape
Q1
CLR
D3D2D1D0
171
Q1
Q0Q0
CLK Q3Q3Q2Q2
11
109
5
67
43
2
14
13
151
12
\Clr
D3
D2
D1
D0
Clk
Q3
Q2
Q1
Q0
D
R
S
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
R
S
R
S
R
S
RegistersInput/Output Variations
Selective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs
74377 Octal D-type FFswith input enable
74374 Octal D-type FFswith output enable
EN enabled low andlo-to-hi clock transition
to load new data intoregister
OE asserted lowpresents FF state to
output pins; otherwisehigh impedence
D3
D6Q5
Q2
377
Q1Q0
Q3
EN CLK
Q6
Q4
Q7
D5
D2D1D0
D4
D7
1
3478
13141718
11
256912151619
HGFEDCBA
QHQGQFQEQDQCQBQA
OE
37411
1
3478
13141718
256912151619
CLK
Registers
Register FilesTwo dimensional array of flipflopsAddress used as index to a particular wordWord contents read or written
74670 4x4 Register File withTri-state Outputs
Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs
Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)
670
Q4
D1
D4D3D2
Q3Q2Q1
WE
WAWB
RE
RARB
54
11
1413
12
15123
10976
Shift RegistersShift Registers
Storage + ability to circulate data among storage elements
Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal
Wrap around from rightmost element to leftmost element
Master Slave FFs: sample inputs while clock is high; change outputs on falling edge
Shift Direction\Reset
\ResetShift
CLK CLK CLK CLK
Q 1 1 0 0 0
Q 2 0 1 0 0
Q 3 0 0 1 0
Q 4 0 0 0 1
Shift
Shift
Shift
+
SQ1 Q2 Q3S S
+
J
K
Q
QR
S J
K
Q
QR
J
K
Q
QR
J
K
Q
QR
Q4
Shift Registers
• Bidirectional Shift Registers
D
C
Q D
C
Q D
C
Q D
C
Q
CLK
Q1 Q2 Q3Q0
RIGHT/LEFT
Serial data in
Shift Registers
Universal Shift Register Serial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right
74194 4-bit UniversalShift Register
Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices
S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state
Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
D7D6D5D4
Sender
D3D2D1D0
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
Receiver
D7D6D5D4
D3D2D1D0
Clock
194 194
194194
ParallelInputs
Serialtransmission
ParallelOutputs
Shift Registers
• Shift Register Application:– Parallel-to-Serial/Serial-to-Parallel Conversion
Shift Registers
• Shift Register Application:– Parallel to Serial Conversion for asynchronous communication
8-bit register
8-bit shift register
counterdiv 8
one-shot
clkgen
Serialdata in
1
0
J
K
Q
0
parallel data out
load
CLR
D
Q
CLR
CLK
TC
D7 D6 D5 D4 D3 D2 D1 D0startbit
stopbit
stopbit
Shift Registers
• Shift Register Application:– Universal Asynchronous Receiver Transmitter (UART)
micro-processor
systemUART
externaldevice
paralleldata bus
serial data out
serial data in
buffers
xmitterdata
register
receiverdata
register
xmittershift
register
receivershift
register
paralleldatabus
serialdataout
serialdata
in
CountersCounters
Proceed through a well-defined sequence of states in response to count signal
3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code Counters
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
Counters
Johnson (Mobius) Counter
End-Around
8 possible states, single bit change per state, useful for avoiding glitches
J CLK K
S
R
Q
Q
+
+
+ +
0 1
Shift
Q 1 Q 2 Q 3 Q 4
\Reset
J
K
S
R
Q
Q
J
K
S
R
Q
Q
J
K
S
R
Q
Q CLK CLK CLK
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Shift
Q 1
Q 2
Q 3
Q 4
100
Counters
• Up counter
• Down counter
T
CLK
Q
Q
QAT
CLK
Q
Q
QBT
CLK
Q
Q
QC
Count
T
CLK
Q
Q
QAT
CLK
Q
Q
QBT
CLK
Q
Q
QC
Count
1
1
Counters
• Uo/down counter
T
CLK
Q
Q
QA
T
CLK
Q
Q
QB
Count
1 T
CLK
Q
Q
QC
UP/DOWN
CountersCatalog Counter
74163 Synchronous4-Bit Up counter
Synchronous Load and Clear Inputs
Positive Edge Triggered FFs
Parallel Load Data from D, C, B, A
P, T Enable Inputs: both must be asserted to enable counting
RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"
74161: similar in function, asynchronous load and reset
QAQBQCQD
163RCO
PT
ABCD
LOAD
CLR
CLK2
710
15
9
1
3456
14
1211
13
Counters74163 Detailed Timing Diagram
CLK
A
B
C
D
LOAD
CLR
P
T
Q A
Q B
Q C
Q D
RCO 12 13 14 15 0 1 2
Clear Load Count Inhibit
PresentState
NextState
FlipflopInputs
Counter Design ProcedureIntroduction
This procedure can be generalized to implement ANY finite state machine
Counters are a very simple way to start: no decisions on what state to advance to next current state is the output
Example: 3-bit Binary Upcounter
State TransitionTable
FlipflopInput Table
Decide to implement withToggle Flipflops
What inputs must bepresented to the T FFsto get them to change
to the desired state bit?
This is called"Remapping the Next
State Function"
010
100
C+00011110
Count
\Reset
Q C
Q B
Q A
100
Counter Design ProcedureExample Continued
K-maps for Toggle Inputs:
Resulting Logic Circuit:
Timing Diagram:
T
CLK
\Reset
Q
Q
S
R
QAT
CLK
Q
Q
S
R
QBT
CLK
Q
Q
S
R
QC
Count
+
TB = A
TC = A • B
T A = 1
CB A
C
00 01 11 10
0
1
B
1 1 1 1
1 1 1 1
CB
A
C
00 01 11 10
0
1
B
0 0 0 0
1 1 1 1
CB A
C
B
00 01 11 10
0
1
0 0 0 0
0 1 1 0
Counter Design ProcedureMore Complex Count Sequence
Step 1: Derive the State Transition Diagram000 110
101010
011
Count sequence: 000, 010, 011, 101, 110
Step 2: State Transition Table
PresentState
NextState
C00001111
B00110011
A01010101
C+0X01X10X
B+1X10X10X
A+0X11X00X
Counter Design ProcedureMore Complex Counter Sequencing
Step 3: Choose flip-flop type for Implementation Use Excitation Table to Remap Next State Functions
Toggle ExcitationTable
Remapped Next StateFunctions
PresentState
ToggleInputs
NextState
Q0011
Q+0101
T0110
C00001111
B00110011
A01010101
C+0X01X10X
B+1X10X10X
A+0X11X00X
TC0X01X01X
TB1X01X11X
TA0X10X10X
Counter Design ProcedureMore Complex Counter Sequencing
Step 4: Draw remapped K-Maps
TC
TA
TB
CB
0 0 1 X
X 1 X 0
00 01 11 10
0
1
ACB
1 0 1 X
X 1 X 1
00 01 11 10
0
1
A
CB
0 1 0 X
X 0 X 1
00 01 11 10
0
1
A
TC = A C + A C = A xor C
TB = A + B + C
TA = A B C + B C
Step 5: Obtain minimized logic expressions
Counter Design ProcedureMore Complex Counter Sequencing
Resulting Logic:
Timing Waveform:
TCT
CLK
Q
Q
S
RCount
T
CLK
Q
Q
S
R
TBC
\C
B A
\B \A
TAT
CLK
Q
Q
S
R
\Reset
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
100
Count
\Reset
C
B
A
5 Gates13 (Input Literals + Flip-flop connections)
Step 6: Implement
AC
A\BC
\AB\C
\B
C
TC
TB
TA
Self-Starting CountersStart-Up States
At power-up, counter may be in possible state
Designer must guarantee that it (eventually) enters a valid state
Especially a problem for counters that use a subset of states
Self-Starting Solution:Design counter so that even the invalid states eventually transition to valid state
Two Self-Starting State Transition Diagrams for the Example Counter
Implementationin Previous
Slide!000
010
111
110
101
001 011 100
000
010
111
110
101
001 011 100
Self-Starting Counters
Deriving State Transition Table from Don't Care Assignment
Present State
Next State
C+ 0 1 0 1 0 1 0 1
B+ 1 1 1 0 1 1 0 0
A+ 0 1 1 1 1 0 0 1
C 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
Inputs to Toggle Flip-flops State Changes
State Transition Table
CB
0 0 1 X
X 1 X 0
00 01 11 10
0
1
A
CB
1 0 1 X
X 1 X 1
00 01 11 10
0
1
A
CB
0 1 0 X
X 0 X 1
00 01 11 10
0
1
A
TC
TB
TA
CB
0 1 0 1
1 1 1 0
00 01 11 10
0
1
A
CB
1 1 0 1
1 0 0 1
00 01 11 10
0
1
A
CB
0 0 0 0
1 1 1 1
00 01 11 10
0
1
A
Implementation with Different FF Types
J-K FFs
J-K Excitation Table
Remapped Next State Functions
PresentState
NextState
Remapped Next State
Q+ = J Q + K Q
Q0011
Q+0101
J01XX
KXX10
C00001111
B00110011
A01010101
C+0X01X10X
B+1X10X10X
A+0X11X00X
JC0X01XXXX
KCXXXXX01X
JB1XXXX1XX
KBXX01XX1X
JA0X1XXX0X
KAXXX0X1XX
Implementation with Different FF TypesJ-K FFs Continued
JC = A
KC = A
JB = 1
KB = A + C
JA = B C
KA = C
JC
JA
JB
KC
KA
KB
CB
0 0 X X
X 1 X X
00 01 11 10
0
1
ACB
X X 1 X
X X X 0
00 01 11 10
0
1
A
CB
1 X X X
X X X 1
00 01 11 10
0
1
ACB
X 0 1 X
X 1 X X
00 01 11 10
0
1
A
CB
0 1 0 X
X X X X
00 01 11 10
0
1
ACB
X X X X
X 0 X 1
00 01 11 10
0
1
A
Implementation with Different FF TypesJ-K FFs Continued
Resulting Logic Level Implementation: 2 Gates, 10 (Input Literals + Flip-flop Connections)
CLK CLK CLK J
K
Q
Q
A
\ A
C
\ C KB
J
K
Q
Q
B
\ B
+
J
K
Q
Q
JA
C
A
\ A
B \ C
Count
A C KB JA
Implementation with Different FF Types
• D FFs– Simplest Design Procedure: No remapping needed!
PresentState
NextState
DC
DA
DB
CB
0 0 0 X
X 1 X 1
00 01 11 10
0
1
A
CB
1 1 0 X
X 0 X 1
00 01 11 10
0
1
A
CB
0 1 0 X
X 1 X 0
00 01 11 10
0
1
ADC = A
DB = A C + B
DA = B C
C00001111
B00110011
A01010101
C+0X01X10X
B+1X10X10X
A+0X11X00X
Implementation with Different FF TypesD FFs Continued
DC = A
DB = A C + B
DA = B C
Resulting Logic Level Implementation: 3 Gates, 8 (Input Literals + Flipflop connections)
CLK CLK
D Q
Q
A
\ A
D Q
Q
DA DB B
\ B CLK
D Q
Q
A C
\ C Count
\ C \ A
\ B
B \ C DA DB
Implementation with Different FF Types
• Comparison– T FFs well suited for straightforward binary counters
» But yielded worst gate and literal count for this example!
– J-K FFs yielded lowest gate count» Tend to yield best choice for packaged logic where gate count is
key
– D FFs yield simplest design procedure» Best literal count» D storage devices very transistor efficient in VLSI» Best choice where area/literal count is the key
Asynchronous vs . Synchronous CountersRipple Counters
Deceptively attractive alternative to synchronous design style
Count signal ripples from left to right
State transitions are not sharp!
Can lead to "spiked outputs" from combinational logic decoding the counter's state
Can lead to "spiked outputs" from combinational logic decoding the counter's state
T
Count
Q
QA
T Q
QB
T
CLK
Q
QC
CLK CLK
Asynchronous vs . Synchronous CountersCascaded Synchronous Counters with Ripple Carry Outputs
First stage RCOenables second stage
for counting
RCO assertedsoon after stageenters state 1111
also a functionof the T Enable
Downstream stageslag in their 1111 to
0000 transitions
Affects Count periodand decoding logic
(1) Low order 4-bits = 1111
(2) RCO goes high
(3) High order 4-bits are incremented
Clock
Load
D
C
B
A
100
Asynchronous vs . Synchronous CountersThe Power of Synchronous Clear and Load
Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
Use RCO signal to trigger Load of a new state
Since 74163 Load is synchronous, state changes only on the next rising clock edge
0110is the state
to be loaded
D C B A
L O A D
C L R
C L K
R C O
P T
Q A
Q B
Q C
Q D1
6 3
Load
D C B A
0 1++
Asynchronous vs . Synchronous CountersOffset Counters Continued
Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
Decode state todetermine when to
reset to 0000
Clear signal takes effect on the rising count edge
Replace '163 with '161, Counter with Async ClearClear takes effect immediately!
D C B A
C L R
L O A D
C L KP T
1 6 3
R C O
Q Q Q Q D C B A
CLR
D C B A
1 0
