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L. Dauphinee et al.‚ “A Balanced 1.5 GHz Voltage Controlled Oscillator withan Integrated LC Resonator‚” in IEEE International Solid-State Circuits Conf.(ISSCC)‚ 1997‚ pp. 390–391.

T. Ahrens and T. Lee‚ “A 1.4-GHz 3-mW CMOS LC Low Phase Noise VCOUsing Tapped Bond Wire Inductances‚” in International Symposium on Low-Power Electronics and Design‚ 1998‚ pp. 16–19.

P. G. M. Baltus et al.‚ “A 3.5 mW‚ 2.5 GHz Diversity Receiver and a 1.2 mW‚3.6 GHz VCO in Silicon on Anything‚” IEEE Journal of Solid-State Circuits‚vol. 33‚ no. 12‚ pp. 2074–2075‚ Dec. 1998.

J. Lin‚ “An Integrated Low-Phase-Noise Voltage Controlled Oscillator forBase Station Applications‚” in IEEE International Solid-State Circuits Conf.(ISSCC)‚ 2000‚ pp. 432–433.

B. De Muer et al.‚ “A 1.8 GHz highly-tunable low-phase-noise CMOS VCO‚”in IEEE Custom Integrated Circuits Conf. (CICC)‚ 2000‚ pp. 585–588.

T. Lui‚ “A 6.5 GHz Monolithic CMOS Voltage-Controlled Oscillator‚” in IEEEInternational Solid-State Circuits Conf. (ISSCC)‚ 1999‚ pp. 404–405.

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P. Andreani‚ “A Comparison between Two 1.8GHz CMOS VCOs Tuned byDifferent Varactors‚” in European Solid-State Circuits Conf. (ESSCIRC)‚ 1998‚pp. 380–383.

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A. Pottbacker and U. Langmann‚ “An 8 GHz Silicon Bipolar Clock-Recoveryand Data-Regenerator IC‚” in IEEE International Solid-State Circuits Conf.(ISSCC)‚1994‚ pp. 116–117.

M. Meghelli et al.‚ “SiGe BiCMOS 3.3V Clock and Data Recovery Circuitsfor 10Gb/s Serial Transmission Systems‚” in IEEE International Solid-StateCircuits Conf. (ISSCC)‚ 2000‚ pp. 56–57.

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B. Razavi‚ “A Study of Phase Noise in CMOS Oscillators‚” IEEE Journal ofSolid-State Circuits‚ vol. 31‚ no. 3‚ pp. 331–343‚ Mar. 1996.

J. van der Tang et al.‚ “A 9.8-11.5 GHz I/Q Ring Oscillator for Optical Re-ceivers‚” in IEEE Custom Integrated Circuits Conf. (CICC)‚ 2001‚ pp. 323–326.

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B. Razavi‚ “A 2-GHz 1.6-mW Phase-Locked Loop‚” IEEE Journal of Solid-State Circuits‚ vol. 32‚ no. 5‚ pp. 730–735‚ May 1997.

J. van der Tang and D. Kasperkovitz‚ “A 0.9 -2.2 GHz Monolithic QuadratureMixer Oscillator for Direct-Conversion Satellite Receivers‚” in IEEE Interna-tional Solid-State Circuits Conf. (ISSCC)‚ 1997‚ pp. 88–89.

D. Jeong et al.‚ “CMOS Current-Controlled Oscillators Using Multiple-Feedback-Loop Ring Architectures‚” in IEEE International Solid-State CircuitsConf. (ISSCC)‚ 1997‚ pp. 386–387.

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About the Authors

Johan Van der Tang was born on April 21‚ 1970 in Wolvega‚ the Netherlands.From 1988 until 1992 he studied Electrical Engineering at the Technical College inLeeuwarden (NHL). He subsequently studied Electrical Engineering at the Universityof Twente in Enschede‚ the Netherlands. He successfully concluded his studies atTwente University in 1995 with a M.Sc. project at the Institute for Micro-electronicSystems in Darmstadt‚ Germany. In September 1995 Johan van der Tang started asresearch scientist in the field of integrated transceivers at Philips Research Labora-tories‚ Eindhoven. In this position he worked on analog integrated High-Frequencykey building-blocks for satellite‚ television‚ radio and optical front-ends. In 1996 hejoined the Centre of Technical Training (CTT) of Philips as a part-time lecturer. SinceFebruary 2000‚ Johan van der Tang works as an assistant professor in the Mixed-signal Microelectronics group at Eindhoven‚ University of Technology. In December2002‚ he gained his Ph.D. degree after defending his thesis titled “High-FrequencyOscillator Design for Integrated Transceivers”. For his thesis work he received the“Vederprijs 2002”. His current research interests are design of innovative integratedtransceivers varying from ultra low-power/low-bit rate transceivers to 30 GHz front-ends‚ reusable and programmable RF building blocks‚ and design methodology foranalog RF circuits.

Dieter Kasperkovitz got his B.Sc. in Mechanical Engineering‚ his M.Sc. in Experi-mental Physics and his Ph.D. in Theoretical (Nuclear) Physics in Vienna‚ Austria. Be-fore starting his industrial career he was engaged in a Postdoctoral Fellowship in SolidState Physics at the University of Cologne‚ Germany. He started his work at PhilipsResearch in Eindhoven‚ the Netherlands‚ with the design of new functional deviceslike ultra-fast switches and IMPATT oscillators‚ bi-stable elements‚ image sensors‚etc. Supporting innovative projects for the consumer market he designed the first digi-tal tuning system for TV tuners. Other areas of interest were serial and random access

311

312 About the Authors

mass memories‚ fully integrated FM receivers and Paging Receivers. Before his re-tirement from Philips Research he was also involved in the design of new architecturesfor integrated transceivers‚ in the development and evaluation of new technologies forRF-IC’s‚ and in adaptive signal processing for transmission channels with high levelsof noise and spurious signals. After retirement he co founded the innovative IC designcompany Semiconductor Ideas to the Market (ITOM).

Arthur H.M. van Roermund was born in Delft‚ The Netherlands in 1951. He re-ceived the M.Sc. degree in electrical engineering in 1975 from the Delft Universityof Technology and the Ph.D. degree in Applied Sciences from the K.U.Leuven‚ Bel-gium‚ in 1987. From 1975 to 1992 he was with Philips Research Laboratories inEindhoven. From 1992 to 1999 he has been a full professor at the Electrical Engi-neering Department of Delft University of Technology‚ where he was chairman of theElectronics Research Group and member of the management team of DIMES. From1992 to 1999 he has been chairman of a two-years post-graduate school for chartereddesigner. From 1992 to 1997 he has been consultant for Philips. October 1999 hejoined Eindhoven University of Technology as a full professor‚ chairing the Mixed-signal Microelectronics Group. Since September 2002 he is member of the facultyboard‚ with research portfolio. He is chairman of the board of ProRISC‚ a nation-widemicroelectronics platform‚ and senior member of the IEEE. Specific areas of interestcurrently are AD and DA conversion and high-frequency transceivers.

Index

Symbols1 / f noise‚ see flicker noise

noise‚ see white noise floornoise‚ see phase noisenoise‚ see flicker noise

see phase noise to carrier ratio

AAAC‚ see Automatic amplitude con-

trolAC phase noise simulation‚ 202ACPN‚ 202

example‚ 208‚ 211principle‚ 203simulation flow‚ 207

Active inductance‚ 149AGC‚ see Automatic gain controlAmplitude noise

multiplicative‚ 16removal‚ 16

Amplitude stabilization‚ 30‚ 203automatic gain control‚ 34modeling‚ 203self-limiting‚ 31

Analog circuit design‚ 38Automatic gain control‚ 34

BBalanced design‚ 80Barkhausen‚ 6

Barkhausen conditions‚ 22Behavior modeling

building blocks‚ 257Benchmark FOMs‚ 190

LC oscillator design efficiency‚ 195Normalized phase noise‚ 191Oscillator number‚ 191Ring oscillator design efficiency‚

197Breakdown‚ 83Buffers‚ 80

CCarrier amplitude

current limited‚ 179ideal‚ 108practical‚ 178saturation‚ 179voltage limited‚ 180

Carrier powerideal‚ 108practical‚ 178

Carrier to phase noise ratio‚ 71CCO‚ see Oscillator‚ CCOChristian Huygens‚ 1Circuit optimizers‚ 46

algorithms‚ 46analysis types‚ 47

Classification‚ see Oscillator‚ classifi-cation

313

314 Index

Closed-loop gain‚ 204Colpitts oscillator‚ 26

noise shifting‚ 176phase noise‚ 174

Complementary error function‚ 79Component mismatch‚ see device mis-

matchCrystal oscillator‚ 11Current limited region‚ 179

DDCR‚ 5‚ 242

half-rate‚ 242DECT‚ 3Design FOMs‚ 186

188frequency‚ 187tuning‚ 188

Design methods‚ 44expert systems‚ 47Figures of Merit‚ 49‚ 51FOM-based design‚ 50optimization tools‚ 46synthesis environments‚ 47trial-and-error‚ 45

Design phases‚ 40optimization and implementation‚

41specification and conceptualization,

41verification and documentation‚ 41

Design resources‚ 38‚ 40capitalization‚ 40

Device mismatch‚ 85Dielectric Resonator Oscillator (DRO)‚

19Differential pair‚ 261Distributed oscillators‚ 11

literature‚ 11Double loop PLL‚ 226Dynamic selectivity‚ 74

EElectrical energy‚ 90

FFDMA‚ 3Feedback modeling‚ 21

limitations‚ 22Figures of Merit‚ 51

benchmark FOMs‚ 55‚ 190normalized phase noise‚ 191oscillator design efficiency‚ 193oscillator number‚ 191

benefits‚ 56design FOMs‚ 53‚ 186

188frequency‚ 187tuning‚ 188

design margin‚ 56Flicker noise

corner‚ 72corner calculation‚ 176device 1/ f corner‚ 175reduction‚ 172region‚ 72

FM modulationsignal-to-noise ratio reduction‚ 76

FM radio‚ 142‚ 216FOM‚ see Figures of MeritFrequency‚ 113Functional specifications‚ 38‚ 39

inequality constraint‚ 39

GGSM

phase noise specification‚ 75type-approval template‚ 76

HHalf-circuit concept‚ 62Harmonics‚ 101

even‚ 17odd‚ 17

Hartley oscillator‚ 27Hartley receiver architecture‚ 82Heuristics‚ 42

II/Q matching‚ 81‚ 231

Index 315

I/Q signals‚ see Quadrature signalsIdeal limiter‚ 261Image rejection ratio‚ 81

formula‚ 82Impulse sensitivity function‚ 174

effective‚ 175Inductor choice‚ 189INSPEC‚ 8

LLC oscillator

circuit examples‚ 115complementary MOS‚ 117cross-coupled bipolar‚ 115design example‚ 216‚ 233differential equation‚ 90frequency deviation‚ 92ideal

behavioral model‚ 91frequency‚ 91multi-phase‚behavioral model‚

94multi-phase‚frequency‚ 95multi-phase‚tuning‚ 100multi-phase‚ waveform‚ 103tuning‚ 99waveform‚ 102

multi-phase‚circuit example‚ 122multi-phase,coupling strength‚ 120multi-phase,implementation exam-

ple‚ 164multi-phase‚multi-oscillation‚ 163

multi-phase‚optimal coupling‚ 162performance overview‚ 275practical

behavioral model‚ 113frequency‚ 113‚ 114multi-phase‚behavioral model‚

119multi-phase‚frequency‚ 118multi-phase‚operation‚ 119multi-phase‚phase noise (LTI)‚

161phase noise (LTI)‚ 156‚ 281phase noise (LTV)‚ 169waveform‚ 177

quality factor‚ 151LC Tank‚ see ResonatorLeeson‚ 155Leeson’s formula‚ 156LO leakage‚ 226Lorentz-function‚ 205Lorentzian‚ 206

MMagnetic energy‚ 90Marconi‚ 2Measurement

buffer isolation‚ 81Modeling

behavioral building blocks‚ 62behavioral level‚ 61circuit level‚ 63single-ended models‚ 62system level‚ 58transistor models‚ 64

MOS-varactor‚ see Varactor‚ MOS-typeMulti-oscillation‚ 27

elimination‚ 28Pierce oscillator‚ 27

Multi-phase LC oscillator‚ see LC os-cillator

Multi-phase ring oscillator‚ see Ringoscillator

JJitter‚ 16‚ 77

cycle-to-cycle‚ 77definition‚ 77generation‚ 78in PLLs‚ 77peak-to-peak‚ 79relation to 77rms‚ 79SONET(SDH)‚ 77unit intervals‚ 77

316 Index

NNarrow range system‚ 68Negative resistance modeling‚ 29Negative resistance oscillator‚ 29Noise shaping‚ 59

formula‚ 59Q definition‚ 59

NRZ data stream‚ 5

OOpen loop

gain‚ 24simulations‚ 24

Open loop gain‚ 24modeling‚ 203relation to phase noise‚ 161

Open loop transfer function‚ 26Oscillation conditions‚ 21

application‚ 23Barkhausen conditions‚ 22Bode plots‚ 25feedback modeling‚ 21gain condition‚ 22modeling limitations‚ 22negative resistance modeling‚ 29‚

30phase condition‚ 22root locus‚ 26start-up conditions‚ 23steady-state‚ 22

Oscillatorapplications‚ 3benchmarking‚ 190carrier amplitude‚ 108‚ 178carrier power‚ 108‚ 178CCO‚ 14classification‚ 17comparison‚ 190design examples‚ 215elementary properties‚ 89FM radio‚ 142frequency‚ 113ideal‚ 13‚ 90implementation principle‚ 17

inductor choice‚ 189Latin origin‚ 1layout‚ 9literature‚ 6LO‚ 3non-ideal‚ 15non-resonator based‚ 19output buffer‚ 80phase noise

LTI modeling‚ 155LTV modeling‚ 169

power dissipation‚ 181practical properties‚ 111resonator based‚ 17specifications‚ 67supply voltage‚ 181switching‚ 152tuning‚ 132tuning constant‚ 70VCO‚ 14waveform‚ 101‚ 177

Oscillator design efficiency‚ 193

PParasitic oscillations‚ 28Perpetuum mobile‚ 91Phase noise

slope‚ 72slope‚ 72

AC based simulation‚ 202AM-PM conversion‚ 170bipolar LC oscillator (LTI)‚ 156CML ring oscillator (LTI)‚ 168Colpitts oscillator‚ 174cross-coupled LC oscillators (LTV)‚

173dependency on Q‚ 160down-conversion‚ 171extrapolation‚ 72inductor choice‚ 189Leeson‚ 156LTI modeling‚ 59‚ 155LTV modeling‚ 169measurement‚ 72

Index 317

MOS LC oscillator (LTI)‚ 157noise source modulation‚ 172non-linear mechanisms‚ 170nonlinear modeling‚ 169optimum no. of ring oscillator stages‚

169power law curves‚ 71power spectral density‚ 71relation to loop gain‚ 161resulting angular phase deviation‚

73saturation effects‚ 172sidebands‚ 16simulation‚ 201single-sideband‚ 71switching diff. pair‚ 159tail noise filtering‚ 172up-conversion‚ 170voltage limited region‚ 180waveform symmetry‚ 176

Phase noise to carrier ratio‚ 71definition‚ 71dependency on power‚ 160LTI modeling‚ 155LTV modeling‚ 169valid region of 73

PLL‚ 11literature‚ 11

PN-junction varactor‚ see Varactor‚ PN-junction type

Pole locations‚ 30Pulling‚ 80

QQ‚ see Quality factorQuadrature signals‚ 15‚ 82

correct-by-construction‚ 82generation methods‚ 265

Quality factor‚ 25‚ 255active inductance‚ 149active varactor‚ 145at resonance‚ 60capacitor‚ 113frequency deviation‚ 114

inductor‚ 113LC oscillator‚ 281loaded‚ 117multi-phase oscillator‚ 61‚ 151‚ 161ring oscillator‚ 198‚ 287single-phase oscillator‚ 59switched capacitor‚ 141two-integrator oscillator‚ 166‚ 287visualization‚ 255

RReciprocal mixing‚ 74Relaxation oscillators‚ 11‚ 20

literature‚ 11Residual FM‚ 75Resonator

choice‚ 10energy storage‚ 25phase shift‚ 162practical model‚ 114quality factor‚ 10‚ 25

Ring oscillator‚ 97benchmarking‚ 251

circuit examples‚ 130design example‚ 242effective Q factor‚ 198frequency estimation‚ 129frequency when switching‚ 267ideal

behavioral model‚ 97frequency‚ 98tuning‚ 101waveform‚ 106

optimum number of stages‚ 169performance overview‚ 279practical

behavioral model‚ 128frequency‚ 129phase noise (LTI)‚ 165‚ 287phase noise (LTV)‚ 169tuning‚ 152waveform‚ 177

Q factor‚ 167time delay MOS stage‚ 132

318 Index

time-delay CML stage‚ 131two-stage topologies‚ 244

SSatellite receiver‚ 225SDH‚ 69Self-limiting‚ 31

cross-coupled differential pair‚ 32Self-reception‚ 226Settling time‚ 32Silicon on Anything‚ 216‚ 217

inductor Q‚ 219varactor Q‚ 220

Simulation‚ 201ACPN‚ 202

advantages‚ 202example‚ 208‚ 211flow‚ 207limitations‚ 203principle‚ 203

phase noise‚ 201pnoise analysis‚ 201PSS analysis‚ 201

SONET‚ 69Specifications‚ 67

carrier amplitude‚ 80carrier power‚ 80center frequency‚ 68chip area‚ 86design spec.‚ 67frequency‚ 68frequency grid‚ 68I/Q matching‚ 81jitter‚ 77nominal spec.‚ 67peak-to-peak jitter‚ 79phase noise to carrier ratio‚ 71power dissipation‚ 83process spread‚ 70‚ 84reciprocal mixing‚ 74rms jitter‚ 78SNR degradation‚ 75spurious emission‚ 76supply pushing‚ 83

supply voltage‚ 83technology‚ 86temperature‚ 84tuning constant‚ 70tuning range‚ 68unit intervals‚ 77waveform‚ 79

Spectral purity‚ 16Spurious emission‚ 76Stability

definition‚ 71long term‚ 5‚ 11short term‚ 5‚ 71

Start-up conditions‚ 23Supply pushing‚ 83

formula‚ 84Syntonic Wireless Telegraphy‚ 2

TTank circuit‚ see ResonatorThermal resistance‚ 85

formula‚ 85Three-terminal oscillator‚ 26Timing reference‚ 13Transconductor

limiting characteristic‚ 92‚ 261piece-wise linear‚ 93

Transistorbipolar 272bipolar 272generic model‚ 271MOS 272MOS 272simplified models‚ 271

Tuning‚ 132active capacitive‚ 144active inductive‚ 149band-switching‚ 140capacitor switching‚ 140delay interpolation‚ 153LC oscillators‚ 133oscillator switching‚ 152passive inductive‚ 147phase shift tuning‚ 150

Index 319

resistive‚ 153ring oscillator‚ 152two-integrator oscillator‚ 152varactor implementations‚ 136varactor tuning‚ 133

Tuning constant‚ 70linearity‚ 70too high‚ 140

Two-integrator oscillatorAGC‚ 35circuit example‚ 125design example‚ 225frequency estimation‚ 126ideal‚ 95

behavioral model‚ 96frequency‚ 96tuning‚ 101waveform‚ 106

practicalbehavioral model‚ 123frequency‚ 124phase noise (LTI)‚ 165‚ 287phase noise (LTV)‚ 169tuning‚ 152waveform‚ 177

Q factor‚ 166V/I converter‚ 127‚ 229

UUMTS‚ 69

VV/I converter‚ 127‚ 229Van der Pol‚ 6Van der Pol oscillator‚ 32

differential equation‚ 32output voltage‚ 32settling time‚ 32

Varactor133

active variable capacitance‚ 144‚236

compound‚ 134compound Q‚ 135

effective Q‚ 145measured performance‚ 139MOS-type‚ 136‚ 138‚ 233PMOS‚ 236PN-junction type‚ 135–137‚ 235

VCO‚ see Oscillator‚ VCOVCO gain constant‚ see tuning constantVHDL‚ 38Voltage limited region‚ 179

WWaveform‚ 101

relation to 1 / f corner‚ 176White noise floor‚ 16Wide range system‚ 68