References - Springer978-0-306-47014... · 2017-08-25 · References 193 [18] B. Ricco, R. Versari and D. Esseni, "Characterization of polysil-icon depletion effect and its impact

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Appendix A AN EXPLICIT EXPRESSION FOR ψ s IN A MOS ACCUMULATION CAPACITOR

In order to find an explicit expression for ψ s in terms of VGB, werewrite (2.23) as

Working with normalized variables

we have

(A.1)

(A4

(A.3)

04.4)

(A.5)

We need to find x in terms of z. Notice that the only parameter in the equation is a. If we could find an approximate explicit equation for x for practical values of a, the surface potential will "track" changesin substrate doping concentration and temperature. Then, the model formulation is based entirely on the physics of the device, and is devoid of function fitting for particular values of process parameters and temperature.

200 HIGH FREQUENCY CONTINUOUS TIME FILTERS

As a guide towards an approximation, we consider the asymptotic behavior of (A.5). For small x, the exponential can be approximated by the first three terms of its Taylor expansion, whereas for large x itbecomes dominant. Thus, we obtain

small xlarge x

(A.6)

Inverting these relations, we obtain:

(A.7)small z

large z

The second factor in these relations can be approximated by log(1 + z/a), for both small and large z. The first factor is typically 1 for small z, and becomes 2 for large z. This behavior can be satisfied by the

function 2 , with k1 and k2 typically being 3 and 6, respectively. Thus the behavior in (A.7) can be approximated by:

(A.8)

Although this relation was developed from the asymptotic behav-ior of (AS), we find that it approximates the latter well for the entire useful range of z and for typical values of a, when k1 = 3 and k2 = 6 are chosen. Thus, rewriting (A.8) by using (A.2–A.4), we obtain (2.25).

Appendix B CALCULATION OF THE BIAS VOLTAGE AT WHICH dCGB——dVGB

In this appendix we calculate an aproximate value for VGB atwhich the C–V curve has a "flat-top" (dCGB—–dVGB

) = 0). Let this occur for a VGB = VGB0. Differentiating (2.48), we get

(B.1)

For typical process parameters, when VGB = VGB0, VGB0 >> ψs >>φ t. Hence, (2.29) and (2.25) can be approximated as

and

Using (B.3) in (B.2), we get

Using (2.50),

(B.2)

03.3)

03.4)

03.5)


Figure B.1 Simulation of the effect of finite polysilicon doping on C–V characteristics.

From (B.3),

This leads to

From (B.4),

or

(B.6)

(B.7)

(B.8)

Assuming that << 1 (we are only interested in estimatingVGB 0 ) and using (B.7) and (B.8) in (B.1), we get

03.9)

(B.10)

Appendix B: CALCULATION OF THE BIAS VOLTAGE AT WHICH dCGB—dVGB= 0 203

The above relation is within a few hundred millivolts of an accurate value obtained from simulations. Figure B.1 shows the C-V curve of a MOS capacitor in accumulation, as its gate doping is progressively reduced. Notice that the "flat-top" occurs at lower biasvoltages as the gate doping concentration is reduced.

Appendix C SUMMARY OF THE PROPERTIES OF A DISTRIBUTED RC LINE

We summarize the properties of a one-dimensional uniformly distributed RY (URY )

——structure. The meaning of URY

——is illustrated

Figure C.1. A uniformly distributed RY line.


Figure C.2. Admittance of a URY——

line contacted at both ends.

in Figure C.1. The line has a total resistance R and total admittance Y, distributed as shown in Figure C.1(a). Notice that Y(s) is the value of Yi(s) when R is zero (Figure C.1(b)). R is the total resistance of the line (Figure C.1(c)). In Figure C.2, the URY network is contacted at both ends. This is relevant to the way contacts are made to the capacitor plates, as in Figure 2.15a. For this connection, it can be shown that the driving point admittance Yi(s) is [21]

————

(C.1)

Appendix D SMALL SIGNAL MOS TRANSISTOR MODELS

In this appendix we review the small-signal equivalent circuit for the MOS transistor [16]. First, we consider the device part between the source and drain, containing the inversion layer, the depletion region, the oxide and the gate. This part is shown as the part within broken lines in Figure D.1 and is called the intrinsic part of a transistor. The rest of the device is called the extrinsic part and is responsible for parasitic effects.

1. OPERATION IN STRONG INVERSION AND SATURATION

The DC model for the device in is given to first order by

where

(D.1)

(D.2)

(D.3)

where a is a process dependent quantity somewhat larger than 1, and all other terms have their usual meanings. For low and medium frequencies, the model for the transistor is shown in Figure D.2. The values of the various quantities in Figure D.2 in terms of the terminal voltages, currents and physical parameters are [16]

(D.4)


Figure D.1. The intrinsic part of an MOS transistor.

Figure D.2. A simple quasistatic model for the MOS transistor.

(D .5 )

(D.6)

(D.7)

(D.8)

(D.9)

Appendix D: SMALL SIGNAL MOS TRANSISTOR MODELS 209

Figure D.3. MOS transistor model in the off condition.

2.

D.3. In that figure

MODEL WHEN THE DEVICE IS OFF When the device is off, the small signal model reduces to Figure

(D.10)

3. EXTRINSIC PARASITES The extrinsic parasitic capacitors near the drain of a transistor

are shown in Figure D.4. Cdb is the depletion capacitance between the drain contact and the substrate. Cgd is the physical overlap capacitance between the gate and the drain. Similar capacitances exist at the source end of the transistor. An important thing to notice is that Cgd and Cdb stay the same irrespective of whether the transistor is on or off as long as the gate and drain are maintained at the same potential. Figure D.5 shows the complete model for the MOSFET. All extrinsic capacitors have the subscript 'e'. Csde can also account for any wiring overlap capacitance between the source and the drain .


Figure D.4. Extrinsic parasitic capacitors near the drain.

Figure D.5. Extrinsic transistor capacitances added to an intrinsic model.

Appendix E CALCULATION OF THE STEADY STATE WAVEFORM OF THE FILTER COMPARATOR OSCl LLATOR

For this analysis, the reader is referred to Figure 8.11. We use T = 2 t1 from (8.18), and denote by k, the even integer 2 m. Then,from (8.17), we get,

(E.1)

Using a change of variables, and keeping in mind that k is even, for τ < t1 (E.1) can be written as follows:

(E.2)

In order to avoid unwieldy expressions, and in preparation for the development that follows , we use the notation

(E.3)

Equation (8.8) for t = τ + nt1 becomes, using (8.11) and (E.3):


Using (E.4) in (E.2), and noting that (–1)n sin(x + nπ ) = sin(x), we

get

or, using (8.11) ;

(E.5)

To calculate the steady state response, we allow k to increase. In the limit, replacing the sum by an infinite sum, and using

, |x| < 1

the right hand side of (E.6) becomes

, 0 < τ < t1

(E.7)

(E4

It is obvious from Figure 8.10 that for t1 < τ < 2t1, the steady stateresponse shape is the same as in the interval 0 < τ < t1, except for asign inversion. Thus, (8.19)–(8.22) in Section 4. hold, where T is as in (8.18).

Index

CMOS, 48 Layout Gm-C, 42 Balanced, 120 Gm-OTA-C, 46, 149 Biquad, 120 MOSFET-C, 37 Monte Carlo, 102 Mismatch, 100Nauta’s technique, 149 Accumulation, 8, 12 Binary weighted, 98 Biquad, 34 Butterworth filter, 95

Capacitors Noise spectrum, 138

Offsets due to, 101

current factor, 100 oxide-thickness dependence of, 100 threshold voltage, 100

Mixed nodal analysis (MNA), 80 Noise in constant-conductance scaled

quality factors in a, 95

Depletion, 118 Nonlinear capacitor, 6 Empirical formula for interconnect, 118 Interconnect, 118 Phase error, 34

Constant-capacitance scaling Implementation of, 91 Programmability, 56

Constant-conductance scaling Implementation of, 90 Read-channel, 1

Crossmodulation, 87 Degeneration, 49 Scaled networksDepletion, 28Disc-drive, 1 Nonlinear, 79 Distortion in scaled networks, 87 Distortion, 7, 31, 86

Dynamic range, 56, 89 Excess noise factor, 50, 53–54 Excess phase, 65 Feedthrough, 133 Transconductor, 98 Flatband voltage, 18 Gate overdrive, 103 Integrator, 34 gain of, 98 Intermodulation, 87 Transconductors, 48 Inversion, 8

networks, 76

Passband, 136

Polysilicon gate depletion, 19

Quality factor, 28, 33

Right half plane zero, 38

Noise properties of, 75

Properties of, 73 Scaling, 72

Measured filter, 143 constant-capacitance, 74 constant-conductance, 74

Scattering parameters, 135 Surface potential, 10

Modified Nauta, 152 constant capacitance scaled, 92

Triode operated MOSFETs, 51

Documents

References - Springer978-0-306-47014... · 2017-08-25 · References 193 [18] B. Ricco, R. Versari and D. Esseni, "Characterization of polysil-icon depletion effect and its impact