http://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/Challenges and tradeoffs of SOC vs SIP (Challenges and Trade-offs of SOC vs SIP SESSION 5)http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1358735Past present and futureTimeline: http://www.computerhistory.org/semiconductor/timeline.htmlhttp://www.mckinsey.com/~/media/mckinsey/dotcom/client_service/Semiconductors/Issue%204%20Autumn%202014/PDFs/MoSC2014_Advanced-packaging_technologies_The_implications_for_first_movers_and_fast_followers.ashxProcess flow SIP https://www.ll.mit.edu/mission/electronics/qiin/cmos-technology/3d-integration-of-CMOS.htmlSOP paper(2004 Electronic Components and Technology Conference)http://users.ece.gatech.edu/~etentze/ECTC2004_Sundaram.pdfSystem-on-a-Package (SOP) Substrate and Module with Digital, RF and Optical Integration Venky Sundaram*, Rao Tummala, George White, Kyutae Lim, Lixi Wan, Daniel Guidotti, Fuhan Liu, Swapan Bhattacharya, Raj M. Pulugurtha, Isaac Robin Abothu, Ravi Doraiswami, Raghuram V. Pucha, Joy Laskar, Manos Tentzeris, G. K. Chang, Madhavan Swaminathan Packaging Research Center, Georgia Institute of Technology * vsunda@ece.gatech.edu, 404-894-9394, 404-894-3842 (Fax)

Packaging types imageshttp://web.ece.ucdavis.edu/~bbaas/116/notes/Handout.packaging.pdfPresentation by Dr Jones FIU http://web.eng.fiu.edu/~jonesweb/EML%204561-%20spring%2010/EML%204561-PackagingOverview-Electrical.pptxweb.eng.fiu.edu

System in Package trendshttp://www.springer.com/cda/content/document/cda_downloaddocument/9783642285219-c2.pdf?SGWID=0-0-45-1338322-p174307159TSV Manufacturing Yield and Hidden Costs for 3D IC Integrationhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5490828978-1-4244-6412-8/10/$26.00 2010 IEEE2010 Electronic Components and Technology Conference

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