Reference System: OPB PCI · The ALi M1535D+ South Bridge interfaces to the legacy devices, including the audio, modem, USB, and IDE ports. PCI-to-PCI Bridge TI2250 Intel 10/100 Ethernet

XAPP911 (v1.0.2) Jan 27, 2006 www.xilinx.com 1

© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.All other trademarks are the property of their respective owners.

Summary This application note describes how to build a reference system for OPB PCI using theIBM®PowerPC405™ processor (PPC405) based embedded system in the ML310 EmbeddedDevelopment Platform. The reference system uses three pcores. A set of files containing XilinxMicroprocessor Debugger (XMD) commands is provided for writing to the Configuration SpaceHeader and verifying that the ML310 is operating correctly. Several software projects illustratehow to configure the OPB PCI core, set up interrupts, scan the configuration registers, and setup and use DMA operations. The procedure for using ChipScope™ to analyze OPB PCIfunctionality is provided. The steps used to build a Linux kernel using MontaVista™ are listed.

IncludedSystems

This application note includes one reference system:

• www.xilinx.com/bvdocs/appnotes/xapp911.zip

Introduction This application note accompanies a reference system built on the ML310 development board.The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB PCIcore. Figure 1 is a block diagram of the reference system.

Although this reference system targets the ML310 board, it can be modified to work on anyother board that contains an FPGA and a PCI card slot.

The ML310 board design provides the Virtex-II™ Pro XC2VP30 access to two 33 MHz/32-bitPCI buses: a primary 3.3V PCI bus and a secondary 5.0V PCI bus. The FPGA is directlyconnected to the primary 3.3V bus. The 5.0V PCI bus is connected to the Primary PCI bus viaa PCI-to-PCI bridge. The PCI devices and four PCI add-in card slots on the ML310 are listed inTable 1. The Memec Spartan-II™ 2S200 PCI Board is inserted into slot 3. All PCI bus signalsdriven by the XC2VP30 comply with the I/O requirements in the PCI Local Bus Specification,Revision 2.2.

Application Note: OPB PCI Reference System: Embedded Processing

XAPP911 (v1.0.2) Jan 27, 2006

Reference System: OPB PCIR

Figure 1: OPB PCI Reference System Block Diagram

PPC405

PLBDDR

OPBUART16550

OPBGPIO

OPBPCI

OPBINTC

PLB

OPB

OPBSYSACE

PLBBRAM

http://www.xilinx.com

2 www.xilinx.com XAPP911 (v1.0.2) Jan 27, 2006

IntroductionR

The majority of the ML310 features are accessed over the 33 MHz/32-bit PCI bus. The Virtex-II Pro Platform FPGA contains PPC405 processors which access the primary PCI bus throughthe OPB PCI Bridge. The PCI configuration in this reference design uses the OPB PCI Bridge.

Figure 2: PCI Bus Devices on ML310

Figure 2 shows PCI Bus Devices on the ML310. The TI2250 device is a PCI-to-PCI bridge tothe two 5V PCI slots. The Intel GD82559 10/100 Ethernet NIC is used to connect to an Ethernetport. The ALi M1535D+ South Bridge interfaces to the legacy devices, including the audio,modem, USB, and IDE ports.

PCI-to-PCIBridge TI2250

Intel 10/100Ethernet NIC

5.0V PCI Slot 6

5.0V PCI Slot 4

Virtex-II ProFPGA

XC2VP30

ALi Southbridge

IDSELIDSEL

0xAC23 104C

0x1229 8086

0x5451 10B9Dev ID Vend IDIDSEL

0x1533 10B9

0x5457 10B9

0x5237 10B9

0x5229 10B9

0x5237 10B9

PCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

USB#1

PCI_BUS

PCI Bus

PCI_S_AD18

PCI_S_CLK0

PCI_S_AD19PCI_P_AD25PCI_P_AD24

3.3V

PCI_P_CLK5PCI_P_CLK4PCI_P_CLK0PCI_P_CLK1PCI_P_CLK2PCI_P_CLK3

PCI_S_CLK1

3.3V PCI Slot 5

3.3V PCI Slot 3

PCI_P_AD21

PCI_P_AD22

PCI_P_AD23

PCI_P_AD31IDE Bus

PCI_P_AD27USB#2

PCI_P_AD26Modem

PCI_P_AD19S. Bridge

PCI_P_AD18Audio

PCI_P_AD17

5.0V

U32

U37

U15

U11

UG068_11_090204

Memec2S200


Introduction


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Figure 3: ALI Bus - PCI to Legacy Devices

Figure 3 shows the connections of the South Bridge to the legacy devices.

The functions, devices, and buses in the OPB PCI reference design defined in Figures 2 and 3are addressed using the Configuration Address Port defined in Figure 4.

Figure 4: Configuration Address Port format

The Configuration Address Port and Configuration Data Port registers in the Virtex-II Pro OPBPCI Bridge can be used to configure multiple PCI bridges when host bridge configruation isenabled.

PCI_P_AD31

PCI_P_AD27

PCI_P_AD26

PCI_P_AD19

PCI_P_AD18

PCI_P_AD17

ALiSouth Bridge

OSC32.768

MHz

X4

OSC

48MHz

X2

OSC14.3181

MHz

X3

OSC

24.576MHz

X1

AC97

U1

USB1

USB2

ParallelPort

PS/2KBD

GPIO FLASHPRIMARY IDE

SECONDARY IDE

SERIAL1

SERIAL2

FPGA

PCI_P_AD24

PCI_P_CLK3

PCI_BUS

IDSEL

U37

U15

J3 P1 P2 J5 U4 J16/J15

PCI_BUS

Device ID Vendor IDIDSEL

0x5451

0x1533

0x5457

0x5237

0x5229

0x5237

0x10B9

0x10B9

0x10B9

0x10B9

0x10B9

0x10B9USB#1

IDE Bus

USB#2

Modem

S. Bridge

Audio

UG068_12_090204

Reserved Bus No. Device No.FunctionNumber DoublewordE



Reference System SpecificsR

ReferenceSystemSpecifics

In addition to the PowerPC processor and OPB_PCI, this system includes DDR and BRAMmemory on the PLB and a UART, interrupt controller, Sysace, and GPIO on the OPB. SeeFigure 1 for the block diagram. The FPGA provides the PCI Arbiter.

Table 1 provides the addresses of the IDSEL lines on the ML310 Board.

Table 1: ML310 PCI Devices - IDSEL lines

ML310 XC2VP30 Address Map

Table 2 provides the address map of the ML310 XC2VP30.

The reference design contains the following settings for OPB PCI generics:

C_INCLUDE_PCI_CONFIG = 1C_INCLUDE_BAROFFSET = 0C_DMA_CHAN_TYPE = 0C_NUM_IDSEL = 16C_IPIFBAR_NUM = 4C_PCIBAR_NUM = 1

The C_INCLUDE_PCI_CONFIG generic configures the bridge as a host bridge. WhenC_INCLUDE_BAR_OFFSET = 0, the C_IPIFBAR2PCIBAR_* generic(s) are used in addresstranslation instead of registers. Setting C_DMA_CHAN_TYPE = 0 is used for simple DMA.C_IPIFBAR_NUM defines 4 address ranges for OPB to PCI transactions andC_PCIBAR_NUM defines 1 address range for PCI to OPB transactions

Device IDSEL Address

South Bridge (Ali M1535D+) AD18

Intel EMAC (GD82559) AD23

TI Bridge (TI2250) AD25

3.3V PCI Slot 3 (S2 Board) AD22

3.3V PCI Slot 5 (Empty) AD21



Table 2: ML310 XC2VP30 System Address Map

Peripheral Instance Base Address High Address

PLB_DDR plb_ddr2_0 0x00000000 0x0FFFFFFF

OPB GPIO opb_gpio_0 0x90000000 0x900001FF

OPB UART16550 opb_uart16550_0 0xA0000000 0xA0001FFF

OPB INTC opb_intc_0 0xD0000FC0 0xD0000FDF

OPB_PCI opb_pci_1 0x3C000000 0x3C0001FF

PLB BRAM plb_bram_if_cntlr_0 0xFFFF8000 0xFFFFFFFF

OPB SYSACE opb_sysace_0 0xCF000000 0xCF0001FF


Reference System Specifics


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The misc_logic_v1_00_a pcore is used to control PCI reset after power up, setting the PCIreset Low after the FPGA provides a stable PCI clock. It also handles the external PCIinterrupts.

Several clocks are distributed on the ML310 board as defined by the clocks_v1_00_c pcore.The main system clock is a 100 MHz oscillator. The clocks_v1_00_c pcore uses four Virtex-IIPro Digital Clock Managers (DCMs) to provide PPC405, Dual Data Rate (DDR) controller, andPCI clocks. Setting the CLKFX_MULTIPLY attribute = 3 in DCM1 provides the 300 MHzclkcpu_i to the PPC405. DCM3 is used for the DDR clocking. To change the clock frequency,edit the CLKFX_MULTIPLY and/or CLKDV_DIVIDE attributes in clocks.v.

The my_jtag_logic_v1_00_a core facilitates debugging.

Figure 5 provides a functional diagram of the OPB PCI Full Bridge core. The three functions ofthe core are the OPB IPIF, the v3.0 PCI LogiCORE, and the IPIF/v3 Bridge.

Figure 5: Block Diagram of OPB PCI Bridge core

EndianessTranslation

AddressTranslation

IPMaster SM

InterruptModule

OptionalDMA

MasterAttach

SlaveAttach

ResetModule

PCI2IPIFFIFO

IPIF2PCIFIFO

EndianessTranslation

TargetSM

PCIInitiator SM

AddressTranslation

IPIFSlave SM

IPIF/V3 BridgeIPIF

C_INCLUDE_PCI2OPB_SLV

C_INCLUDE_OPB2PCI_TARG

OP

B B

us

V3Core

PC

I Bus

DS437_01




Memec Design Spartan-II 200 PCI Development Board

The OPB PCI in the 2VCP30 on the ML310 board can interface to the OPB PCI in the S200 onthe Memec Design 200 PCI board(1). The Memec board uses the 200K gate Xilinx Spartan-IIdevice (XC2S200-6FG456C) in the 456 fine-pitch ball grid array package. The<opb_pci_proj>/memec_design contains the system.mhs and other project files for thisreference design.

Table 3 provides the address map for the 2S200.

Figure 6: Memec Design Spartan-II Development Board

Figure 6 shows the Spartan-II Development board. The board includes two clock sources, a 32-bit PCI edge connector, 8 MB SDRAM memory, RS232C port, LED displays, ISP PROM, anda JTAG port. The MicroBlaze microprocessor is used in this design.

1. Memec has been acquired by Avnet, Inc.

Table 3: 2S200 Address Map

Peripheral Instance Base Address High Address

OPB BRAM opb_bram_if_cntlr_1 0x7000000 0x700007FF

OPB Uartlite opb_uartlite_0 0x30000000 0x300000FF

OPB PCI opb_pci_1 0x1A000000 0x1A00007F

OPB SDRAM opb_sdram_0 0x20000000 0x2000FFFF




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Interfacing to the OPB PCI on the Memec Design Spartan-II 200 PCIBoard

Figure 7 shows the principle interface blocks when transferring data between the OPB PCIBridge in the XC2VP30 and the OPB PCI Bridge in the XC2S200

Figure 7: Interfacing ML310 Board OPB PCI with Memec Design Board OPB PCI

Configuration of OPB PCI on ML310 Board

The OPB PCI bridge uses the 32-bit Xilinx LogiCore Version 3 IP (v3) core. Before the bridgecan perform transactions on the PCI bus, the v3 core must be configured using configurationtransactions from either the PCI-side, or from the OPB side. This reference design configuresthe bridge from the OPB side, so C_INCLUDE_PCI_CONFIG is set to 1. In this case, the v3’sIDSEL input is connected to the address ports specified in Table 1, and the IDSEL port of thebridge is unused.

To write to the configuration header, do the following in the order shown:

1. Configure the Command and Status Register. The minimum that must be set is the BusMaster Enable bit in the command register. For memory transactions, the memory space bitmust be set. For I/O transactions, the I/O space bit must be set.

2. Configure the Latency Timer to a non-zero value.

3. Configure at least one BAR. Configure subsequent BARs as needed for other systems.

The v3 core can configure itself only after the Bus Master Enable bit is set and the latency timeris set to avoid time-outs. If the v3 core latency timer remains at the default 0 value, configurationwrites to remote PCI devices will not complete and configuration reads of remote PCI deviceswill terminate due to the latency timer expiration. Configuration reads of remote PCI deviceswith the latency timer set to 0 return 0xFFFFFFFF.

DDR

PPC OPB PCI OPB PCI MB

SDRAM

BRAM BRAM

ML310 - V2P ML310 - Slot 3

PCI




Configuration of OPB PCI on Memec Design Spartan-II 2S200 PCI Board

Optionally, the OPB PCI Bridge in the Xilinx XC2VP30 FPGA can interface to an OPB PCIBridge in the XC2S200 FPGA on the Memec Design Spartan-II 2S200 PCI Board. To configurethe XC2S200, use Impact to download the <opb_pci>.mcs file in the <proj>/memec_designdirectory. This is done using a Parallel 3 cable to the JTAG port. After configuring the 2S200using the mcs file, the OPB PCI in the 2S200 is configured using Configuration Writes from theOPB PCI in the XC2VP30.

Verifying the Reference Design with Xilinx Microprocessor Debugger

After downloading the design, the following procedure can be used to verify that the ML310reference design is set up correctly.

1. Configure the v3 Command Register, Latency Timer, and BAR(s).

2. Read the configuration header.

3. Configure the Command Register, Latency Timer, and BAR(s) of the other devices in thesystem.

4. Read the configuration headers of the other devices in the system.

5. Do a memory read of one of the IPIF BARs.

6. Do a memory write of one of the IPIF BARs.

This verification can be done using either Xilinx Microprocessor Debugger (XMD) and/or thesoftware projects discussed later in this document. Text files of the XMD commands areprovided in the XMD_command directory in the design files. The configure.xmd filecontains XMD commands which configure the bridge. The test_interrupt_regs.xmd filecontains command which set up and verify the interrupt registers. Thewrite_read_bram.xmd and write_read_ddr.xmd files contain XMD commands whichtest PLB BRAM and PLB DDR respectively. Table 4 lists the files containing XMD commandswhich are useful in verifying that the initial setup of a design is correct.

Table 4: XMD Configuration Commands

XMD command Function

configure_v2p_pci.xmd Configures the XC2VP30 CSR, Latency Timer, BARs

configure_s2_pci.xmd Configures the S2 CSR, Latency Timer, BAR

v2p_wr_plbbram.xmd Tests the PLB BRAM connected to the XC2VP30

v2p_wr_plbddr.xmd Tests PLB DDR connected to the XC2VP30

v2p_wr_s2opbbram.xmd Tests XC2VP30 writing to Spartan-II Board OPB BRAM

v2p_wr_s2sdram.xmd Tests XC2VP30 writing to Spartan-II Board SDRAM

s2_wr_opbbram.xmd Tests the OPB BRAM connsected to the S2

s2_wr_plbddr.xmd Tests the S2 writing to PLB DDR

dma_ml310_s3sdram.xmd Tests DMA from the ML310 to OPB SDRAM

dma_pcibridge2plbbram.xmd DMA from XC2VP PLB DDR to S2 SDRAM

dma_pcibridge2plbddr.xmd Tests DMA from S2 SDRAM to XC2VP DDR

dma_plbbram2pcibridge.xmd Tests DMA from PLB BRAM to PCI Bridge




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The following steps use the XMD commands in the files in the

<opb_pci_proj>/xmd_command

directory efficiently when Win2000 is used.

1. Invoke XMD.

2. Open the XMD command file (e.g. configure.xmd) using a text editor such as WordPad.

3. Select and copy the XMD commands in the text editor.

4. Right click the mouse in the XMD window to paste the commands.

The XMD commands in the configure.xmd file, listed in Figure 8, write to the ConfigurationAddress Port and Configuration Data Port to write the Configuration Space Header. TheCommand/Status Register, Latency Timer, and Base Address Registers are written and read.

dma_plbddr2pcibridge.xmd Tests DMA from PLB DDR to PCI Bridge

dma_s3sdram2ml310.xmd Tests DMA from S3 SDRAM to ML310

Table 4: XMD Configuration Commands

XMD command Function




Figure 8: XMD Commands for Configuring OPB PCI

Software Projects

The design files contain the following software projects to run with this reference system. Ineach software project directory, there are src and results sub-directories for the source codeand Hyperterminal results, respectively.

TestApp_Memory. This project tests the memory on the ML310 board.

TestApp_Peripheral.This project verifies that the OPB Sysace (if used) is used correctly.

hello_pci. This code enables master transactions, sets the latency timer, defines the busnumber/subordinate bus number, and scans the ML310 configuration registers.

Xilinx Microprocessor Debug (XMD) Engine

Xilinx EDK 7.1.2 Build EDK_H.12.5.1

Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

XMD% mrd 0x3C00010C 1

3C00010C: 00000000

XMD% mwr 0x3C00010C 0x04400080

XMD% mrd 0x3C00010C 1

3C00010C: 04400080

XMD% mrd 0x3C000110 1

3C000110: 46050022

XMD% mwr 0x3C000110 0x86002002

XMD% mrd 0x3C000110 1

3C000110: 46050002

XMD%

XMD% mwr 0x3C00010C 0x08400080

XMD% mrd 0x3C000110 1

3C000110: 1A452301

XMD% mwr 0x3C00010C 0x0C400080

XMD% mwr 0x3C000110 0x00FF0000

XMD% mrd 0x3C000110 1

3C000110: 00FF0000

XMD% mwr 0x3C00010C 0x10400080

XMD% mwr 0x3C000110 0x00000000

XMD% mrd 0x3C000110 1

3C000110: 08000000

XMD% mwr 0x3C00010C 0x14400080




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xpci_tapp_example. This project contains two major functions which use level 0 drivers:PciInitLevel_0() and ShowPCI(). PciInitLevel reads and writes the bus and subordinate busnumber, initializes the bridge device number if present, and performs configuration writes to thePCI header to setup the bridge. The latency timer is set to the maximum. The BAR registers areset, and interrupts are enabled.

xpci_example_level_0. This project uses level 0 drivers to initialize the PCI bridge. It theninitializes a remote device on the PCI bus, and prints messages describing the bridge andmemory mappings.

xpci_example_level_1. This project initializes the OPB PCI bridge and a remote device on thePCI bus. It then initializes Direct Memory Access (DMA) and runs local to DMA and DMA tolocal transfers. The PciIsr() function handles interrupts. The OPB PCI Bridge supports simplebut not scatter gatter DMA. Simple DMA is enabled by setting C_DMA_CHAN_TYPE = 0. TheDS416 Direct Memory Access and Scatter Gather product specification provides informationon the use of the DMA function in the IPIF. The base address for DMA in the ML310 ReferenceDesign is C_DMA_BASEADDR = 0x3D000000. The registers used in DMA setup are givenbelow.

The code which transfers DMA data is given in Figure 9.

Table 5: DMA Registers

DMA Register Address

Control Register C_DMA_BASEADDR + 0x04

Source Address Register C_DMA_BASEADDR + 0x08

Destination Address Register C_DMA_BASEADDR + 0x0C

Length Address Register C_DMA_BASEADDR + 0x10




Figure 9: C Code for DMA Operation

* PciDmaTransfer - interrupt driven DMA to/from a device on the PCI bus * * Parameters: * LocalAddress - address of a local memory device such as SRAM, DDR, etc. * RemoteAddress - address local to the processor that maps to the PCI bus * Bytes - bytes to transfer * Direction - direction to transfer, 0 = local to remote, 1 = remote to local *****************************************************************************/void PciDmaTransfer(Xuint32 LocalAddress, Xuint32 RemoteAddress, Xuint32 Bytes, int Direction){ Xuint32 DmaSrc; Xuint32 DmaDest;

/* setup transfer direction */ if (Direction == 0) { /* local to PCI */ XDmaChannel_SetControl(&Bridge.Dma, XDC_DMACR_SOURCE_INCR_MASK | XDC_DMACR_DEST_INCR_MASK | XDC_DMACR_DEST_LOCAL_MASK); DmaSrc = LocalAddress; DmaDest = RemoteAddress; } else if (Direction == 1) { /* PCI to local */ XDmaChannel_SetControl(&Bridge.Dma, XDC_DMACR_SOURCE_INCR_MASK | XDC_DMACR_DEST_INCR_MASK | XDC_DMACR_SOURCE_LOCAL_MASK); DmaSrc = RemoteAddress; DmaDest = LocalAddress; } else { printf("Invalid direction argument. Must be 0 or 1\n"); return; }

/* begin transfer */ XDmaChannel_Transfer(&Bridge.Dma, (Xuint32*)DmaSrc, (Xuint32*)DmaDest, Bytes);

/* wait for completion */ SemaphoreTake(&Bridge.DmaSemaphore); printf("Dma Transfer complete\n");}


Running the Applications


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Running theApplications

In EDK, select the Applications tab, Software Projects, Add SW Applications Projects.Name the software project (e.g. TestApp_Memory), and add the files from the software projectsrc directory to the Source Files area. Figure 10 illustrates how to make the hello_pci projectactive and the remaining software projects inactive.

Figure 10: Selecting the hello_pci Software Project

Select hello_pci and right click to build the project.



Running the ApplicationsR

Connect a serial cable to the RS232C port on the board. Start up a HyperTerminal. Set thebaud rate to 9600, number of data bits to 8, no parity, and no flow control, as shown inFigure 11. If a board other than the ML310 is used, a null modem may be required.

Figure 11: HyperTerminal Parameters


Using ChipScope with OPB PCI


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From XPS, start XMD and issue ppc and rst. Invoke GDB and select Run to start theapplication as shown in Figure 12. The Hyperterminal output should be similar to that in the<software_project>/results directory.

Figure 12: Running hello_pci in gdb

UsingChipScope withOPB PCI

To facilitate the use of ChipScope to analyze OPB PCI hardware, opb_pci.cdc,opb_pci.ctc, and opb_pci.cpj files are included in the chipscope directory. Theopb_pci.cdc is used to insert ChipScope ILA core into the opb_pci_1_wrapper core. Thefollowing steps are used to insert a core and analyze problems with ChipScope.

1. Invoke XPS. Run Tools → Generate Netlist.

2. In the opb_pci.cdc file, change the path <design_directory> name to the directory inwhich the design files are installed. Three paths need to be changed.

3. Backup implementation/opb_pci_0_wrapper.ngc.

4. Start → Programs → ChipScope Pro → ChipScope Inserter



Using ChipScope with OPB PCIR

5. From ChipScope Inserter, File → Open Project opb_pci.cdc. Figure 13 shows theChipScope Inserter setup GUI.

Figure 13: ChipScope Inserter Setup




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6. Click Next to move to the Modify Connections window. If there are any red data or triggersignals, correct them. The Filter Pattern can be used to find the correct net(s). As an exampleof using the Filter Pattern, enter *AD* in the dialog box to locate AD signals. Select the net andclick Make Connections. Figure 14 shows net connections.

Figure 14: Making net connections in ChipScope Inserter

7. Click Insert Core to insert the core. Copy the opb_pci_1_wrapper.ngo file toopb_pci_1_wrapper.ngc.

8. In XPS, run Tools → Generate Bitstream and Tools → Download. Do not rerun Tools →Generate Netlist as this overwrites the implementation/opb_pci_1_wrapper.ngc justproduced by Inserter. Verify that the filesize of the opb_pci_wrapper.ngc with the inserted coreis significantly larger than the original version. A mistake sometimes made is to use theopb_pci_1_wrapper.ngc located in the opb_pci_1_wrapper directory rather than the one in theimplementation directory.

9. Invoke ChipScope Core Analyzer. Click on the Chain icon located at the top left of AnalyzerGUI. Verify that the message in the transcript window indicates that an ICON is found.



Using ChipScope with OPB PCIR

10. The ChipScope Analyzer waveform viewer displays signals named DATA*. To reload thewaveform viewer with signal names specified in ChipScope Inserter, select File → Import andenter opb_pci.cdc in the dialog box.

10. In the Trigger Setup window, select File → Import opb_write.ctj. Change Windows toN samples to a setting of 500. Arm the trigger by selecting Trigger Setup → Arm, or clickingon the Arm icon.

11. Run XMD or GDB to activate the trigger patterns which cause ChipScope to displaymeaningful output. For example, invoke XMD, enter rst, and paste the contents ofconfigure.xmd into the XMD window.

12. ChipScope results can be analyzed in the waveform window, as shown in Figure 15. Toshare the results with remote collegues, save the results in the waveform window as a ValueChange Dump (vcd) file. The vcd files can translated and viewed in most simulators. Thevcd2wlf translator in Modeltech reads a vcd file and generates a wlf file for viewing in theModeltech waveform viewer. The vcd file can be opened in the Cadence Design System, IncSimvision© design tool with File → Open Database.

Figure 15: ChipScope Analyzer Results




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After running ChipScope, it is sometimes necessary to revise the nets used in triggeroperations and data in a debug operation. An efficient method to revise nets used byChipScope Analyzer uses the following command.

fpga_editor <system>.ncd

From the FPGA Editor GUI, select Tools → ILA.

Select an existing net which isn’t needed in debugging, and click Change Net. The pattern filterbox shown in Figure 16 facilitates the selection of the new net. Click Write CDC to generate annew opb_pci.cdc file. Click Bitgen to generate a new .bit file.

The FPGA Editor ILA flow is more efficient than re-doing the Chip Inserter flow listed abovebecause the MAP and PAR implementation phases are not required.

Figure 16: Using FPGA Editor to Revise Nets used in ChipScope Analyzer



Linux KernelR

Linux Kernel The steps to build and boot a linux kernel are given below. Steps 1-3, 7, 8 are run on a Linuxmachine with MontaVista Professional Edition© installed.

1. Add /opt/montavista/pro/host/bin and/opt/montavista/pro/devkit/ppc/405/bin to $PATH.

2. Create and change to the <opb_pci_proj>/linux_pci directory.

3. Run

tar cf - -C /opt/montavista/pro/devkit/lsp/xilinx-ml300-ppc_405/linux-2.4.20_mv31/ . tar xf -

4. To generate the Linux LSP in XPS, enter Project Software → Platform Settings andselect Kernel and Operating Systems and select linux_mvl31 1.00.a for ppc405_0.

5. Under Library/OS Parameters, set the entries as shown in Figure 17.

Figure 17: BSP Settings

Verify that the target directory is the same as the directory containing the Linux source.


Linux Kernel


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6. Click Connect_Periphs and add OPB_INTC, OPB_SYSACE, OPB_PCI, OPB_GPIO,OPB_IIC, and OPB 16550 entries as shown in Figure 18.

Figure 18: Connected Peripherals

Click OK.

7. Select Tools → Generate Libraries and BSPs to generate LSP in<opb_pci_proj>/linux_pci.

8. The <opb_pci_proj>/linux_pci/.config is used to generate the Linux kernel. Analternative is to enter make menuconfig and generate a new .config.

9. Run make clean dep bzImage. Verify that the zImage.elf file is in<opb_pci_proj>/linux_pci/arch/ppc/boot/images directory.

10. Invoke Impact and download implementation/download.bit to xc2vp30. Onemethod of doing this uses the command below.

impact -batch etc/download.cmd

11. Invoke XMD. From the <opb_pci_proj>/linux_pci directory, enter the followingcommands in the XMD window.

rstdow arch/ppc/boot/imagest/zImage.elfcon

12. View the output in the HyperTerminal window. Login as root with 310ml as password. Entercd / and ls -l to view the contents of the mounted Linux partition of the Compact Flash(CF).

13. Enter lspci to view the PCI devices. For each line of output, the first 2 digits represent thePCI bus number, followed by the device number and function number.

14. An alternative to downloading the Linux kernel executable is to load it into CompactFlash.The file used uses an ace file extension. To generate an ace file, run the command belowfrom the <opb_pci_proj> directory.

xmd -tcl ../genace.tcl -jprog -hw ../implementation/system.bit -ace../implemetation/ace_system_hw.ace -board ml310

Copy the ace file to the 64-512 MB CompactFlash card in a CompactFlash reader/writer.Remove the CF from the CF reader/writer and insert it into the CompactFlash slot (J22) on theML310 board. Power up the board.



ReferencesR

References DS437 OPB IPIF/LogiCore V3 PCI Core Bridge (v1.02a)

Xilinx LogiCore PCI Interface v3.0 Product Specification

Xilinx The Real PCI Design Guide v3.0

DS416 Direct Memory Access and Scatter Gather

Spartan-II 200 PCI Development Board User’s Guide

XAPP765 Getting Started with EDK and MontaVista Linux

UG068 ML310 User Guide

ChipScope ILA Tools Tutorial

RevisionHistory

Table 6 shows the revision history for this document.

Table 6: XAPP911 Revision History

Date Version Revision

12/23/05 1.0 Initial Xilinx release.

1/06/06 1.0.1 Changed Initial release date. Moved trademark. Removed links.

1/27/06 1.0.2 Changed link to design files.

www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_pci.pdf

http://ww.xilinx.com/products/logicore/pci/docs/design_guide_30.pdf

http://www.xilinx.com/partinfo/pci/xcvpci64_32ds.pdf

http://www.xilinx.com/products/logicore/pci/docs/design_guid_30.pdf


http://www.xilinx.com/products/software/chipscope/chipscope_ila_tut.pdf

Documents

Reference System: OPB PCI · The ALi M1535D+ South Bridge interfaces to the legacy devices, including the audio, modem, USB, and IDE ports. PCI-to-PCI Bridge TI2250 Intel 10/100 Ethernet