Reference Interface Design between ISD5008 ChipCorder

ISD5008 GSM Cell Phone Reference Design Page 1

Reference Interface Design between ISD5008 ChipCorderTM and

AD20MSP425 GSM processor chip-set

By Prasanna Shah

& Robert L. Taber

Pragmatic Communications Systems, Inc. &

Joe Jarrett ISD/Winbond


Reference Interface Design between ISD5008 ChipCorder and AD20MSP425 GSM processor chip-set.

Introduction________________________________________________________________ 2

ISD5008 Application _________________________________________________________ 2

Hardware description ________________________________________________________ 4

Normal / Conversation Mode__________________________________________________ 4

One-way call record _________________________________________________________ 7

Two-way call record _________________________________________________________ 8

Voice memo record __________________________________________________________ 8

Out-going message record (Answering Machine) _________________________________ 9

Out-going message review/message playback_____________________________________ 9

Out-going message play to the phone __________________________________________ 10

Incoming Message Record ___________________________________________________ 11

Conclusion ________________________________________________________________ 11

References ________________________________________________________________ 11

Description of Software Flowcharts _______________________________________ 12

Overview _________________________________________________________________ 12

Software Architecture_______________________________________________________ 12

Flowchart 1, Menu 70: Activate one-way call record _____________________________ 16

Flowchart 2, Menu 71: Activate two-way call record _____________________________ 18

Flowchart 3, Menu 72: Activate voice memo record _____________________________ 19

Flowchart 4, Menu 73: Begin outgoing message record ___________________________ 20

Flowchart 5, Menu 74: Outgoing message playback______________________________ 20

Flowchart 6, Menu 75: Activate answering machine mode ________________________ 21

Flowchart 7: Play Outgoing Message to the incoming Phone call and Record incoming Message __________________________________________________________________ 21

Flowchart 8, Menu 76: Cancel answering machine mode_________________________ 23

Flowchart 9: Menu 77: Message playback _____________________________________ 23

Flowchart 10, Menu 78: Erase message _______________________________________ 24

Appendix _____________________________________________________________ 25


Reference Interface Design between ISD5008 ChipCorder and AD20MSP425 GSM processor chip-set.

Introduction The benefits and advantages of using a ChipCorder to add features to a GSM Cellular Phone have been discussed in earlier publications. (See Reference [1] on page 11.) This document presents an implementation of the ChipCorder in a typical GSM phone, based on the AD20MSP425 GSM chipset. Although this document is based on the AD20MSP425 GSM chip set, similar implementations are also possible for other GSM chipsets, including cellular systems such as the TMDA IS-136 and CDMA. The hardware implementation and interface between the GSM chipset and ISD5008 are shown in this document with software design and flowcharts for implementing various features. Figure 1 displays a block diagram of a typical GSM phone implementation using the AD20MSP425 GSM chip set. The RF section includes antenna diversity, down conversion, up-conversion and frequency synthesis, RF power amplifier, power ramp control, etc. The baseband section includes the DSP, Voice Band Codec (VBC), memory, and user interface such as keypads, LCD, buzzer, etc.

Figure 1: Block Diagram of a Typical GSM Phone

Microcontroller

RFSection

Baseband Section

DSPVB

CodecBB

Codec

MIC IN+MIC IN -

SP OUT -SP OUT+

Earpiece

Microphone

1234567890

AD20MSP425 GSM Chip Set

Display

Keyboard

ISD5008 Application The ISD5008 Record/Playback IC includes an interface designed to easily connect to most Baseband Chipsets. The ANA IN input is designed to connect directly (through a coupling capacitor) to one side of the speaker or piezo driver output of the Chipset. The ISD5008 then supplies a differential speaker power driver that may be used to drive the original earpiece element of the cell phone. Likewise, the ANA-OUT plus and minus differential output of the ISD5008 is designed to drive the microphone input of the Chipset. The original cell phone microphone then connects to the microphone input of the ISD5008. These two signals are passed through the ISD5008, giving it control of the audio paths in the phone. This allows the cell phone designer to implement the rich feature-set available with the ISD5008. Figure 2 displays a block diagram of the ISD5008 and Figure 3 displays a block diagram of the cell phone with the ISD5008 attached.


Figure 2: Block Diagram of ISD5008

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC

1.0 / 1.414 / 2.0 / 2.828

ΣΣΣΣΣΣΣΣ

Multilevel StorageArray

Internal Clock

FILTO

ANA IN

ARY

Low passFilter

VolumeControl

VOLMUX

Device Control

SCLK SS MOSI MISO INT RAC

Power Conditioning

ANA OUT–

FTHRU

INP

VOL

SUM1

SUM2

SP+

SP–

VOL

ANA IN

AUX OUT

6dB

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

AXG0AXG1( )2

1(AXPD)

1(AIPD)

ANA INAMP

AUX INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

FILT0

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARYANA IN

OUTPUTMUX

2OPA0OPA1( )

FILT0

SUM 1

2 OPS0OPS1( )

2

SUM 1

ANA IN

INP

1 (VLPD)( )VLS0VLS1

SUM 2

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC

1.0 / 1.414 / 2.0 / 2.828

ΣΣΣΣΣΣΣΣ


Internal Clock

Internal Clock

FILTO

ANA IN

ARY

Low passFilter

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT–

FTHRU

INP

VOL

SUM1

SUM2

SP+

SP–

VOL

ANA IN

AUX OUT

6dB

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )AIG0AIG1( )22

33

AXG0AXG1( )AXG0AXG1( )22

1(AXPD)1(AXPD)

1(AIPD)1(AIPD)

ANA INAMP

AUX INAMP

INPUT SOURCE

MUX

1(AGPD)1(AGPD)

1(INS0)1(INS0)

FILT0

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)1(FLS0)

22S1S0S1S1( )

S1M0S1M1( )22

SUM2 SUMMINGAMP

1(FLPD)1(FLPD)

22

22S2M0S2M1( )

FLD0FLD1( )FLD0FLD1( )

FILTERMUX

ARYANA IN

OUTPUTMUX

22OPA0OPA1( )

FILT0

SUM 1

22 OPS0OPS1( )

22

SUM 1

ANA IN

INP

1 (VLPD)1 (VLPD)( )VLS0VLS1

SUM 2

Figure 3: Block Diagram Cell Phone using ISD5008

Earpiece Earpiece

ANA OUT+ANA OUT-

ANA IN

ISD5008

SP+ SP-

MIC+MIC-

Microcontroller

RFSection

Baseband Section

DSP VBCodec

BBCodec

MIC IN+MIC IN

SP OUTSP OUT+

1234567890

AD20MSP425 GSM Chip Set

Display

Keyboard

AUX IN AUX OUT


Hardware description The complete interface schematic between AD6425 (VBC), AD6426 (EGSMP) and the ISD5008 is displayed in Figure 4. The microphone is biased from the VBC through VrefOUT pin 48 and resistors R1 and R2. The signal generated across the microphone is differentially fed to the ISD5008 through coupling capacitors C3 and C4. This signal is routed through the ISD5008 and input into VBC VIN pins 44 and 45. Capacitors C5 and C6 provide DC isolation between the two chips. On the receive side, the audio signal output from the VBC at pin 38 is fed into the ISD5008 pin 18 via C8. This signal is then driven into the speaker by pins 14 and 16 of ISD5008. Both the analog and digital supply voltages on ISD5008 have adequate filtering through C11, C12, C13 and C14. The interface between the SPI port on ISD5008 and EGSMP AD6426 is through the general-purpose I/O port pins: GPIO0, GPIO3, GPIO4, GPIO5, GPO10 and GPCS. The only extra components required to implement these voice storage features are the ISD5008 and approximately seven capacitors. A car kit interface can be made either into the ISD5008 AUX IN / AUX OUT pins or the VBC AUX IN / OUT port.

Figure 4. Schematic diagram of interface between AD20MSP425 & the ISD5008

SCLK/SS

MOSIMISOVSSDVSSDNCMIC+VSSAMIC-ANA OUT+ANA OUT-A CAPSP-

XCLK

U1

ISD5008

VrefCA

P49

U2

AD6425

M1 MICROPHONE

S1

SPEAKER

C40.22uF

C60.22uF

C30.22uF

C80.22uF

C50.22uF

C10.22uF

R1

1K

R2

1K

R3

1K

+ C74.7uF

+ C14

22uF

+ C1222uF

C130.1uF

C110.1uF

VCCD

VCCA

B1

BUZZERQ12N3904

R41K

D11N914

VCCD

AU

XAD

C1

AU

XAD

C2

AU

XAD

C3

AU

XAD

C4

IDA

CO

UT

IDA

CR

EFA

GN

D4

AVD

D4

AFC

AG

CR

AM

PITXPITXNQ

TXNQ

TXP

505152535455565758596061626364

C20.22uF

VSSASP+

VCCAANA INAUX IN

AUX OUTNCNC

VSSARAC/INT

VCCDVCCD

VCCDAGND1BREFCAPBREFOUTIRXPIRXNQRXPQRXNAGND2DGND2DVDD2ASDIASDIFSASDOFSASDOASCLK

123456789

10111213141516 VSFS

VSDIDVDD4DGND4

BUZZERVOUTNORPVOUTNORN

AGND3AVDD3

VOUTAUXNVOUTAUXP

VINNORPVINNORNVINAUXPVINAUXN

VrefOUT

33343536373839404142434445464748

BSC

LKB

SDO

BSD

OFS

BSD

IFSB

SDI

MC

LKD

VDD

3R

XON

TXON

RESET

TDI

TDO

TMS

TCK

VSCLK

VSDO

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32123456789

1011121314 15

16171819202122232425262728

GPIO0

GPO10

GPIO4

GPCSGPIO3

Interface

GPIO5

Normal / Conversation Mode The GSM phone can be in an idle/stand-by mode or it can be in an active/conversation mode. The active/conversation mode is referred to as the normal operational mode here. In the normal operational mode, the signal flow through the ISD5000 is as shown in Figure 5. The microphone is biased from the VBC VrefOut. The differential signals pass through the AGC amplifier that has a 34 dB gain range. From the AGC amplifier, it is differentially fed through ANA OUT into the VBC. The VBC normal inputs have Programmable Gain Amplifiers (PGA) with a gain range of 39 dB in 3 dB steps. With the AGC in the ISD5008 and the PGA in the VBC, setting up the reference level for the microphone in the GSM phone becomes very simple.


The reconstructed audio signal from the VBC is available at the normal VBC output. The PGA of the VBC provides a gain range of + 6 dB to – 15 dB in 3 dB steps. This signal is fed into the analog input ANA IN of the ISD5008. The ANA IN AMP has fixed gain settings of 6, 9, 12 or 15 dB and the volume control provides a 0 to +28 dB attenuation range with 4 dB steps.

Figure 5. Signal flow through the ISD5008 during normal/conversation mode

VCCA VSSA VSSA VSSA VSSD1 VSSD2 VCCD1 VCCD2

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

FTHRU

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1

Configuration Registers1

CFG0=4442hCFG1=11E2h


MIC–

XCLK

ANA IN

AUX IN

MIC+AGC

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

FTHRU

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1



This extensive gain control range, due to the combination of the VBC PGA and ISD5008 ANA IN AMP and volume control, provides enough dynamic range and linearity to prevent distortion and clipping in the receive mode. The setting of the output reference level also becomes very easy with this combination.1 An alternative signal path for the microphone signal is via the pass through mode. This is displayed in Figure 6. In this mode, a 6dB gain is available through the ISD5008 and the balance of the gain or attenuation is available through the PGA in the VBC.

1 See Appendix for details on the setup of the configuration registers for each ISD5008 Block Diagram


Figure 6. Alternative Signal Path through the Chip (Pass Through Mode)


MIC–

XCLK

ANA IN

AUX IN

MIC+

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

FTHRU

SP+

SP–

VOL

AUX OUT

6dB

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1




MIC–

XCLK

ANA IN

AUX IN

MIC+

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

FTHRU

SP+

SP–

VOL

AUX OUT

6dB

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1



Setting of the gain both in the microphone and earpiece/speaker path is important. The standard procedure is to use an acoustical setup similar to the B&K test equipment. The calibrated transducer will produce a unity reference level acoustical signal that is coupled to the microphone. The gain in the microphone path will be set to produce a unity reference level in the GSM Mobile Test set. The combination of AGC in the ISD5008 and the gain range of the PGA in the VBC should be sufficient to produce a signal that meets the distortion specifications for the GSM. If the alternate pass through mode is utilized, the gain settings are only done in the PGA of the VBC. In the speaker path, reference tones will be created from the GSM test set. The pick-up transducer of the B&K acoustical equipment will be coupled with the speaker output and gain settings in the ISD5008, and the PGA of the VBC will set to product the unit reference level. This process is only necessary in the design phase of the GSM handset when the microphone and earpiece transducers are selected. The spread on the sensitivity of the transducers is fairly narrow and so once the gain settings are selected, they can be used in the production of the GSM handsets without any further calibration.


One-way call record In an active/conversation mode, it may be necessary to record the received audio signal. An example would be to record an address or directions, a phone number or a short note during a conversation. The ability to record the incoming audio signal during the conversation is referred to here as a “One-way call record”. In this mode, the signal flow through the ISD5008 is as shown in Figure 7. The microphone and speaker signals are connected similar to the connections previously show in the normal conversation mode, in Figures 5 or 6.

Figure 7. Signal flow through the ISD5008 during one-way call record

VCCA VSSA VSSA VSSA VSSD1 VSSD2 VCCD1 VCCD2 SCLK SS MOSI MISO INT RAC

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ

Multilevel Storage

Array

Internal ClockANA IN

Low passFilter

VolumeControl

VOLMUX

Device ControlPower Conditioning

ANA OUT+

ANA OUT–

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1


CFG0=4442hCFG1=10C8h


MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ

Multilevel Storage

Array


Low passFilter

VolumeControl

VOLMUX


ANA OUT+

ANA OUT–

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1


CFG0=4442hCFG1=10C8h

In addition, the received signal is also routed to the multi-level storage array through the following path: ANA IN AMP > SUM1 MUX > SUM1 SUMING AMP > FILTER MUX > LOW PASS (Anti-aliasing) FILTER > SUM2 SUMMING AMP > STORAGE ARRAY. The proper setup for the ISD5008 Configuration registers is shown in Figure 7. The record function is initiated as described in a later Software section of this document. In this example we are assuming that record is performed with a 5.3 KHz sample rate clock. The ISD5008 record function is controlled through the SPI interface by the EGSM processor’s general purpose I/O port.


Two-way call record Similar to the “One-way call record” function, it may be necessary to record both the incoming as well as the outgoing audio signal during a conversation mode. Figure 8 displays the signal flow through the ISD5008 for both the transmitted/received signal as well as the audio stored. The microphone signal is routed to the VBC as usual, but is also routed to the SUM1 summing amplifier. The received signal from the VBC is routed to the speaker through the volume control and also to the input of the SUM1 amplifier. At the SUM1 amplifier, both the signals are combined and stored in the multi-level storage array. The two-way call record function is initiated as described in a later Software section of this document. The general-purpose I/O ports of the EGSM processor control the ISD5008 through the SPI interface. This is a very unique feature that is easily available when using the ISD5008 ChipCorder. Attempting to implement a similar feature in the digital storage mode would be difficult and inefficient. In this example we will change to a different sample rate clock of 4 KHz.

Figure 8. Signal flow through the ISD5008 during two-way call record


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ



Low passFilter

VolumeControl

VOLMUX


ANA OUT–

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2 S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1


CFG0=4442hCFG1=104Ch


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ



Low passFilter

VolumeControl

VOLMUX


ANA OUT–

INP

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2 S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1


CFG0=4442hCFG1=104Ch

Voice memo record This feature allows the GSM phone to act as a voice memo recorder for taking personal notes. During the stand-by or idle mode of the GSM phone, the voice signals from the microphone are routed to the multi-level storage array. The signal flow through the ISD5008 for voice memo record function is displayed in Figure 9. The microphone signal is routed through the AGC, INPUT SOURCE MUX, SUM1, FILTER MUX, Low pass filter, SUM2 and into the multi-level storage array. All other blocks that are not selected can be in power down mode. The voice memo record function is initiated as described in a later Software section of this document. During this function, the VBC can be completely in the power down mode for power savings on the GSM phone. An alternate digital method for voice memo record on the GSM phone would require more power and would be more complex to implement. For this example, we are recording with a sample rate clock of 8.0 KHz.


Figure 9. Signal flow through the ISD5008 during voice memo record


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter


ANA OUT–

SP+

SP–

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY


CFG0=2421hCFG1=0140h


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+AGC ΣΣΣΣ

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter


ANA OUT–

SP+

SP–

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

INPUT SOURCE

MUX

1(AGPD)

1(INS0)

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY


CFG0=2421hCFG1=0140h

Out-going message record (Answering Machine) The out-going message (OGM) record is identical to the voice memo record and so the signal flow shown in Figure 9 is applicable here as well. The software issues for this function are detailed in a later Software section of this document.

Out-going message review/message playback Once the out-going message has been recorded, it can be reviewed via the message playback configuration. The signal flow through the ISD5008 is displayed in Figure 10. The stored message is read from the multi-level storage array and, via the low pass filter, is routed to the volume control block via SUM2 amplifier. Once again, in this process no involvement from the VBC is required, thus yielding the lowest power consumption. The software issues for this function are detailed in a later Software section of this document. We are assuming a sample rate clock of 6.4 KHz in this example.


Figure 10. Signal flow through the ISD5008 during message playback


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter

VolumeControl

VOLMUX


ANA OUT–

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

VOL0VOL1VOL2( )3

1(FLS0)

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2 1 (VLPD)( )VLS0VLS1

SUM 2

Configuration RegistersCFG0=2422hCFG1=51D5h


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter

VolumeControl

VOLMUX


ANA OUT–

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

VOL0VOL1VOL2( )3

1(FLS0)

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )2 OPS0

OPS1( )

2 1 (VLPD)( )VLS0VLS1

SUM 2


Out-going message play to the phone When the answering machine mode is activated, the previously recorded out-going message is played back from the multi-level storage array through the low pass filter and SUM2 amplifier. It is then fed through the volume control into the VBC where it is processed and transmitted through the system. The signal flow through the ISD5008 is displayed in Figure 11. At the end of the out-going message, an alert tone can be created through the VBC and the Incoming message record mode can be initiated. This is described in detail in the Incoming Message Record section. The software issues related to implementing this function are described in a later Software section of this document. We are assuming a sample rate clock of 6.4 KHz in this example.

Figure 11. Signal flow through the ISD5008 during OGM play to phone


MIC–

XCLK

ANA IN

AUX IN

MIC+

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

VOL

SP+

SP–

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )3

1(FLS0)S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARYANA IN

2

INP

1 (VLPD)( )VLS0VLS1



MIC–

XCLK

ANA IN

AUX IN

MIC+

ΣΣΣΣ

Multilevel Storage

Array

Internal Clock

Low passFilter

VolumeControl

VOLMUX

Device Control


Power Conditioning

ANA OUT+

ANA OUT–

VOL

SP+

SP–

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

ANAOUTMUX

3

1

AOS0AOS1AOS2( )

(AOPD)

VOL0VOL1VOL2( )3

1(FLS0)S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARYANA IN

2

INP

1 (VLPD)( )VLS0VLS1



Incoming Message Record After the OGM is played in Answering Machine Mode, it is necessary to put the phone in a configuration where the incoming message can be recorded. This configuration is similar to the configuration used in One Way Call Record described earlier, except that the Microphone to Chip Set path is disabled. This allows the Incoming Message (ICM) to be recorded into the storage array while the user is able to monitor the call. The designer would probably configure the telephone’s software so that the user could immediately connect to the call and interrupt the recording of the ICM by pressing the Connect button on the telephone. Figure 12 displays the Signal flow set up for recording of the ICM.

Figure 12. Signal flow through the ISD5008 during ICM Record from Phone Line


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+ΣΣΣΣ

ΣΣΣΣ



Low passFilter

VolumeControl

VOLMUX


ANA OUT–

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )

2 OPS0OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1

Configuration RegistersCFG0=4422hCFG1=10C5h


ANA OUT+

MIC–

XCLK

ANA IN

AUX IN

MIC+ΣΣΣΣ

ΣΣΣΣ



Low passFilter

VolumeControl

VOLMUX


ANA OUT–

SP+

SP–

VOL

AUX OUT

AGCCAP

Microphone

CarKit

ChipSet

ChipSet

CarKit

Speaker

.625 / .883 / 1.25 / 1.767

VOL0VOL1VOL2( )

AIG0AIG1( )2

3

1(AIPD)

ANA INAMP

1(INS0)

SUM1MUX

SUM1 SUMMINGAMP

1(FLS0)

2S1S0S1S1( )

S1M0S1M1( )2

SUM2 SUMMINGAMP

1(FLPD)

2

2S2M0S2M1( )

FLD0FLD1( )

FILTERMUX

ARY

OUTPUTMUX

2OPA0OPA1( )

2 OPS0OPS1( )

2

ANA IN

1 (VLPD)( )VLS0VLS1

Configuration RegistersCFG0=4422hCFG1=10C5h

Conclusion It can be concluded that adding voice storage and answering machine features to a standard GSM can be done very effectively by using the ISD5008 ChipCorder. Although the example here is a GSM chip-set from Analog Devices, other GSM chip-sets can also be used to implement these same features. Since the advantages of the ISD5008 and its built-in functional blocks are shown in a GSM implementation, parallel conclusions can be drawn and similar implementations can be made for IS-136 TDMA and IS-95 CDMA cellular standards as well. References 1) “Software Considerations for Adding a Speech Recording System to a Digital

Cellular Telephone” by Joe Jarrett, Information Storage Devices and Prasanna Shah, Pragmatic Communications Systems, Inc. 1997

2) Datasheet for ISD5008 ChipCorder. 1999


Description of Software Flowcharts Overview This section describes the software architecture, the software operation and flowcharts, and the low-level control software for the ISD5008 ChipCorder. The following voice storage features and functions, using the ISD5008 ChipCorder, will be described:

• One-way and two-way (full duplex) call record (during phone call) • Voice memo record and playback • Outgoing message record (phone in standby) • Outgoing message play and incoming call record (answering machine)

Software Architecture The control software is divided up into three cooperative layers for integration into the GSM cellular phone control software. The layers are:

(1) User Interface (2) Protocol layer (3) Operational layer

Each of these layers is reviewed below. 1. User Interface The user interface layer is responsible for all aspects of activation and selection for the various features and functions of the ChipCorder circuitry. The user interface layer provides the routines, menu readouts and selections, and control settings/selections for programming the ChipCorder. The specific details of the user interface functions and routines are left to the designer’s discretion. The examples in this document provide possible ways that user interface functions and menu selections can be implemented for the ChipCorder. For example, the flowcharts later in this document display how pressing the “Menu” key, followed by a numeric code (which is typical of most user interface implementations for cellular phones) programs specific functions. However, there are many other selection methods that can be used for programming specific functions. What is important is that the user is given an easy method for selecting functions and options.


The following is a list of functions that can be easily implemented for the ChipCorder: Menu 70: Activate one-way call record. Menu 71: Activate two-way call record. Menu 72: Activate voice memo record. Menu 73: Begin Outgoing Message (OGM) record. Menu 74: Outgoing Message playback. Menu 75: Activate answering machine mode. Menu 76: Cancel answering machine mode. Menu 77: Message playback. Menu 78: Erase message. Each of these functions is described in more detail beginning on the next page. 2. Protocol Layer The protocol layer includes all functions that are integrated into the GSM protocol routines of the cellular phone control software. The protocol layer is generally responsible for activating the operation of the ChipCorder when specific events occur. This ensures that the operation of the ChipCorder flows smoothly, and the desired features and functions of the ChipCorder are integrated closely and seamlessly with the GSM protocol. Because the ChipCorder functions are activated when specific events occur, “hooks” are required in the protocol routines that control and cause the low-level operational routines to initialize. For example, the "Answering Machine Mode" must be activated when the phone receives an incoming call. Therefore, the protocol routines must be able to activate the "Answering Machine Mode" from within the routines that handle an incoming call. 3. Operational Layer The operational layer contains all of the low-level control routines and drivers for the ISD5008 ChipCorder circuitry. The most essential routines in this layer control the basic ChipCorder functions: Begin Record, Stop Recording, Begin Playback, and Stop Playback. These low-level control routines are called from the appropriate places in the higher-level routines so that the ChipCorder is controlled and activated at the appropriate times. Other control routines reviewed in this section will handle all of the message management functions. These functions manage the recording and playback of individual messages as directed by the other routines. These routines also manage storage tables or other mechanisms that keep track of the individual messages in the storage array so that a specific message can, for example, be played back.


Normal Mode and Description of Software Flowcharts Note: in each explanation below, it is assumed that all sections of the chip having power controls are powered down when ever possible. This ensures that the chip is always in its lowest power state. We are assuming that all sections of the chip are powered down before we change to the Normal Mode described below. Additional details for the setup of each Mode and Flow Chart entry can be found in the Appendix. As shown in Figure 5 on page 5, the normal (or conversational mode) is used to pass the audio, from the microphone, to the GSM chipset, and to accept the audio from the GSM chipset in order to drive the speaker. The following steps accomplish this:

1. Power up the AGC Amplifier 2. Select the MIC path through the INPUT SOURCE MUX. 3. Select the INPUT SOURCE MUX input of the ANAOUT MUX. 4. Power up the ANA OUT output stage 5. Power up the ANA IN AMP 6. Select the ANA IN input through the VOL MUX. 7. Power up the VOLUME CONTROL LEVEL. 8. Select a VOLUME CONTROL LEVEL. 9. Select the VOLUME CONTROL path through the OUTPUT MUX. 10. Power up the SPEAKER amplifier and select the HIGH GAIN mode.

The 10 steps above are accomplished by loading the two configuration registers in the ISD5008. Configuration Register 0 is loaded first with the hex value 4442h1. Loading data to Configuration Register 0 loads a temporary internal register with this data but does not yet affect the set up of the chip. Next, load Configuration Register 1 with 11E2h. When Configuration Register 1 is loaded, the latest data from both registers is transferred into the chip’s internal setup. All changes to the audio paths, amplifier gains, power down states, etc. all occur synchronized with the loading of Configuration Register 1.

11. If the ISD5008 master PU (Power Up) bit was previously LOW it should now be set HIGH. The PU bit is not located in the Configuration Registers. It is part of every command given to the ISD5008. It must be set HIGH to enable all of the internal functions of the chip.

1 Some of the Configuration Register bits are “don’t care” for this configuration of the chip, i.e. they can be a “0” or a “1”. Therefore, there are other possible configuration register settings that can result in the same chip set up. See the Appendix for further discussion.


As shown in Figure 6 on page 6, there is an alternate path for routing the microphone audio to the ANA OUT output called Pass-Through Mode. It is up to the system designer to determine which mode is best for their application. To use Pass-Through mode instead of Normal Mode, use the following steps: 1. Select the FTHRU input to the ANAOUT MUX. 2. Power up the ANA OUT AMP 3. Power up the ANA IN AMP 4. Select the ANA IN input through the VOL MUX. 5. Power up the VOLUME CONTROL LEVEL. 6. Select a VOLUME CONTROL LEVEL. 7. Select the VOLUME CONTROL path through the OUTPUT MUX. 8. Power up the SPEAKER amplifier and select the HIGH GAIN mode. The above requires a Configuration Register load of: CFG0=4402h and CFG1=11E3h. 9. If the ISD5008 master PU bit was previously LOW (i.e., the entire chip was in Power Down),

it should now be set HIGH to power up the chip. The storage array of the ChipCorder is not used when Normal or Pass-through Modes are used by themselves. When the call is terminated, the ChipCorder should be placed in power-down mode to conserve battery power.


Flowchart 1, Menu 70: Activate one-way call record (see Figure 7 on page 7) The purpose of this function is to record the audio of the received call while the phone is in operation. Menu 70 of the user interface routines activates this function. The first step is to initialize the ChipCorder and establish the storage address and all of the control parameters required to configure it for this function. The message management routines are called to establish the address for storing the next recorded message into the Multilevel Storage Array of the ChipCorder. Then, the ChipCorder is configured to route the audio from the "ANA IN" input to the storage array so that the storage array can record the received audio. The following steps accomplish this function. Note: it is assumed the chip is already in Normal Mode. 1. Select the ANA IN path through the SUM1 MUX. 2. Select the SUM1 MUX input (only) to the SUM1

SUMMING amplifier (this also powers up the SUM1 SUMING AMP).

3. Select the SUM1 SUMMING amplifier path through the FILTER MUX.

4. Power up the LOWPASS FILTER. 5. Select the desired sample rate. 6. Select the LOW PASS FILTER input (only) to the SUM2

SUMMING amplifier (this also powers up the SUM2 SUMMING AMP).

The output of the SUM2 Summing Amp drives the input to the ISD5008 analog storage array. It should be noted that the ANA IN audio path goes two directions: (1) to the Analog Storage Array (as described above) and (2) to the Speaker driver section of the chip. The above requires a Configuration Register load of: CFG0=4442h and CFG1=10C8h. This assumes a recording sample rate of 5.3 KHz. After the ChipCorder has been configured to record the audio from the proper source, ANA IN, the recording may begin. The low-level routine "BEGIN_RECORD" is called to activate the recording function. We are now ready to exit this procedure and resume normal call-processing functions. We exit this procedure with the ChipCorder actively recording the incoming call. This illustrates one of the major benefits of using the ChipCorder in this application. After the control command has been sent to the ChipCorder to begin the recording function, the actual recording process proceeds under hardware control of the ChipCorder, without any further intervention by the main processor. The main processor is not burdened by having to control the recording process and is free to take care of normal call processing functions. This approach greatly simplifies both the

Menu 70: Activate one-way call record

Initialize ChipCorder:1. Establish address for message storage2. Setup to record from "ANA IN" input

Begin record function

Return

"Stop" key

Stop recording:Update message storage tables

Return

Periodic Timer interrupt:

Monitor ChipCorder functions:If full, then stop recording

Return

Flowchart 1


hardware design and the software design for efficiently implementing the voice recording features described here. There are two ways to terminate the call record procedure. The first is for the user to manually terminate the recording by pressing a "Stop" key. When this occurs, the low-level routine "STOP_RECORD" is called to stop the ChipCorder. Then, the message management routines are called to update the storage tables with the length of the just-completed message. This will also enable the system to establish the storage address for the next message. The second way the call record procedure is terminated is via an automatic termination from the system when the storage array becomes full. The ChipCorder has the ability to generate an interrupt if an alarm such as "overflow" occurs. In this case, the interrupt service routine would call the message management routines to update the storage tables for a "device full" condition. If the hardware interrupt capability is not implemented, then it is necessary to periodically poll the ChipCorder to determine its status and see if there are any conditions that need to be handled. This situation is shown in the lower part of Flowchart 1. In this case, a polling routine would be activated as part of a periodic timer interrupt, or equivalent function within the GSM protocol routines, to monitor the status of the ChipCorder and take care of any conditions that need servicing. Menu 77 is used to playback this recording.


Flowchart 2, Menu 71: Activate two-way call record (see Figure 8 on page 8) The purpose of this function is to record both the incoming audio of the received call and the outgoing audio from the local microphone, in full-duplex mode, while the phone is in operation. This allows both sides of the conversation to be simultaneously recorded. The elements of this procedure are almost identical to Flowchart 1, with the only difference being that the audio is taken from both inputs and mixed prior to storage in the storage array. This mixer function is a built-in feature of the ChipCorder, which makes the full-duplex recording process very easy to implement. The first step is to initialize the ChipCorder and establish the storage address, and determine all of the control parameters required to configure it for this function. The message management routines are called to establish the address for the next recorded message. Then, the ChipCorder is configured to route the audio from the "ANA IN" and "MIC" inputs to the storage array so that the storage array can record the audio from both sides of the call. The following steps accomplish this function. Note: it is assumed the chip is already in Normal Mode. 1. Select the ANA IN path through the SUM1 MUX. 2. Select the both SUM1 MUX input and the INPUT

SOURCE MUX INPUT to the SUM1 SUMMING amplifier (this also powers up the SUM1 SUMING AMP). This will mix both of the two inputs into the amplifier.

3. Select the SUM1 SUMMING amplifier path through the FILTER MUX.

4. Power up the LOWPASS FILTER. 5. Select the desired sample rate. 6. Select the LOW PASS FILTER input (only) to the

SUM2 SUMMING amplifier (this also powers up the SUM2 SUMMING AMP).

The output of the SUM2 Summing Amp drives the input to the ISD5008 analog storage array. As in Menu 70 above, the ANA IN audio path goes 2 directions: (1) to the Analog Storage Array and (2) to the Speaker driver section of the chip. The above requires a Configuration Register set up of: CFG0=4442h and CFG1=104Ch. This example assumes a recording sample rate of 4 KHz. After the ChipCorder has been configured to record the audio from the proper source, the recording may begin. The low-level routine "BEGIN_RECORD" is called to activate the recording function.

At this point, we are ready to exit this procedure and resume normal call-processing functions. We exit this procedure with the ChipCorder actively recording the incoming call. The termination of the recording takes place in an identical manner as was described in Menu 70. Menu 77 is used to playback this recording.

Menu 71: Activate two-way call record

Initialize ChipCorder:1. Establish address for message storage2. Setup to record from both "ANA IN"

and "Mic" inputs


Return

"Stop" key

Stop recording:Update message storage tables

Return

Periodic Timer interrupt:

Monitor ChipCorder functions:If full, then stop recording

Return

Flowchart 2


Flowchart 3, Menu 72: Activate voice memo record (see Figure 9 on page 9) The purpose of this function is to record from the local microphone into the storage array of the ChipCorder while the phone is in standby mode. This allows the user to record short memos for later playback. The first step is to initialize the ChipCorder and establish the storage address, and determine all of the control parameters required to configure it for this function. The message management routines are called to establish the address for storing the next recorded message. Then, the ChipCorder is configured to route the audio from the "MIC" input to the storage array so that the storage array can record the audio from the local microphone. The following steps accomplish this function. Note: since this recording operation normally occurs when the phone is not in use, it is assumed that the ISD5008 is totally powered down prior to beginning these steps: 1. Power up the AGC Amplifier. 2. Select the MIC path through the INPUT SOURCE MUX. 3. Select the INPUT SOURCE MUX input (only) to the SUM1 SUMMING Amplifier. This

also powers up the SUM1 Summing Amplifier. 4. Select the SUM1 SUMMING Amplifier path through the FILTER MUX. 5. Power up the LOWPASS FILTER. 6. Select the desired sample rate. 7. Select the FILTER input (only) to the SUM2 SUMMING Amplifier. This also powers up the

SUM2 SUMMING Amplifier. The output of the SUM2 Summing Amp drives the input to the ISD5008 analog storage array. The above requires a Configuration Register load of: CFG0=2421h and CFG1=0140h. This example assumes a recording sample rate of 8 KHz. 8. The PU bit should be set to power up the chip. After the ChipCorder has been configured to record the audio from the proper source, MIC IN, the recording may begin. The low-level routine "BEGIN_RECORD" is called to activate the recording function. The termination of the recording takes place in an identical manner as was previously described in Menu 70. After a memo has been recorded, Menu 77 is used to playback the recorded message. Note: since the ChipCorder handles the details of the recording process in hardware, there is a very low power consumption for this procedure; a majority of the cellular phone chipset components are left in a power-down state. The ChipCorder may be powered down after the completion of this procedure.

Menu 72: Activate voice memo record

Initialize ChipCorder:1. Establish address for message storage

2. Setup to record from "Mic" input


Return

Flowchart 3


Flowchart 4, Menu 73: Begin outgoing message record (See Figure 9 on page 9) The purpose of this function is to record the outgoing message (OGM) that will be used for the answering machine mode. In operation, the audio is recorded from the local microphone in an identical manner to that described in Menu 72 for Voice Memo Record. The only difference is that the recorded message is stored in a fixed location for playback during the answering machine mode, rather than storing the message in the next available location as the Voice Memo record normally does. Flowchart 5, Menu 74: Outgoing message playback (See Figure 10 on page10) The purpose of this function is to playback the OGM for review. In order to playback the outgoing message, the ChipCorder needs to be configured to route the audio output of the multilevel storage array to the speaker output. The following steps accomplish this function. Note: since this recording operation normally occurs when the phone is not in use, it is assumed that the ISD5008 is totally powered down prior to beginning these steps. 1. Select the MULTILEVEL STORAGE ARRAY path

through the FILTER MUX. 2. Power up the LOWPASS FILTER. 3. Select the sample rate (must be same as originally used

to record the OGM ). 4. Select the LOW PASS FILTER input (only) to the

SUM2 SUMMING Amplifier. This also powers up the SUM2 SUMMING Amplifier.

5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX.

6. Power up the VOLUME CONTROL LEVEL. 7. Select a VOLUME CONTROL LEVEL. 8. Select the VOLUME CONTROL path through the

OUTPUT MUX. 9. Power up the SPEAKER amplifier and select the HIGH

GAIN mode. The above requires a Configuration Register set up of: CFG0=2422h and CFG1=51D5h. This example assumes a recording sample rate of 6.4 KHz. 10. Set the PU bit to power up the chip.

Menu 74: Outgoing message playback

Initialize ChipCorder:1. Establish address of outgoing message

2. Setup for playback

Begin playback function

Return

Wait for playback end-of-message

Power-down ChipCorder

Flowchart 5

Menu 73: Begin outgoing message record

Initialize ChipCorder:1. Establish address for message

storage for outgoing message2. Setup to record from "Mic" input


Return

Flowchart 4


Once the ChipCorder has been configured to select and output the playback audio to the speaker, the playback of the OGM may begin. The low-level routine "BEGIN_PLAYBACK" is called to activate the playback function. The address of the outgoing message is determined by its recorded location as described in Menu 73. After the message playback has completed the ChipCorder is powered down. Flowchart 6, Menu 75: Activate answering machine mode The purpose of this function is to set the “flag” to activate the answering machine mode. This function works in conjunction with the next procedure described by Flowchart 7. When there is an incoming call, a method is needed to determine if the phone should ring normally and wait for the user to answer, or if it should automatically answer the phone and perform the answering machine functions. This flag is used to determine whether or not the answering machine mode is active. This procedure does not access any ChipCorder functions. Flowchart 7: Play Outgoing Message to the incoming Phone call and Record incoming Message (See Figure 11 on page 10 and Figure 12 on page11) The purpose of this procedure is to operate the record function of the answering machine mode. It watches for an incoming call, automatically answers the phone, plays the outgoing announcement or greeting (OGM), and records the incoming message from the caller into the local storage of the ChipCorder. The first step is to test the flag, described above in Flowchart 6, to determine whether or not the answering machine mode is active. If the flag is not set, then normal processing continues. If the answering machine mode is active, the next step is to auto-answer the phone. The appropriate routines or procedures within the GSM protocol are called to accomplish this step. The next step is to play the outgoing message. In order to play back the outgoing message from the multilevel storage array, the ChipCorder needs to be configured to route the audio output of the multilevel storage array to the ANA OUT output for the chipset. This ensures

Menu 75: Activate answeringmachine mode

Set flag for answering machine mode

Return

Flowchart 6

Incoming Call

Answering machine modeactive?

ResumeNormal

Processing

Auto-answer phone

Play outgoing message

Record incoming call

Return

No

Yes


Flowchart 7


the audio of the outgoing message may be transmitted to the caller. The following steps accomplish this: 1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX. 2. Power up the LOWPASS FILTER. 3. Select the sample rate (must be the same as the message was recorded.) 4. Select the LOW PASS FILTER input (only) to the SUM 2 SUMMING amp (This also

powers up the SUM 2 SUMMING amplifier.) 5. Select the SUM 2 SUMMING amp input to the VOL MUX. 6. Power up the VOLUME CONTROL 7. Select a VOLUME CONTROL level 8. Select the VOL path to the ANA OUT MUX. 9. Power up ANA OUT. The above requires a Configuration Register set up of: CFG0=2480h and CFG1=59D5h. This example assumes a recording sample rate of 6.4 KHz.

The microcontroller now starts the OGM playback by loading the proper address into the chip and initiating playback. The low-level routine "BEGIN_PLAYBACK" is called to activate the playback function. The microcontroller now watches for the end of the OGM message, signaled by an EOM interrupt from the ISD5008.

After the outgoing message has finished playing, the next step is to record the incoming call. This requires a change in the analog path setup so that the incoming call is passed to the analog storage array for recording. The incoming call audio is also passed to the speaker output so that the user has the option of monitoring the incoming call.

The first step is to initialize the ChipCorder and establish the storage address and all of the control parameters required to configure it for this function. The following steps continue the processing of the Answering Machine mode: 10. Power down ANA OUT. 11. Select the ANA IN path through the SUM1 MUX. 12. Select the SUM1 MUX input (only) to the SUM1 SUMMING amplifier. 13. Select the SUM1 SUMMING amplifier path through the FILTER MUX. 14. Select the desired sample rate. 15. Select the LOW PASS FILTER input (only) to the SUM2 SUMMING amplifier (this also

powers up the SUM2 SUMMING AMP). The output of the SUM2 Summing Amp drives the input to the ISD5008 analog storage array. Next the path is setup to monitor the call. 16. Select the ANA IN input through the VOL MUX. 17. Select a VOLUME CONTROL LEVEL. 18. Select the VOLUME CONTROL path through the OUTPUT MUX. 19. Power up the SPEAKER amplifier and select the HIGH GAIN mode. The above requires a Configuration Register load of: CFG0=4422h and CFG1=10C5h. This assumes a recording sample rate of 5.3 KHz. After the ChipCorder has been configured to record the audio from the proper source, ANA IN, the recording may begin. The low-level routine "BEGIN_RECORD" is called to activate the recording function.


After completion of the call, the recording process is terminated and the phone returns to normal standby operation. The ChipCorder should be placed in a power-down state when the phone is in its standby state. Menu 77 is used to playback recorded messages. Flowchart 8, Menu 76: Cancel answering machine mode The purpose of this function is to clear the flag to deactivate the answering machine mod and to return the machine to normal operation. This function is the complement of Menu 75. This procedure does not access any ChipCorder functions. Flowchart 9: Menu 77: Message playback (See Figure 10 on page 10) The purpose of this function is to begin playback of the recorded messages. There are several types of messages that the user may want to playback. These may be recordings of incoming calls recorded through menu selections 70 or 71, voice memos recorded through Menu selection 72, or incoming messages recorded while Answering Machine mode was activated via Menu selection 75. The designer may chose to provide a “sub menu” that allows the user to select what type of message to play. In order to playback the stored messages, the ChipCorder needs to be configured to route the audio output of the multilevel storage array to the speaker output. This is accomplished by the following steps: 1. Select the MULTILEVEL STORAGE ARRAY

path through the FILTER MUX. 2. Power up the LOWPASS FILTER. 3. Select the sample rate (must be same as

RECORD mode). 4. Select the LOW PASS FILTER input (only) to

the SUM2 SUMMING amplifier. 5. Select the SUM2 SUMMING amplifier path

through the VOLUME MUX. 6. Power up the VOLUME CONTROL LEVEL. 7. Select a VOLUME CONTROL LEVEL. 8. Select the VOLUME CONTROL path through

the OUTPUT MUX. 9. Power up the SPEAKER amplifier and select the HIGH GAIN mode.

Menu 76: Cancel answering machine mode

Clear flag for answering machine mode

Return

Flowchart 8

Menu 77: Message playback

Init ChipCorder:Setup for playback through speaker

Return

Begin loop: For all messages

Playback one message

Loop for all messages

Done


Flowchart 9


Once the ChipCorder is configured to select and output the playback audio to the speaker, the playback of the stored messages may begin. The low-level routine "BEGIN_PLAYBACK" is called to activate the playback function. After the playback function has completed, the ChipCorder is placed in a power-down state. Flowchart 10, Menu 78: Erase message The purpose of this function is to erase messages, that are no longer needed, from the storage array. The details of how this function operates are left up to the designer and how s/he wishes to implement them. For example, one method would allow each message to be kept or erased after being played. That is, after each message is played, the user would be given the choice to either play the next message (which would retain the current message) or to erase the current message. The action taken would depend on which key the user pressed. The low-level message management routines would be called to erase the message and update the message storage tables.

Menu 78: Erase message

User choice: keep or erase message

Return

Update storage tables to erase message

Flowchart 10


Appendix Configuration Register Set up

The charts and tables below map the Configuration Register programming for the ISD5008. Refer to these maps to determine how to configure the various paths, gains and power control bits in the device.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0

Configuration Register 0 (CFG0)

Volume Control Power DownSPKR & AUX OUT Control (2 bits)OUTPUT MUX Select (2 bits)ANA OUT Power DownAUXOUT MUX Select (3 bits)INPUT SOURCE MUX Select (1 bit)AUX IN Power DownAUX IN AMP Gain SET (2 bits)ANA IN Power DownANA IN AMP Gain SET (2 bits)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0

Configuration Register 0 (CFG0)

Volume Control Power DownSPKR & AUX OUT Control (2 bits)OUTPUT MUX Select (2 bits)ANA OUT Power DownAUXOUT MUX Select (3 bits)INPUT SOURCE MUX Select (1 bit)AUX IN Power DownAUX IN AMP Gain SET (2 bits)ANA IN Power DownANA IN AMP Gain SET (2 bits)

AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD

AGC AMP Power DownFilter Power DownSAMPLE RATE (& Filter) Set up (2 bits)FILTER MUX SelectSUM 2 SUMMING AMP Control (2 bits)SUM 1 SUMMING AMP Control (2 bits)SUM 1 MUX Select (2 bits)VOLUME CONTROL (3 bits)VOLUME CONT. MUX Select (2 bits)

Configuration Register 1 (CFG1)D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0

AGC AMP Power DownFilter Power DownSAMPLE RATE (& Filter) Set up (2 bits)FILTER MUX SelectSUM 2 SUMMING AMP Control (2 bits)SUM 1 SUMMING AMP Control (2 bits)SUM 1 MUX Select (2 bits)VOLUME CONTROL (3 bits)VOLUME CONT. MUX Select (2 bits)

Configuration Register 1 (CFG1)D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0

VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 AGPDFLPDFLD0FLD1FLS0

CONTROL MUX Select (2bits)


Configuration Register 0 Bit Map Volume Control Power Bit

Bit 0

(VLPD)

0 = Power ON

1 = Power OFF

SPEAKER and AUX OUT Control Bits

Bits 2,1

(OPA1, OPA0)

00 = Power down SPKR and AUX

01 = SPKR ON, HIGH GAIN, AUX Power down

10 = SPKR ON, LOW GAIN, AUX Power down

11 = SPKR Powered down, AUX ON

OUTPUT MUX Control Bits

Bits 4,3

(OPS1, OPS0)

00 = Source is VOL CONTROL (VOL)

01 = Source is ANA IN Input (ANA IN AMP)

10 = Source is LOW PASS FILTER (FILT0)

11 = Source is SUM2 SUMMING AMP (SUM2)

ANA OUT Power Bit Bit 5

(AOPD)

0 = Power ON

1 = Power OFF

ANA OUT MUX Control Bits

Bits 8,7,6

(AOS2, AOS1, AOS0)

000 = Source is MICROPHONE AMP (FTHRU)

001 = Source is INPUT MUX (INP)

010 = Source is VOLUME CONTROL (VOL)




110 = Unused

111 = Unused

INPUT SOURCE MUX Control Bit

Bit 9

(INS0)

0 = Source is Microphone AGC AMP (AGC)

1 = Source is AUX IN Input (AUX IN AMP)

AUX IN AMP Power Bit

Bit 10

(AXPD)

0 = Power ON

1 = Power OFF

AUX IN AMP Control Bits

Bits 12,11

(AXG1, AXG0)

00 = Input Gain = 1, OTLP input Level = 0.694

01 = Input Gain = 1.414, OTLP input Level = 0.491

10 = Input Gain = 2, OTLP input Level = 0.347


ANA IN AMP Power Bit

Bit 13

(AIPD)

0 = Power ON

1 = Power OFF

ANA IN AMP Control Bits

Bits 15,14

(AIG1, AIG0)


01 = Input Gain = 0.883, OTLP input Level = 0.7.l85




Configuration Register 1 Bit Map

AGC Power Control Bit

Bit 0

(AGPD)

0 = Power ON

1 = Power OFF

LOW PASS FILTER Power Control Bit

Bit 1

(FLPD)

0 = Power ON

1 = Power OFF

SAMPLE RATE and LOW PASS FILTER Control Bits

Bits 3,2

(FLD1, FLD0)

00 = Sample Rate = 8 KHz, FPB = 3.4 KHz

01 = Sample Rate = 6.4 KHz, FPB = 2.7 KHz

10 = Sample Rate = 5.3 KHz, FPB = 2.3 KHz

11 = Sample Rate = 4 KHz, FPB = 1.7 KHz

FILTER MUX Control bits

Bit 4

(FLS0)


1 = Source is Analog Memory Array (ARRAY)

SUM 2 SUMMING AMP Control Bits

Bits 6,5

(S2M1, S2M0)

00 = Source is both ANA IN AMP and FILT0

01 = Source is ANA IN Input (ANA IN AMP) ONLY

10 = Source is LOW PASS FILTER (FILT0) ONLY

11 = Power Down SUM2 SUMMING AMP

SUM1 SUMMING AMP Control Bits

Bit 8,7

(S1M1, S1M0)

00 = Source is both SUM1 and INP

01 = Source is SUM1 SUMMING AMP (SUM1) ONLY

10 = Source is INPUT MUX (INP) ONLY

11 = Power Down SUM1 SUMMING AMP

SUM1MUX Control Bits

Bit 10,9

(S1S1, S1S0)

00 = Source is ANA IN Input (ANA IN AMP)

01 = Source is Analog Memory Array (ARRAY)


11 = UNUSED

VOLUME CONTROL Control Bits

Bits 13,12,11

(VOL2, VOL1, VOL0)

000 = Attenuation = 0 dB








VOL MUX Control Bits

Bit 15,14 (VLS1, VLS0) 00 = Source is ANA IN Input (ANA IN AMP)



11 = Source is INPUT MUX (INP)


Notes on the programmable systems in the ISD5008: An analysis of the ISD5008 shows that there are 16 subsystems present in the chip that must be accounted for during Configuration Register Programming. These systems are: Amplifiers: 1) Pass Through +6 dB Microphone

Amplifier (connects to FTHRU input of ANAOUT MUX).

2) AGC amplifier with power control 3) AUX IN programmable gain Input

Amplifier with power control 4) ANA IN programmable gain Input

Amplifier with power control 5) SUM1 Summing Amplifier with power

control 6) SUM2 Summing Amplifier with power

control 7) ANA OUT differential Output

Amplifier with power control 8) Speaker Driver programmable gain

Output Amplifier and AUX OUT Output Amplifier with power control

Muxes (Audio Switches): 9) INPUT SOURCE MUX with 2 inputs 10) SUM1 MUX with 3 inputs 11) FILTER MUX with 2 inputs 12) ANAOUT MUX with 6 inputs 13) VOL MUX with 4 inputs 14) OUTPUT MUX with 4 inputs Volume Control: 15) VOLUME CONTROL with an 8 step

programmable attenuator and power control

Clock and Filter: 16) INTERNAL CLOCK and LOW PASS

FILTER with 4 programmable frequencies and sample rates with power control

Each system must be accounted for when the Configuration Registers are programmed. To conserve power, it is a good idea to power down any system when it is not in use. A brief description of the programming considerations for each subsystem follows: 1) Pass Through +6 dB Microphone Amplifier – This amplifier is not programmable and is

always powered up when the PU master Power Up bit is set. The differential microphone inputs of the chip independently feed this amplifier and the AGC Amplifier.

2) AGC amplifier with power control – This amplifier must be powered up whenever the microphone is to be connected through the INPUT SOURCE MUX to other parts of the chip.

3) AUX IN programmable gain Input Amplifier with power control – This amplifier must be powered up whenever its output is to be connected through the INPUT SOURCE MUX to other parts of the chip. One of the 4 programmable gain settings must be selected when this amplifier is used. It is not necessary to change the gain settings when the amplifier is powered down.

4) ANA IN programmable gain Input Amplifier with power control – This amplifier must powered up whenever its output is to be connected to other parts of the chip. One of the 4 programmable gain settings must be selected when this amplifier is used. It is not necessary to change the gain settings when the amplifier is powered down.

5) SUM1 Summing Amplifier with power control – This amplifier has 4 input states. Either input or both inputs may be selected. When both inputs are selected, the two signals are added together. The 4th state (both bits = “1”) powers this amplifier down.

6) SUM2 Summing Amplifier with power control – This amplifier has 4 input states. Either input or both inputs may be selected. When both inputs are selected, the two signals are added together. The 4th state (both bits = “1”) powers this amplifier down.


7) ANA OUT differential Output Amplifier with power control – This amplifier must be powered up anytime its output is needed.

8) Speaker Driver programmable gain Output Amplifier and AUX OUT Output Amplifier with power control – This system consists of 2 amplifiers. Both amplifiers are not on at the same time. Two of the control bit combinations select 2 gain settings for the Speaker Amplifier while the AUX Amplifier is disabled. The 3 combination enables the AUX Amplifier while the Speaker Amplifier is disabled. The 4th combination powers down both amplifiers.

9) INPUT SOURCE MUX with 2 inputs – The one control bit of the INPUT SOURCE MUX selects either of two inputs to transfer audio to other parts of the ISD5008. A mux cannot be powered down. (They consume only a few microamps of power).

10) SUM1 MUX with 3 inputs – The two control bits of the SUM1 MUX select one of 3 inputs to transfer audio to the SUM1 SUMMING Amplifier. The 4th state of the control bits is not used.

11) FILTER MUX with 2 inputs – The one control bit of the FILTER MUX selects one of 2 inputs to transfer audio to the LOW PASS FILTER.

12) ANAOUT MUX with 6 inputs – The 3 control bits of the ANAOUT MUX selects one of 6 inputs to transfer audio to the ANA OUT Differential Amplifier. Two of the control bit states are not used.

13) VOL MUX with 4 inputs – The 2 control bits of the VOL MUX select one of 4 inputs to transfer audio to the VOLUME CONTROL.

14) OUTPUT MUX with 4 inputs – The 2 control bits of the OUTPUT MUX select one of 4 inputs to transfer audio to the Speaker or AUX Output Amplifiers.

15) VOLUME CONTROL with an 8 step programmable attenuator and power control – The VOLUME CONTOL must be powered up to transfer audio through the system. The 3 bits control the attenuator setting. One of the 8 settings completely turns off the audio. It is not necessary to change the attenuator setting to power the system down. The setting of the VOLUME CONTROL may be changed at any time during playback.

16) INTERNAL CLOCK and LOW PASS FILTER with 4 programmable frequencies and sample rates with power control – This system must be powered up for record or playback operation or if the LOW PASS FILTER is to be used. It is not necessary to be recording or playing back to use the LOW PASS FILTER. The 2 control bits of this system select 4 possible sample rates and Low Pass Filter settings.


Configuration Register Setup Notes for Figures 5 through 11 General notes: 1) The AUX INPUT Amplifier is not used in any of the examples shown. The settings used for

all of the figures is AXPD=”1”, AXG0=”0” and AXG1=”0”. Note that the gain setting called for by these values is 1.0, but since the amplifier is powered down, any gain setting may be used.

2) The INPUT SOURCE MUX is always connected to the AGC, even when the AGC is powered down. For all figures, INS0=”0”.

3) The SUM1 MUX is always connected to the ANA IN Amplifier. For all Figures S1S0=”0” and S1S1=”0”.

Figure 5: Signal flow through the ISD5008 during normal/conversation mode: CFG0=4442 CFG1=11E2 1) The AGC Amplifier is powered up, AGPD=”0”.

2) ANA-IN powered up, AIPD=”0”, and is set for a gain of 0.883, AIG0=”1”, AIG1=”0”.

3) Both SUM1 and SUM2 SUMMING Amplifiers are powered down. S1M1, S1M0, S2M1 and S2M0 all equal “1”.

4) The ANA OUT DIFFERENTIAL OUTPUT Amplifier is powered up. AOPD=”0”.

5) The SPEAKER Amplifier is powered up in its high gain setting. OPA1=”0”, OPA0=”1”.

6) The FILTER MUX connects from the SUM1 SUMMING Amp. FLS0=”0”.

7) The ANA OUT MUX connects from INPUT MUX (INP). AOS2=”0”, AOS1=”0”, AOS0=”1”.

8) The VOLUME MUX connects from ANA IN Input (ANA IN AMP). VLS1=”0”, VLS0=”0”.

9) The OUTPUT MUX connects from VOL CONTROL (VOL). OPS1=”0”, OPS0=”0”.

10) The VOLUME CONTROL is powered up, VLPD=”0” and is set for an attenuation of 8 dB. VOL2=”0”, VOL1=”1”, VOL0=”0”.

11) The INTERNAL CLOCK and LOW PASS Filter are set for a sample rate of 8 KHz and 3.4 KHz respectively. FLD1=”0”, FLD0=”0”. The LOW PASS Filter is powered down, FLPD=”1”. Note: since the INTERNAL CLOCK and LOW PASS Filter are not being used in this setting, any value may be used for FLD1 and FLD0.

Figure 6: Alternative Signal Path through the Chip (Pass Through Mode): CFG0=4402 CFG1=11E3 1) The AGC Amplifier is powered down. AGPD=”1”.

2) ANA IN powered up, AIPD=”0”, and is set for a gain of 0.883, AIG0=”1”, AIG1=”0”.

3) Both SUM1 and SUM2 SUMMING Amplifiers are powered down. S1M1, S1M0, S2M1 and S2M0 all equal “1”.


5) The SPEAKER Amplifier is powered up in its high gain setting. OPA1=”0”, OPA0=”1”.



7) The ANA OUT MUX connects from MICROPHONE AMP (FTHRU). AOS2=”0”, AOS1=”0”, AOS0=”0”.




11) The INTERNAL CLOCK and LOW PASS Filter are set for a sample rate of 8 KHz and 3.4 KHz respectively. FLD1=”0”, FLD0=”0”. The LOW PASS Filter is powered down, FLPD= “1”. Note: since the INTERNAL CLOCK and LOW PASS Filter are not being used in this setting, any value may be used for FLD1 and FLD0.

Figure 7: Signal flow through the ISD5008 during one-way call record: CFG0=4442 CFG1=10C8 1) The AGC amplifier is powered up, AGPD=”0”.


3) The SUM1 SUMMING Amplifier is powered up with its input coming from the SUM1 MUX only. S1M1=”0” and S1M0=”1”.

4) The SUM2 Summing Amplifier is powered up with its input coming from FILTER OUT (FILT0). S2M1=”1” and S2M0=”0”.


6) The SPEAKER OUTPUT Amplifier is powered up in its high gain setting. OPA1=”0”, OPA0=”1”.


8) The ANA OUT MUX connects from INPUT MUX (INP). AOS2=”0”, AOS1=”0”, AOS0=”1”




12) The INTERNAL CLOCK and LOW PASS Filter is set for a sample rate of 5.3 KHz and 2.3 KHz respectively. FLD1=”1”, FLD0=”0”. The LOW PASS Filter is powered up, FLPD=”0”.

Figure 8: Signal flow through the ISD5008 during two-way call record: CFG0=4442 CFG1=104C 1) The AGC amplifier is powered up, AGPD=”0”


3) The SUM1 SUMMING Amplifier is powered up with both the SUM1 MUX and INPUT MUX signals being added together. S1M1=”0” and S1M0=”0”.

4) The SUM2 Summing Amplifier is powered up with its input coming from FILTER OUT (FILT0). S2M1= “1” and S2M0=”0”




7) The FILTER MUX connects from the SUM1 SUMMING Amp. FLS0=”0”

8) The ANA OUT MUX connects from INPUT MUX (INP), AOS2=”0”, AOS1=”0”, AOS0=”1”.




13) The INTERNAL CLOCK and LOW PASS Filter is set for a sample rate of 4.0 KHz and 1.7 KHz respectively. FLD1=”1”, FLD0=”1”. The LOW PASS Filter is powered up, FLPD=”0”.

Figure 9: Signal flow through the ISD5008 during voice memo record: CFG0=2421 CFG1=0140 1) The AGC amplifier is powered up. AGPD=”0”.

2) ANA-IN powered down, AIPD=”1”, and is set for a gain of 0.0625, AIG0=”0”, AIG1=”0”. Note: since ANA-IN is powered down, any gain setting may be used.

3) The SUM1 SUMMING Amplifier is powered up with its input coming from the INPUT MUX only. S1M1=”1” and S1M0=”0”.

4) The SUM2 Summing Amplifier is powered up with its input coming from the FILTER OUT (FILT0). S2M1=”1” and S2M0=”0”.

5) The ANA OUT DIFFERENTIAL OUTPUT Amplifier is powered down. AOPD=”1”.

6) The SPEAKER OUTPUT Amplifier is powered down. OPA1=”0”, OPA0=”0”.


8) The ANA OUT MUX connects from MICROPHONE AMP (FTHRU). AOS2=”0”, AOS1=”0”, AOS0=”0”. Note: since the ANA OUT DIFFERENTIAL OUTPUT is powered down, any value may be used for this setting.

9) The VOLUME MUX connects from ANA IN Input (ANA IN AMP). VLS1=”0”, VLS0=”0”. Note: since the VOLUME CONTROL is not being used, any value may be used for this setting.

10) The OUTPUT MUX connects from VOL CONTROL (VOL). OPS1=”0”, OPS0=”0”. Note: since the SPEAKER OUTPUT is powered down, any value may be used for this setting.

11) The VOLUME CONTROL is powered down, VLPD=”1” and is set for an attenuation of 0 dB. VOL2=”0”, VOL1=”0”, VOL0=”0”. Note: since the VOLUME CONTROL is powered down, any value may be used for the attenuation setting.

14) The INTERNAL CLOCK and LOW PASS Filter is set for a sample rate of 8 KHz and 3.4 KHz respectively. FLD1=”0”, FLD0=”0”. The LOW PASS Filter is powered up. FLPD=”0”.


Figure 10: Signal flow through the ISD5008 during message playback: CFG0=2422 CFG1=51D5 1) The AGC amplifier is powered down. AGPD=”1”.

2) ANA-IN powered down, AIPD=”1” and is set for a gain of 0.625, AIG0=”0”, AIG1=”0”.

3) The SUM1 SUMMING Amplifier is powered down with S1M1=”1” and S1M0=”1”.

4) The SUM2 Summing Amplifier is powered up with its input coming from FILTER OUT (FILT0). S2M1=”1” and S2M0=”0”.



7) The FILTER MUX connects from the Analog Memory Array. FLS0=”1”.

8) The ANA OUT MUX connects from MICROPHONE AMP (FTHRU), AOS2=”0”, AOS1=”0”, AOS0=”0”. Since the ANA OUT DIFFERENTIAL OUTPUT is powered down, any value may be used for this setting.

9) The VOLUME MUX connects from SUM2 SUMMING AMP (SUM2). VLS1=”0”, VLS0=”1”.


11) The VOLUME CONTROL is powered up. VLPD=”0” and is set for an attenuation of 8 dB. VOL2=”0”, VOL1=”1”, VOL0=”0”.

12) The INTERNAL CLOCK and LOW PASS Filter is set for a sample rate of 6.4 KHz and 2.7 KHz respectively. FLD1=”0”, FLD0=”1”. The LOW PASS Filter is powered up. FLPD=”0”.

Figure 11: Signal flow through the ISD5008 during OGM play to phone: CFG0=2480 CFG1=59D5 1) The AGC amplifier is powered down, AGPD=”1”

2) ANA-IN powered down, AIPD=”1”, and is set for a gain of 0.625, AIG0=”0”, AIG1=”0”. Note: since the ANA-IN Amplifier is powered down, any value may be used for the gain setting.

3) The SUM1 SUMMING Amplifier is powered down with S1M1=”1” and S1M0=”1”.

4) The SUM2 Summing Amplifier is powered up with its input coming from FILTER OUT (FILT0), S2M1=”1” and S2M0=”0”.


6) The SPEAKER OUTPUT Amplifier is powered down. OPA1=”0”, OPA0=”0”.

7) The FILTER MUX connects from the Analog Memory Array. FLS0=”1”.

8) The ANA OUT MUX connects from VOLUME CONTROL (VOL). AOS2=”0”, AOS1=”1”, AOS0=”0”.

9) The VOLUME MUX connects from SUM2 SUMMING AMP (SUM2). VLS1=”0”, VLS0=”1”.

10) The OUTPUT MUX connects from VOL CONTROL (VOL). OPS1=”0”, OPS0=”0”. Note: since the SPEAKER OUTPUT is powered down, any value may be used for this setting.


11) The VOLUME CONTROL is powered up, VLPD=”0” and is set for an attenuation of 12 dB. VOL2=”0”, VOL1=”1”, VOL0=”1.

12) The INTERNAL CLOCK and LOW PASS Filter are set for a sample rate of 6.4 KHz and 2.7 KHz respectively. FLD1=”0”, FLD0=”1”. The LOW PASS Filter is powered up, FLPD=”0”.

Figure 12: Signal flow through the ISD5008 during ICM Record from Phone Line: CFG0=4422 CFG1=10C5 1) The AGC amplifier is powered up down, AGPD=”1”

2) ANA-IN powered up and is set for a gain of 0.883, AIG0=”1”, AIG1=”0”.

3) The SUM1 SUMMING Amplifier is powered up with its input coming from the SUM1 MUX, S1M1=”0” and S1M0=”1”.

4) The SUM2 Summing Amplifier is powered up with its input coming from FILTER OUT (FILT0), S2M1=”1” and S2M0=”0”.




8) The ANA OUT MUX connects from MICROPHONE AMP (FTHRU). AOS2=”0”, AOS1=”0”, AOS0=”0”. Note: since the ANA OUT DIFFERENTIAL OUTPUT is powered down, any value may be used for this setting.

9) The VOLUME MUX connects from ANA IN Input (ANA IN AMP), VLS1=”0”, VLS0=”0”.

10) The OUTPUT MUX connects from VOL CONTROL (VOL), OPS1=”0”, OPS0=”0”.


12) The INTERNAL CLOCK and LOW PASS Filter are set for a sample rate of 6.4 KHz and 2.7 KHz respectively. FLD1=”0”, FLD0=”1”. The LOW PASS Filter is powered up, FLPD=”0”.


}

Configuration Register Notes: 1. Important Note: All changes to the internal settings of the ISD5008 are synchronized with

the load of Configuration Register 1. A command to load Configuration Register 1 immediately transfers the input data to the internal settings of the device and the changes take place immediately at the end of the command when SS\ goes HIGH. A load to Configuration Register 0 sends the new data to a temporary register in the ISD5008 and does not affect the internal settings of the device. The next time Configuration Register 1 is loaded, data will also transfer from the temporary register to the Configuration 0 Register and effect the desired changes. See Appendix Figure 1 below:

Temporary Register Configuration Register 0 Configuration Register 1 Input Shift Register (16 bits) →→→→ MOSI Control Word (C7-C0)

Appendix Figure 1 2. Configuration Registers may be loaded with data at any time, including when the chip is

powered down using the PU bit in the SPI Control Register. The PU bit in the SPI Control Word must be set to a “1” before the changes in configuration are seen.

3. All bits of the configuration registers must be correctly set each time the registers are programmed.

Command = Load Configuration Register 1

Command = Load Configuration Register 0 {

Documents

Reference Interface Design between ISD5008 ChipCorder