Reduction of Register File Reduction of Register File Power ConsumptionPower Consumption

Approach:Approach: Value Lifetime Value Lifetime CharacteristicsCharacteristics

- Pradnyesh Gudadhe

Paper being presented:Paper being presented:

• Reducing Register File power Reducing Register File power Consumption by Exploiting Value Consumption by Exploiting Value Lifetime CharacteristicsLifetime Characteristics– Zhigang HuZhigang Hu– Margaret MartonosiMargaret Martonosi

(Department of Electrical Engineering,(Department of Electrical Engineering,Princeton university )Princeton university )

Source:Source: Workshop on Complexity Effective Workshop on Complexity Effective Designs (WCED), (held in conjunction with Designs (WCED), (held in conjunction with ISCA-27), June 2000. ISCA-27), June 2000.

ScenarioScenario

• Trend towards wider instruction issue Trend towards wider instruction issue and larger instruction windowand larger instruction window

• Size and number of Read/Write ports Size and number of Read/Write ports of register file is increasingof register file is increasing

• Register file consumes substantial Register file consumes substantial amount of poweramount of power

• Register accesses show good Register accesses show good temporal localitytemporal locality

• Register values are short lived. (30-Register values are short lived. (30-65%)65%)

IntroductionIntroduction

Instructionmemory

Address

4

32

0

Add Addresult

Shiftleft 2

Inst

ruct

ion

IF/ID EX/MEM MEM/WB

Mux

0

1

Add

PC

0

Address

Writedata

Mux

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

Datamemory

1

ALUresult

Mux

ALUZero

ID/EX

Register file in 5-stage Register file in 5-stage pipelinepipeline

• Has 6 portsHas 6 ports– 4 input ports ( 3 – register number, 1 write data )4 input ports ( 3 – register number, 1 write data )– 2 output ports ( 2 – registers read from register 2 output ports ( 2 – registers read from register

file)file)

• Write register number input port and write Write register number input port and write register data port are active in write back register data port are active in write back stagestage

• Number of ports increases in multiples of the Number of ports increases in multiples of the cores added in multicore scenario.cores added in multicore scenario.

• Register file accessed more extensively in Register file accessed more extensively in case of multicore scenario.case of multicore scenario.

Why register file power Why register file power consumption?consumption?

• In the Motorola M.CORE architecture, the register file consumes 16% of the total processor power and 42% of the data path power.

•Register file power may reach 25% of the total processor power when running embedded applications.

•Due to the comparatively small size of the register file, the power density (power per unit area) of the register file is very high.

Contribution towards the Contribution towards the problem:problem:

• Solution:Solution: Reduce the number of register file accesses.

• Idea:Idea:

•Have a “holding talk” to buffer results between Functional Units and register File.

•This holding tank is “Value Aging Buffer”

•This will reduce Register file access and hence reduce power consumption.

Decode: Physical Register Assigned if instruction produces value

Physical register filled with data atInstruction completion (Write Back)

Following instructions fetch data fromResults bus or physical register

Pre-Value

Active Value

Value kept since last use, in case of misprediction or exception

Free the value when new instruction with same physical register destination is

committed successfully.

Save for exception

Value Lifetime Value Lifetime CharacteristicsCharacteristics

• Pre-Value:Pre-Value: Time period between register Time period between register tag has been allocated and value tag has been allocated and value produced.produced.

• Active Value:Active Value: Time period between value Time period between value first produced and put in a register until first produced and put in a register until last read or write that uses the value.last read or write that uses the value.

• Save for Exception:Save for Exception: Time for which Time for which value is kept since it was last used until it value is kept since it was last used until it can be freed.can be freed.

• Note:Note: Active Value has average length of 3-4 Active Value has average length of 3-4 cycles. (Very less as compared to others.)cycles. (Very less as compared to others.)

Value Aging Buffer (VAB)Value Aging Buffer (VAB)

Value Aging Buffer (VAB)Value Aging Buffer (VAB)

• FIFO BufferFIFO Buffer• VAB stores:VAB stores:

– Physical register numberPhysical register number– DataData– Valid bitValid bit

• Number of entries:Number of entries: ~ 1/4~ 1/4thth of number of physical registers of number of physical registers• VAB postpones register file accessesVAB postpones register file accesses

Register read using VABRegister read using VAB

• Look for register in VAB,Look for register in VAB,– If found, then fetch the value from VABIf found, then fetch the value from VAB– If not found, then fetch it from register file If not found, then fetch it from register file

with one cycle extra penalty. (Rare)with one cycle extra penalty. (Rare)

• VAB Miss Rate = No. of misses in VAB VAB Miss Rate = No. of misses in VAB

Total no. of read Total no. of read requestsrequests

Register Write using VABRegister Write using VAB

• Value produced by functional units is Value produced by functional units is added to VAB.added to VAB.

• If VAB is full, then oldest VAB entry is If VAB is full, then oldest VAB entry is evicted.evicted.

• VAB Eviction Rate = Ratio of VAB entriesVAB Eviction Rate = Ratio of VAB entries

evicted to register evicted to register file.file.

Freeing a register using VABFreeing a register using VAB

• When? When? – Misprediction or ExceptionMisprediction or Exception– Another instruction with same Another instruction with same

destination register is committed.destination register is committed.

• VAB entry freed by resetting the VAB entry freed by resetting the valid bitvalid bit

Exception & Misprediction Exception & Misprediction HandlingHandling

• Exceptions: VAB is dumped into Exceptions: VAB is dumped into register fileregister file– Rare:Rare: Impact on performance & power is Impact on performance & power is

lessless

• Misprediction: High penalty.Misprediction: High penalty.– VAB passed in the branch stack, so that VAB passed in the branch stack, so that

VAB content can be copied quickly.VAB content can be copied quickly.

VAB with Location bitVAB with Location bit

• One extra cycle if value not found in One extra cycle if value not found in VAB.VAB.– Major source of performance lossMajor source of performance loss

• Store 1 bit per Physical Register to Store 1 bit per Physical Register to indicate its location.indicate its location.= 1 if register is in VAB= 1 if register is in VAB

= 0 if register is in register file= 0 if register is in register file

• Map of physical register numbers and Map of physical register numbers and location bits, before accessing VAB or location bits, before accessing VAB or register file to make decision.register file to make decision.

Statistics 1 of 3Statistics 1 of 3

• 16 entry VAB 16 entry VAB captures 50-70% captures 50-70% of read-requests. of read-requests.

• Only 26-56% of all Only 26-56% of all values produced values produced need to be saved need to be saved in register filein register file

Statistics 2 of 3Statistics 2 of 3

• Cons: 5% less Cons: 5% less IPCIPC

But….. But…..

• Saves about Saves about 30% of register 30% of register file power.file power.

Statistics 3 of 3Statistics 3 of 3

• Same Same performance in performance in with and without with and without VAB.VAB.

• 9% power 9% power saving.saving.

Impact on CSE 520Impact on CSE 520

• A new power reduction techniqueA new power reduction technique

• Motivation to come up with VAB Motivation to come up with VAB design for multicore architecture.design for multicore architecture.

• Register file is a crucial element in Register file is a crucial element in data path which decides cycle width. data path which decides cycle width. And hence, performance, IPC, And hence, performance, IPC, throughput, power consumption; throughput, power consumption; everything depends on it.everything depends on it.

• Key factor to improve CPU’s overall Key factor to improve CPU’s overall performance and efficiencyperformance and efficiency

Impact on the project:Impact on the project:

• The project:The project:– Simulation of 5-stage pipelined datapath Simulation of 5-stage pipelined datapath

with Value Added Bufferwith Value Added Buffer

• Aim:Aim:– Simulation of 5-stage pipelineSimulation of 5-stage pipeline– Integrating VAB in the 5-stage pipeline Integrating VAB in the 5-stage pipeline

simulationsimulation– Performance measurement of simulated Performance measurement of simulated

processor with and without VAB.processor with and without VAB.– Exploring further improvement tacticsExploring further improvement tactics

Project Details:Project Details:

Opportunities in the project:Opportunities in the project:

• Exact, strategic placement of VAB in Exact, strategic placement of VAB in datapathdatapath

• Possibilities of reducing register file portsPossibilities of reducing register file ports

• Analysis of register file accesses dataAnalysis of register file accesses data

• Impact of VAB on performanceImpact of VAB on performance

• Experience of actually implementing theory Experience of actually implementing theory proposed by the paper may highlight some proposed by the paper may highlight some cons of the concept.cons of the concept.

• Validating proposed theoryValidating proposed theory

• Verifying functionalities of VABVerifying functionalities of VAB

THANK YOU! THANK YOU!

Questions?