Mrs. M.MANIKUMARI, Name: R.S.G.BHAVANI, Assistant Professor,
Regd. No: 12JG1D6804,Department of ECE M.TECH (VLSI&ES) GVP
College of Engg for Women GVP College of Engg for Women
ABSTRACT In DSM technologies, interconnect can no longer be seen
as a simple resistor but the associated parasitic such as
capacitance and inductance also need to be considered. Thus any
signal propagating through such an interconnect can be expected to
be delayed.
The increasing RC delay for interconnects becomes a critical
issue for high performance and also consumes more power in VLSI
technology.
Buffer insertion and Schmitt trigger techniques are used to
reduce the RC delay.
INTRODUCTIONInterconnects on the VLSI chips are used to
distribute the clock and other signals to the functional blocks of
whole system as well as provide the power supply and ground
connections.
With the technology scaling, the dimensions of local wires also
scale down, resulting in the increasing RC product. As a result,
the increasing RC delay for interconnects becomes a critical issue
for high performance and also consumes more power in VLSI
technology.
The total RC delay of an interconnect line can be reduced
drastically with the insertion of a signal amplifier known as a
repeater.
Existing techniques to reduce delay in VLSI interconnects
are:
Schmitt Trigger Technique Buffer Insertion is a very effective
approach for delay reduction. But a large number of such buffers
can contribute overall delay in signal propagation.
Schmitt trigger is an alternate to buffer to reduce delay and
power in interconnects. The adjustable low-voltage threshold of the
Schmitt trigger handles more noise and voltage glitches as compared
to buffer.
TOOLS REQUIRED:Tanner S-Edit and L-EditHSPICE simulator Tanner
S-Edit and L-Edit is used to design transistor level schematic and
Layout.
The HSPICE simulator is used to measure the Delay and Power.
