Reconfigurable OTA C

8/11/2019 Reconfigurable OTA C

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Fig.1 A Low Voltage FGMOS Integrator.

Previous results show that varying the bias current isresults in a tuning range of 2.7 [10]. Varying current alone,however, is not suitable to achieve wide tuning range. Thus,

programming the input capacitance is also considered

B. Proposed Reconfigurable FGMOS OTA

Tuning the input capacitance will require the use ofswitches at the input. The objective is to ensure that the rightcommon mode voltage is applied to the FGMOS OTA even ifthe input capacitance is changed. A novel scheme that allowssuch reconfigurability is illustrated in Fig. 2. In thisimplementation, the FGMOS transconductor has three inputcapacitors and two programmable inputs.

Programming the input capacitance is achieved by using a2:1 multiplexer block at each of the two inputs. Themultiplexer is used to select which of the 2 input voltages getconnected to the input capacitance. Consider the inputcapacitor C 1A, 2 select signals S 1 and S CM are used to choose

which voltage between the input V in or the bias voltage V CM isfed to the input capacitor. With S 1 asserted, V in is connectedto C 1A thereby contributing to the total C in of thetransconductor. When S CM is asserted, V CM gets connected toC 1A which effectively removes C 1As contribution to C in.

For the design of the CMFB, each of the input capacitanceis further divided into 2 to accommodate the 2 inputs. Thus,transistor M3 will now have 4 inputs with 4 multiplexers thatare controlled in the same manner as those used for transistorsM1 and M2. The magnitude of the original C in must be chosensuch that the magnitude of C GD is still much smaller for M3.

To design the reconfigurable FGMOS OTA, the lowvoltage FGMOS shown in Fig. 1 is first designed. Using the

power-constrained design approach [10], the main goal is todetermine the circuit parameters that will improve the OTAs! %. The main trade-offs considered in [10] was the variationof ! % with circuit parameters, I BIAS , C in /C T and ! eff . Lower biascurrents contribute to better efficiency. A bigger ! eff contributeto higher ! % but must be minimized as this leads to biggerC GD requiring a larger C T . A larger capacitance ratio C in /C T also contributes to higher ! % but this lowers C R /C T in theCMFB that controls the common mode response of the OTA.

With a target V DD=1.8V, using an ! eff =1mA/V2 provides a

good range of V CM values from 0.7V to 1.3V for an I BIAS rangeof 20-200 A. Fixing the common mode voltage to 0.9V will

Fig.2 A Reconfigurable FGMOS OTA.

TABLE ITRANSISTOR PARAMETERS OF THE TRANSCONDUCTOR

Transistor W/L (m) (mA/V 2) V OV (mV)M1 6/1 1.065 300M4 15/1 2.663 200M7 70/5 761.3 350

require a current of 50 A. To ensure better common modecontrol, a C in/C T=0.5 was chosen. With these parameters, a

transconductance efficiency of 20 achieved. A summary of thetransistor dimensions is given in Table I. Given the size of M1,a C GD of 1.5fF was observed. To minimise the effect of this

parasitic capacitance, a C in=C R=360fF was used.To implement the reconfigurable OTA, the original input

capacitance of C in=360fF was divided into two smallercapacitances, C 1A=240fF and C 1B=120fF which are two-thirdsand a third of the original capacitance respectively. In termsof tuning, the input capacitance of the transconductor can now

be programmed by using either C 1A or C 1B as C in. A tuningrange of 3 is achieved using these ratios. For discussion, thestate S 1=S 2=1 is referred to as the Max state while the stateS 1=0, S 2=1 is considered as the Min state . Note that to

function as an OTA, a state where both control signals areinactive is not allowed.For wider tuning range, the input capacitance can be

divided further into several smaller units requiring morecontrol signals to program the transconductor. Dividing C in into smaller units may require a larger C in/C T than the 0.5 usedin this implementation. This is to ensure that the scale of theinput capacitance is still large enough to minimise the effectof C GD on the performance of the transconductor.

One drawback in using multiplexers in this reconfigurableFGMOS OTA is the additional poles and zeroes introduced.The multiplexers are implemented using CMOS transmissiongates (TG) which are basically a parallel combination of a

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PMOS and a NMOS transistor. In the implementation, thePMOS transistor used has twice the width of the NMOStransistor. This topology is used to ensure that the switch isimmune to V th swing limitations encountered in low voltagecircuits [6]. The dimensions of the transistors used in the TGaffect the bandwidth of the transconductor. Each TGcontributes a resistance R to the input path affecting theOTAs bandwidth.

The RC network formed by the TGs introduces two polesand a zero to the OTAs transfer response thereby affecting its

bandwidth. With a reconfigurable input, it was observed thatthe location of the zeroes changed with the input state. Thiszero occurs at the lowest frequency for the Min state while itis highest at the Max state. Note that the location of the polesdoes not change with the states.

Wider switches are needed to operate at higher frequencies.From simulations, the bandwidth decreases from 287MHzto 78MHz as the NMOS width W S is reduced from 8m to2m. A bigger W S is preferable to ensure high frequency

applications but this in turn presents loading problems in thedesign of the filter. A W S =3m is thus chosen as acompromise between good bandwidth and smaller parasitics.

A summary of the AC performance of the FGMOStransconductor is given in Table 2 as a function of the inputcapacitance where Max C in /C T refers to C in /C T =1/2 and Min C in /C T refers to C in /C T =1/6. It is observed that a BW beyond80MHz is obtained. To determine the phase error, a loadcapacitance of 7pF is used which is the same magnitude usedin the filter. The phase errors observed are sufficient in thedesign of a third order Butterworth filter.

The effective dynamic range (DR) of the transconductorremains almost constant at 70dB as shown in Table 3. While

linearity improves at with smaller C in /C T due to signalattenuation at the input, the larger attenuation in the signaltranslates to higher noise referred at the input. Note that thisrelatively constant DR with capacitance tuning is ideal as thissimplifies design trade-off considerations as the circuit istuned. Programming C in /C T however, affects the efficiency ofthe circuit.

The bias voltage is also varied for the different C in /C T casesto evaluate the performance of the FGMOS transconductor.As the bias current decreases with V B, it is observed fromTable 4 how the DR decreases due to higher noise levels andlower linearity. With lower power consumption smaller DR isobserved. A DR of 63dB is achieved with a power of 29.4 W.

An increased tuning range is achievable with thereconfigurable FGMOS transconductor. Smaller currents for aV B=1.0V case in conjunction with a smaller C in /C T provide agm=6.4S. Using this bias condition, a DR of 60dB isobserved for the same power of 29.4 W. On the opposite end,higher currents at V B=0.6V and larger C in /C T allow for ahigher transconductance of 76.4S and a DR of 75dB for a

power consumption of 472 W. Thus, a tuning range of 12 isachieved at no extra power consumption. This is made

possible by the simplicity of the transconductor and theversatility provided for by using an FGMOS circuit.

TABLE IIAC PERFORMANCE OF THE R ECONFIGURABLE FGMOS OTA

Min C in /C T Mid C in /C T Max C in /C T Short Circuit

gm,diff (S) 20.49 40.92 61.4BW(GHz) 125.7 82.55 99.75

Open CircuitR OUT (! ) 2.63M 2.63M 2.63M

Capacitor Loadf T(Hz) 465.9k 930.4k 1.396M

Phase () -89.08 -90.11 -90.43

TABLE IIIDYNAMIC R ANGE OF THE R ECONFIGURABLE FGMOS OTA

Min Mid Max g m,diff 20.49 40.92 61.4

vin@THD=-40dB (mV) 715 465 314Vn,RMS (V) 173.5 86.92 57.91

DR (dB) 69.3 71.56 71.67Power ( W) 278.6 278.6 278.6

%(1/V2

) 7.35 14.7 22TABLE IV

THE R ECONFIGURABLE FGMOS OTA FOR MAX STATE

VB=0.6V V B=0.725V V B=1.0V g m,diff 76.38 61.62 19.08

vin@THD=-40dB (mV) 490 314.4 175Vn,RMS (V) 57.2 57.9 81.59

DR (dB) 75.65 71.67 63.62Power ( W) 471.87 278.6 29.4

%(1/V2) 16.19 22 64.8

III. A THIRD ORDER BUTTERWORTH LOW PASS FILTER A third order Butterworth filter was implemented using the

novel reconfigurable FGMOS OTA. For a target operatingfrequency of 2.5MHz and a Gm,unit =60 S, the load capacitanceneeded were two 7pF capacitor for the gyrator and one 14pFcapacitor for the filter. Initial simulations, however, showedthat the cut-off frequency was smaller by 600kHz from theideal response. This is attributed to the increased capacitiveload seen by the OTAs due to the switches used. The parasiticcapacitance attributed to the TG network is made up of, C GS ,C GD , C GS,ovl , C GD,ovl , and junction capacitance C JS , and C JD for

both the PMOS and NMOS transistors. Thus, each of the loadcapacitors was modified to account for the switch parasitics.

With these newer values, the filter response was againsimulated and the new response is illustrated in Fig. 3 for thedifferent states. From an initial difference of 22.2% with theideal response, it was reduced to 3.85%. Note that the

parasitic capacitance seen by the filter varies for the differentstates from 8 TGs for the Max state to 4 TGs in the Mid and

Min state . Simulations show that with the modified loadcapacitances, the filter follows closely the ideal response forthe Min and Mid state . The small difference of 100kHz in thecut-off frequency for the Max state is acceptable given the

programmable nature of the filter and good response derivedfor the other states.

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Fig. 3 A Summary of the Filter Response with an adjusted load.

Tuning the filter using the input switches and the biasvoltage V B, the filter cut-off frequency was programmed from240kHz to 3.8MHz. This wide tuning range of 12.4 wasachieved for power consumption under 4mW. The lowest cut-off frequency is achieved with V B=1V at the Min state . A DR

of 57dB is achieved for a power consumption of 235W. Thehighest cut-off frequency is achieved with a V B=600mV at the Max state . Increased current levels contributed to higherlinearity and lower noise resulting in a DR of 63.6dB for a

power consumption of 3.8mW. The performance of the filterdesigned is compared to other multi-standard low pass filtersin Table 5. The results obtained prove that the FGMOS OTAoffers a good trade-off in terms of tuning range, powerconsumption and linearity.

IV. CONCLUSIONS The simplicity of the FGMOS OTA permits higher operatingfrequencies at lower power consumption. This bandwidth can

be traded off for increased programmability by using amultiplexer based capacitance tuning for the FGMOS. Usingadditional transmission gates provides the flexibility toreconfigure the FGMOS OTA to achieve wider tuning, but

presents design challenges to operate at higher frequencies. Inaddition, the additional switching network present higher

parasitic capacitances that will require the modification of theload capacitance used in an active filter. With a properunderstanding of the performance trade offs, a third orderButterworth g m-C ladder filter was implemented using thenovel OTA circuit. The tuning range achieved was 12.4 whileconsuming a maximum power of 3.8mW. The DR obtainedwas 63.6dB at maximum power while it was 57dB at a

minimum power of 235 ! W.

ACKNOWLEDGMENT

The author would like to acknowledge the EngineeringR&D for Technology (ERDT) Faculty Development ForeignScholarship and the University of the Philippines DoctoralStudies Fund for the financial support received.

R EFERENCES

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[6] A.M. Durham et al., High-linearity continuous-time filter in 5 V VLSICMOS, IEEE J. Solid State Circuits, vol. 27, no.9, pp. 1270-76, Sept.1992.

[7] S. Pavan et. al., Widely programmable high frequency continuoustime filters in digital CMOS technology, IEEE J. Solid-state Circuits,vol. 35, pp.503-511, Apr. 2000.

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TABLE VCOMPARISON W ITH OTHER ACTIVE FILTERS

Ref Topology Tech(m)

Filter Order Power(mW)/Supply (V)

Tuning(MHz)

Noise IIP3

[11] Active-RC 0.35 3rd, 5th Butt 3.4-12.7 / 2.7 0.13-2.1 17.47Vrms 45dBm[12] g mC 0.13 2nd Butt 0.12-14.2 / 1.2 0.1-20 25-35 Vrms 10dBVp[13] g mC 0.25 3rd Butt 2.5-7.3 / 2.5 0.05-2.2 35-500nV/sqrt(Hz) 12-18 dBVp[14] g mC 0.25 3rd, 5th Butt 1.7-3.3 / 1.2 0.1-2.75 40-1000nV/sqrt(Hz) 9-14dBVp[15] g mC 0.18 3rd Butt 4.1-11.1 / 1.8 0.5-20 12-425nV/sqrt(Hz) 19-22dBm[16] g mC 0.18 3rd Butt 1.57-1.92 / 1 0.135-2.2 65nV/sqrt(Hz) 19-23dBm

FGMOS g mC 0.35 3rd Butt 0.24-3.8 / 1.8 0.25-3.1 89.83-155 Vrms 13-16dBm

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Reconfigurable OTA C