Rec3 Final

8/13/2019 Rec3 Final

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CSE241 Synthesis Overview.1 Kahng & Cichy, UCSD 2003

CSE241AVLSI Digital CircuitsWinter 2003

Recitation 3: Synthesis


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Logic Synthesis: explained

Logic synthesis:Process of transforming Hardware Description Language (HDL)code into a logic circuit

HDLVDHLVerilog (well only use Verilog RTL)

The circuitry:Structural-level HDL netlist

Components from a technology specific library


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Logic SynthesisLogic synthesis converts a software code into a connected set astandard cells

Real cell properties must be accounted in order to insure thatthe actual circuit will perform correctly:

Propagation Delay through cellsConnection Delay between cells

Load CapacitanceDrive ResistanceSlew rate (10%- 90% v)

Area of CellsClock rates

Setup & Hold timesPower Consumption


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Ideal is converted into Real

case (Sel)

2'b00 : status


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Synthesis Related File Types

Script file .scr

Verilog file .v

Synthesized Verilog file .sv

VHDL file .vhd

Synthesized VHDL files .svhd

EDIF file .edif

Synopsys database file .db

Reports .rpt

Log file(standard for most tools).log


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Synthesis Related File Types

Library File .lib

TCL script file .tcl

Ambit Library Format file .alf

Ambit Database file .adbMagma Database file .volcano

Command file .cmd

Standard Delay Format file .sdf

Standard Parasitics Exchange

Format .spef


7/32CSE241 Synthesis Overview.7 Kahng & Cichy, UCSD 2003

Synthesis Data Flow

HDLCode TechLibrary Constraints

SynthesisTool

Gate Level Netlist

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Step 1: Synthesis Setup

Setup accomplished through setup files and global shellvariables

Synopsys (.synopsys_dc.setup & script)

Setup directories (example: Project is called Lab2)

Script (/ee260b/ee260b/lab2/script)Reports (/ee260b/ee260b/lab2/reports)Libaries (/ee260b/ee260b/lab2/libraries) (local)Verilog (/ee260b/ee260b/lab2/src)


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Reading a Library

Synopsys: read_db msi_10k.db

If the .db library file doesnt exist then it must be created fromthe .lib library file (vendor supplied)

.lib is readable by the user , .db is internal format

Use library compiler to create the.db. [ libcompilemsi_10k.lib -> msi_10k.db ] Library Compiler

- Checks the .lib for errors

- Translates to .db



Purpose of the Library

The Library contains the cells of the technology (.18,.13u)

Cells are Building Blocks for the circuit Must use technology library for physical properties

Synthesis tools considers properties and function of cellsThe key properties:- Cell delay- Rise/fall transitions- Capacitive load- Drive strength- Area and power

Delay Total = Delay Cell + Delay Wire



Contents of a Library

Units (V, A, pW, KOhm, nS, etc)

Default parametersMax transitionInput pin capWireload modeOperating conditionMax fanout

Nominal Parameters (PVT)

Operating ConditionsWorst Case /Best Case

Scaling factorsK Factors

Wireload ModelsEstimate for fan-in, fan-out

Look-up table templates

Cells: all properties & attributes, Delay Tables, Rise/FallTransition Tables, Power Tables



Wireload model

wire_load("45Kto75K") {

capacitance : 0.000070;

resistance : 0.000042;

area : 0.28;

slope : 40.258665;

fanout_length(1, 40.258865); fanout_length(2, 80.517750);

fanout_length(3, 120.776600);





}



Reading RTL

Synthesis tool reads the RTL files.

The synthesis tool checks forSyntax errorsEnters design into synopsys .db format

Command:

Synopsys: analyze format verilog lib work

./src/example.v


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Generic Tech Generation

Synopsys: elaborate example arch BEHAVIORAL lib work

Generates Control Data Flow Graphs (CDFGs)

Performs high level logic optimizations

Performs resource allocation AddersMultipliersProduces a table of the resources that are used

Generates a hierarchical netlistGeneric components (gtech.db) No timing or electrical properties in the designGenlib cells


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Design Error Checking

Check:Warnings and Errors in the log file

Examples of Warnings and Errors:Signals missing in sensitivity lists

Shorted inputs or outputsUnused & Undriven inputs and outputsBlackboxesDangling, undeclared and undriven wires

Unsynthesizeable or ignored HDL constructs (# delay, etc.)- Might need linting tool

Latches


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Constrain the Design

Constraints define the parameters of the block which the synthesistool must meet.Constraints define the relationships between the block and the restof the chip.

These items are defined:

Clocks Arrival timesLoading on the output pinsDrive resistance on the input pinsTiming exceptionsOperating ConditionsWireload model mode


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Constraints: Commands

Clocks

Input Delay

Output Delay

Output Load

Input DriveResistance

False Paths

Multicycle Paths

OperatingConditions

Wireload Model

Synopsys

create_clock

set_input_delay

set_output_delay

set_load

set_driving_cell

set_false_path

set_multicycle_path

set_operating_conditions

set_wire_load


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Constraints: set performance targets

Synthesized design:Bounded by constraintsInput/Output, clk; all bound design

The RTL defines the functionality of design

The library contains the building blocks for building the designThe constraints tell the synthesis tool the timing and electricalrelationships between the block and the chip


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Optimization

Optimization:

The generic netlistMapped to the cells in the tech library aTiming is computed (with a clocked design)

Iteratively

Tools restructures design until timing is metTargets:

Power AreaTiming (cycle time)

Note: See Lecture 5 for more details

Command:

Synopsys : compile


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Timing Reports

Timing reports: Are created in synopsys scriptGenerate longest pathsTiming: set-up/hold-time violations

Timing not met:Reconstrain designError in netlistToo long (depth) logic path


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Other Reports

Log file output:Command window shows errors per excuted command (gui)Log file (dc_shell) shows execution trace

Area Report

Just make sure design is not too largeDont try to overoptimize in DC

Hierarchy Report

Library Report

State Machine (FSM) report


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Final Netlist Generation

Synopsys :

Write verilog netlist

write format verilog hierarchy outputexample.mapped.sv

Write synopsys database file

write hierarchy output example.mapped.db


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Compilation Strategies

Top-Down Compilation Strategy

Method: Constraints are applied at the top level and the entire chipis synthesized.

Time-Budgeting Compilation Strategy (Bottom-Up Approach)

Method: Constrain and synthesize each sub-block. Then importresults and synthesize top level.

Compile-Characterize-Write Script-Recompile Strategy (CCWSR)

Method: Apply timing constraints to top level. Let tool propagatetiming constraints to lower level blocks (i.e. let the tool do a timing

budget). Have tool generate a constraint script on the characterizedsub-blocks. Synthesize sub-blocks then synthesize top level block.


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Top-Down Compilation Strategy

Advantages Only top level constraints are needed. Better results are achieved because optimization is performed

across the entire design.

Disadvantages Long compile times A small change in the design requires that the entire design be

re-synthesized If the design contains multiple clocks or generated clocks the

tool doesnt perform as well


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Time-Budgeting Compilation Strategy

Advantages Easier to manage because each sub- block has its own

constraint and synthesis scripts. A change in a sub-block does not necessary require that

other sub-blocks be resynthesized. Multiple and generated clocks are more easily handled.

Disadvantages Each block is individually synthesized May not produce optimal design. Prone to error due to

manually specified time budgets.

Very tedious and time-consuming to update and maintainmultiple scripts. Some critical paths dont become apparent until top level

compile is performed. (unobservability of critical paths) A final incremental compile of entire design may be necessary

in order to remove DRC errors.


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The Automated Chip Synthesis Approach Advantages

Less CPU memory is needed to do synthesis Automated Chip Synthesis (ACS) can create subblock

constraint budgets based on the top-level constraintsbecause budgeting is an integrated part of the ACS flow. Itcan see across the hierarchy like the top-down methodology.

Individual scripts are created for each sub-block

Disadvantages Tool generated constraint scripts are not very readable A change in a lower level sub-block requires that the entire

design be re-synthesized

May be difficult to achieve convergence between sub-blocksbecause of a Ping -Pong effect while synthesizing sub -blocks.

Synopsys ACS White Paper


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Synthesizeable Verilog Constructs

(For Verilog 1997)always endcase module repeat

and endmodule nand supply0

assign endfunction negedge supply1

begin endtask task

buf for nor tri

bufif0 function not wait

bufif1 if notif0 wand

case inout notif1 while

casex input or wire

casez integer output wordefault large parameter xnor

else macromodule posedge xor

end medium reg

sometimes


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Ignored Keywords

scalared, vectored small, large, medium

specify

time (some tools treat these as integers)

weak1, weak0, highz0, highz1, pull0, pull1

$keyword (some tools use these to set synthesis

constraints) wait (some tools support wait with a bounded condition)


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Unsupported Constructs

= = =, != =

cmos, nmos, rcmos,rnmos, pmos, rpmos

deassign

defparam

event

force

fork, join forever, while initial pullup, pulldown release repeat rtran, tran, tranif0, tranif1, rtranif0, rtranif1 table, endtable, primitive, endprimitive


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Common Synthesis Problems

LatchesUnassagined statements

Setup Time Violations/ Hold Time ViolationsRTL, flip-flop designs

Multiple Clock domains correctly

Poor ConstraintsWhat are the specifications?

Inaccuracy of Wireload modelsOnly real #s through place and route

Slow run-timesFlat design

Achieving Timing ClosureMany problems: constraints, RTL design, library, routing


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Timing Closure

Timing problem:Cant reach closure to rapidly achieve timing closure on a design is a HUGEPROBLEM for semiconductor industry

A timing closure problem exists when all timingviolations in a design cannot be eliminated despitemultiple synthesis and place & route iterationsThe timing closure problem occurs for a few reasons Poor design practices Inaccurate wireload models No placement information used during synthesis; therefore

inaccurate connection delays

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