Real-time Simulation Of The Buck Converter · Chapter 1 Introduction This report concentrates on enumerating the steps involved in implementing a buck con-verter (considering non-idealities)

Real-time Simulation Of TheBuck Converter

By

Janamejaya Channegowda

Power Electronics Group

Department of Electrical Engineering

Indian Institute of Science

Bangalore - 560 012

India

February 2014

Chapter 1

Introduction

This report concentrates on enumerating the steps involved in implementing a buck con-verter (considering non-idealities) on an FPGA platform. The focal point during theentire flow of the report will be on the conversion of differential equations of the buckconverter to discrete equations and their final implementation in real-time. The builtblock diagram files and experimental results have also been added.

1

Chapter 2

Switching Model

Nomenclature

• Vg = Input voltage

• Vf = Forward voltage drop of the diode

• Vc = Voltage across capacitor

• Vl = Voltage across inductor

• Vsw = Voltage drop across switch

• il = Current through inductor

• io = Current through load

• ic = Current through capacitor

• id = Current through the diode

• Rl = Resistance of inductor

• Rc = ESR of capacitor

• Ro = Load resistance

• Ts = Time step for simulating the models = 2µs

• Vb = Base voltage = 100 V

• ib = Base current = 4 A

• Zb = Base impedance = 25Ω

2

Development of Off-line and Real-Time Simulator for Electric vehicle /Hybrid Electric Vehicle Systems

+

−

Figure 2.1: Circuit of the buck converter being considered

+

−

Figure 2.2: Circuit of the buck converter with switch and diodes being replced by voltagesources

+

−

Figure 2.3: Circuit of the buck converter when switch is ON

2.1 Switch is ON

When Switch ”S” is ON, voltage across inductor is given by:

04/02/2014 Department of Electrical Engg, IISc, Bangalore Page 3


L · dildt

= Vg − Vsw − ilRl − Vo (2.1)

The Current through the capacitor is given by:

C · dvcdt

= il − io (2.2)

2.2 Switch is OFF

+

−

Figure 2.4: Circuit of the buck converter when switch is OFF

When Switch ”S” is OFF, voltage across inductor is given by:

L · dildt

= −Vf − ilRl − Vo (2.3)

The Current through the capacitor is given by:

C · dvcdt

= il − io (2.4)

2.3 Discrete equations obtained when switch is ON

2.3.1 Inductor current

Vl = Vg − Vsw − ilRl − Vo (2.5)

L · dildt

= Vg − Vsw − ilRl − Vo (2.6)

L · dildt

= Vg − Vsw − ilRl − (icRc + Vc) (2.7)



ic = il − io (2.8)

ic = il −VoR

(2.9)

ic = il −icRc + Vc

R(2.10)

ic + ic ·Rc

R= il −

VcR

(2.11)

ic =R

R +Rc

·(il −

VcR

)(2.12)

Substituting this in the Vl expression we get :

Vl = Vg − Vsw − ilRl −[(

R

R +Rc

)·(il −

VcR

)·Rc + Vc

](2.13)

Converting the equations into dicrete quantities:

il(k + 1)− il(k)

Ts=VgL− Vsw

L− ilRl

L−[(

R

R +Rc

)·(il −

Vc(k)

R

)· Rc

L+Vc(k)

L

](2.14)

Divide throughout by Ibase (ib) and Vbase (vb) to per-unitize the current and voltagerespectively:

ilpu(k + 1)− ilpu(k) =

Ts·Vgpu·Vb

L·ib− Ts·Vswpu·Vb

L·ib− Ts·ilpu(k)·Rl

L−[(

RR+Rc

)(ilpu(k)− Vcpu(k)·Vb

ibR

)TsLRc

+ Vcpu(k)·Vb

ib·L

]Finally:

ilpu(k+1)−ilpu(k) = a·Vgpu−a·Vswpu−a·ilpuRlpu−[(ilpu(k)− Vcpu(k)

Rpu

)· b+ Vcpu(k) · a

](2.15)

Where, a =TsLZb

=2µs2mH25Ω

= (409)d = (199)h (2.16)

and, b =TsLRl

=2µs2mH2Ω

= (32)d = (20)h (2.17)



2.3.2 Capacitor voltage

From previous equations we have:

ic =

[R

R +Rc

] [il −

VcR

](2.18)

Converting the equations into discrete form and per-unitizing them by dividing through-out by Ibase (ib) and Vbase (vb) we get:

Cdvcdt

=

[R

R +Rc

] [il −

VcR

](2.19)

vc(k + 1)− vc(k)

Ts=

[R

RC + CRc

] [il −

VcR

](2.20)

vcpu(k + 1)− vcpu(k) =

[Ts

RC + CRc

] [R · ilpu(k) · ib

vb− Vcpu

](2.21)

Neglecting the term CRc we get:


[TsRC

][Rpuilpu(k)− Vcpu(k)] (2.22)

vcpu(k + 1)− vcpu(k) =Ts

RZbZbC

[Rpuilpu(k)− Vcpu(k)] (2.23)

Finally we get:

vcpu(k + 1)− vcpu(k) =TsZbC

[ilpu(k)− Vcpu(k)

Rpu

](2.24)

here:

xc =TsZbC

= (131)d = (83)h (2.25)

2.4 Discrete equations obtained when switch is OFF

2.4.1 Inductor Current

We have:



Vl = −Vf − ilRl − Vo

L · dildt

= −Vf − ilRl − [icRc + Vc]

we have ic = il − io

ic = il −VoR

ic = il −[icRc + Vc

R

]ic =

[R

R +Rc

] [il −

VcR

]Substituting the above value of ic in Vl we get :

Vl = −Vf − ilRl −[(

R

R +Rc

)·(il −

VcR

)·Rc + Vc

]Converting the equations into discrete form and per-unitizing them by dividing through-

out by Ibase (ib) and Vbase (vb) we get:

L

[il(k + 1)− il(k)

Ts

]= −Vf − ilRl −

[(R

R +Rc

)·(il(k)− Vc(k)

R

)·Rc + Vc

]il(k + 1)− il(k) = −Ts

LVf − il(k)Rl

TsL−[(

TsL

)(RRc

R +Rc

)(il(k)− Vc(k)

R

)]− Vc(k)

TsL

Noting that RRc

R+Rcratio is always 0.59, for example 100·0.6

100+0.6, we take it’s inverse (1.67)

in all the calculations of constants.

ilpu(k + 1)− ilpu(k) = −TsLVfpu

Vbib− ilpu(k)

TsLRl

−

[(TsL

1.67

)(ilpu(k)− Vcpu(k)Vb

ibR

)]− TsVcpu(k)Vb

Lib

ilpu(k + 1)− ilpu(k) = −TsLZb

Vfpu − ilpu(k)TsLRl

−

[(TsL

1.67

)(ilpu(k)− Vcpu(k)

RZb

)]− Vcpu(k)

TsLZb

Finally:

ilpu(k + 1)− ilpu(k) = −AVfpu −Bilpu(k)−[Cilpu(k)− CVcpu(k)R−1

pu

]−AVcpu(k) (2.26)

Where:

A =TsLZb

=2µ2m25Ω

= (409)d = (199)h (2.27)



B =TsLRl

=2µ2m2Ω

= (32)d = (20)h (2.28)

C =TsL

1.67

=2µ2m1.67

= (27)d = (1B)h (2.29)

2.4.2 Capacitor Voltage

From previous equations we have:

ic =

[R

R +Rc

] [il −

VcR

](2.30)

Converting the equations into discrete form and per-unitizing them by dividing through-out by Ibase (ib) and Vbase (vb) we get:

Cdvcdt

=

[R

R +Rc

] [il −

VcR

](2.31)

vc(k + 1)− vc(k)

Ts=

[R

RC + CRc

] [il −

VcR

](2.32)


[Ts

RC + CRc

] [R · ilpu(k) · ib

vb− Vcpu

](2.33)

Neglecting the term CRc we get:


[TsRC

][Rpuilpu(k)− Vcpu(k)] (2.34)

vcpu(k + 1)− vcpu(k) =Ts

RZbZbC

[Rpuilpu(k)− Vcpu(k)] (2.35)

Finally we get:

vcpu(k + 1)− vcpu(k) =TsZbC

[ilpu(k)− Vcpu(k)

Rpu

](2.36)

here:

xc =TsZbC

= (131)d = (83)h (2.37)

2.5 Block diagram implementation of switching model



Fig

ure

2.5:

Con

stan

tsuse

din

the

blo

ckdia

gram



Fig

ure

2.6:

DA

Cin

terf

ace

par

tI



Fig

ure

2.7:

DA

Cin

terf

ace

par

tII



Fig

ure

2.8:

DA

Cin

terf

ace

par

tII

I



Fig

ure

2.9:

The

induct

orcu

rren

tis

pre

vente

dfr

omb

ecom

ing

neg

ativ

e



Fig

ure

2.10

:T

he

enab

lesi

gnal

sar

ege

ner

ated

ata

freq

uen

cyof

500k

Hz



Fig

ure

2.11

:T

he

freq

uen

cyb

eing

gener

ated

at50

kH

z



Fig

ure

2.12

:C

alcu

lati

onof

induct

orcu

rren

tpar

tI



Fig

ure

2.13

:C

alcu

lati

onof

induct

orcu

rren

tpar

tII



Fig

ure

2.14

:B

lock

sin

volv

edin

inte

grat

ion

ofin

duct

orcu

rren

tan

dca

pac

itor

volt

age



Fig

ure

2.15

:B

lock

show

ing

the

sele

ctio

nof

on/o

ffin

stan

ces

ofth

ein

duct

orcu

rren

tb

eing

sele

cted

bas

edon

swit

chin

gfr

equen

cy



Fig

ure

2.16

:B

lock

show

ing

the

calc

ula

tion

ofin

duct

orcu

rren

tduri

ng

the

offp

erio

d



Fig

ure

2.17

:B

lock

show

ing

the

calc

ula

tion

ofou

tput

volt

age

duri

ng

on/o

ffp

erio

dof

the

swit

ch


Chapter 3

Average Model

The various formulae for calculating inductor current and output voltage during CCMand DCM are given below:

Continuous conduction mode

Vo = VinD

[1− Vf (1−D)

DVg

] [R

Rl +R

](3.1)

Il =VoR

(3.2)

Discontinuous conduction mode

Vo =DVg

D +D2

[1− VfD2

DVg

](3.3)

Il =VoR

(3.4)

K =2L

RTswhere Ts = Switching frequency (3.5)

Kcri = 1−D (3.6)

and finally:

D2 =−D +

√D2 + 4K

2(3.7)

22


3.1 Block diagram implementation of average model



Fig

ure

3.1:

The

const

ants

invo

lved

inth

eblo

ckdia

gram



Fig

ure

3.2:

Cal

cula

tion

ofD

2par

tI



Fig

ure

3.3:

Cal

cula

tion

ofD

2par

tII



Fig

ure

3.4:

Clo

cks

that

are

use

din

the

DA

Cin

terf

ace

par

tI



Fig

ure

3.5:

DA

Cin

terf

ace

par

tII



Fig

ure

3.6:

Gen

erat

ion

ofen

able

puls

esat

500k

Hz



Fig

ure

3.7:

Sel

ecti

onof

induto

rcu

rren

tin

CC

M



Fig

ure

3.8:

Sel

ecti

onof

induto

rcu

rren

tin

DC

M



Fig

ure

3.9:

Cal

cula

tion

ofK



Fig

ure

3.10

:C

alcu

lati

onof

outp

ut

volt

age



Fig

ure

3.11

:C

alcu

lati

onof

outp

ut

volt

age

duri

ng

DC

M


Chapter 4

Real-time simulation results

Switching Model

Figure 4.1: The start-up transient of the inductor current of the switching model

35


Figure 4.2: The transient of the inductor current of the switching model when load changesfrom 1000 ohm to 100 ohm

Figure 4.3: The transient of the inductor current of the switching model when duty ratiochanges from 0.2 to 0.5



Figure 4.4: The transient of the inductor current of the switching model when inputvoltage changes from 40 V to 60 V

Figure 4.5: The start-up transient of the output voltage of the switching model



Figure 4.6: The transient of the output voltage of the switching model when load changesfrom 1000 ohm to 100 ohm

Figure 4.7: The transient of the output voltage of the switching model when load changesfrom 100 ohm to 1000 ohm



Figure 4.8: The transient of the output voltage of the switching model when duty ratiochanges from 0.2 to 0.5

Figure 4.9: The transient of the output voltage of the switching model when input voltagechanges from 40 V to 60 V



Average Model

Figure 4.10: The start-up transient of the inductor current of the average model

Figure 4.11: The transient of the inductor current of the average model when load changesfrom 1000 ohm to 100 ohm



Figure 4.12: The transient of the inductor current of the average model when duty ratiochanges from 0.2 to 0.5

Figure 4.13: The transient of the inductor current of the average model when input voltagechanges from 40 V to 60 V



Figure 4.14: The start-up transient of the output voltage of the average model

Figure 4.15: The transient of the output voltage of the average model when load changesfrom 1000 ohm to 100 ohm



Figure 4.16: The transient of the output voltage of the average model when load changesfrom 100 ohm to 1000 ohm

Figure 4.17: The transient of the output voltage of the average model when duty ratiochanges from 0.2 to 0.5



Figure 4.18: The transient of the output voltage of the average model when input voltagechanges from 40 V to 60 V


References

[1] A VHDL Primer, 3rd Edition by Jayaram Bhasker

[2] Digital Electronics - A Practical Approach with VHDL, 9th Edition by William Kleitz

[3] FPGA board document by Venugopal.S

[4] FPGA DOCUMENT-2 by N. Praveen Kumar

[5] FPGA Board Document, Ver.1.3, Revision 2, February 20, 2007 by Parag AnandRajne, Jayalakshmi and Ravi Krishna

[6] Digital Systems Design with FPGA, course material by Kuruvilla Varghese

[7] Dynamic Performance of Switched Mode Power Converters in Simulation of powerelectronic circuits, course material by M.B.Patil, V.T.Ranganathan and V. Rama-narayanan. Narosa, New Delhi, 2009.

[8] Course material on Switched mode power conversion by V.Ramanarayanan.

[9] Fundamentals of power electronics by Robert.W.Erickson and Dragan Maksimovic.

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Documents

Real-time Simulation Of The Buck Converter · Chapter 1 Introduction This report concentrates on enumerating the steps involved in implementing a buck con-verter (considering non-idealities)