REAL TIME EMBEDDED SYSTEM_Lec5

8/7/2019 REAL TIME EMBEDDED SYSTEM_Lec5

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Real-time Embedded Systems

Lecture 5

Understanding targets-8086 based systems

Prof. Dr. Amitava Gupta

Department ofPower Engineering

Jadavpur University, India

Real-time Embedded Systems- Lecture 05


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Embedded System?

Application

Operating System

Hardware

+

What have we learnt?

Interface with application


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We start with a survey of 8086 based systems

AHBHCHDH

ALBLCLDL

SP

BP

SI

DI

IP

CS

SS

DS

ES

Instruction

queue

Control

Logic

ALU

PSW

20

16

Address

Data

Control


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Pipelined Architecture

The fetching and execution activities overlap. Instructions are

pre-fetched and kept in instructions queue.

While one instruction is being executed, the next one is fetched.

This is because of the fact that fetch and execution units are separate.

When processors have more than one execution unit, they are said to

have a superscalar architecture. The Pentium is an example of such

processors.


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Bus Organized Computers

A set of conductors used for communicating information between the components

of a computer is called a bus.

External bus- connects two major components e.g. CPU and memory.Thisis the system bus.

Internal bus- connects two minor components within a major component

e.g. set of working registers and the control unit.

Components which control the Bus are called bus masters, e.g. CPU,DMA

controller etc.


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System Bus Timing contd..

T1 T2 T3 Tw T4 T4 Ti Ti

Bus Cycle: Activity involved in transferring a byte or word over system bus

is called bus cycle. The execution of an instruction may require more

than one bus cycle.

The timing of signals within the CPU and bus control logic is controlled by

a clock. The bus cycles and CPU activity are controlled by groups of clock pulses.

The exact number of clock pulses or cycles within a bus cycle varies


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T1 T2 T3T4

Read timing for 8086 without wait states

Address out Data in

ALE

RD

Device sends a Ready signal here

else wait states are introduced between

T3 and T4

Tw


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Physical memory organization

o e+

D15-D8 D7-D0

512 KB each

Selectable by

bit A0

OA = EA + 1

So, for an even address

the next odd address can

be obtained by using

A0 = 1 keeping all other

bits same

Address

Address

+ 1


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Basic addressing scheme uses two 16 bit registers to

compute a 20 bit address

The memory is logically organized into segments

1M

64K

16 bit segment register

16 bit pointer register

offset

4 Bits

base


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Excercise

Ifthe physical address is 5A230 when [CS] = 5200,

what will it be [CS] becomes 7800?

Solution:


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Interrupts (Hardware Interrupts)

Each interrupt is associated with an Interrupt Service Routine (ISR) that is executed when an

interrupt occurs

Interrupt table

IP type 0CS type 0

00000

00002

00004


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Interfacing External Interrupts

CPU PIC

8259

INTR

T1 T2 T3T4

ALE

T4

INTA

AD7-AD0

INTA


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Establishing the type N

Pushing the contents of PSW, CS

and IP into the stack

Clearing the IF and TF flags

Loading content of 4*N into IPand 4*N + 2 into CS

Interrupt Sequence


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ICW 1(Chip Control)

ICW 2(Type)

ICW 3(Slave Control)

ICW 4(Mode Control)

OCW 1(IMR)

OCW 2

OCW 3

In Service Register Priority Resolver IRR & ML


0

7

0

1

I

0

1

INT0

Pending

INTA


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1 ADI SNGL LTIM IC 4

0 00 SFNM M/S AEOIBUF PM

ICW4- Mode Control

ICW1- Chip Control


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SL EOIR 0 L2 L10 L0

ESMM SMM0 0 P RR1 RIS

OCW2

OCW3


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Requests arrive simultaneously on IRQ2 and IRQ4,

& while IR2 routine is being executed, IRQ1 arrives!

Main

Program

IRQ2

IRQ4

D2 in ISR set

IR2

-----------Reset IF

(STI)

.

.

.

IRET

IRQ1

IR1

-----------

Reset IF

(STI)

.

..

IRET

D1 in ISR set

IR4

-----------

Reset IF

(STI)

.

.

.

IRET

D1 in ISR reset

D2 in ISR reset

D4 in ISR set

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