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RBSP
Rad
iati
on B
elt S
torm
Pro
bes
RBSP
Rad
iati
on B
elt S
torm
Pro
bes
13-4 Sept. 2008 EFW INST+SOC PDR 1
Data Controller BoardFPGA
Dorothy Gordon
UC Berkeley Space Sciences Lab
223-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA Introduction
• Data Controller Board FPGA– Block Diagrams– Basic Subsystems– Memories– Design/Verification Process– Schedule/Issues
333-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA DCB Block Diagram
BOOT ROM 32Kx8
Addr[14:0]Data[7:0]
CS_ROM
SDRAM
Includes SDRAM Power Switch256 MBy tes
Addr[12:0]Data[7:0]
Cntl/Decode
EEPROM128Kx8
Data[7:0]
CS_NVRAM
Addr[16:0]
SRAM128Kx8Addr[16:0]
Data[7:0]
CS_RAM
FLASH
Buf f er/Lev el Shif t 3.3V <> 5 V f or BEB and PCB Control
Includes F LASH Power Switches32 GBy tesIO[7:0]
Cntl/Decode
CDI Interface to DFB
UART Tlm to S/C
AnalogValues from
Instruments
UART Cmd from S/C
1PPS/Spinfrom S/C
M ux
ADC
Filter/Scale
ADCDAT[15:0]
Includes Level Translation(3.3V <> 5V)
Buf/T
Housekeeping
HSKPIN[15:0]
MADRSEL[3:0]
MTDAT[7:0]
ADCDATOE[1:0]
HADCCntl
RBSP-DCB FPGA
Power-OnReset 16.78 M Hz
Z80 Core
Timekeeping
S/C I/F
OSC
M emoryCont/Arb
DM A Cntl
FPGA/Processor Core
Ck1Hz_SPls
HW Reset
MDAT[7:0]
TlmCm d
MBUSCNTL
MADR[16:0]
HADRSEL[2:0]
CDI_I/F
InstCntl
SSRInterface
DRInterface
InstData
HADCCntl
443-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA FPGA Block Diagram
Timekeeper
DFB Interface
CZ80CPU
MBUS Control
Registers/IO Bank
SDRAM Control
Debug UAR Ts
FLASH Control
CPU BUS Control
CPUADR/C TL
RSTHWRST
INT
INT
NM I
CPUDAT
M BUSD AT
MBUSADR/CT L
SELS(P,S,E,A)
CPUL INADDRCPUM EMRQ/ CTL
FLASHCPUCT L
F LASHDATF LASHCT L
F LASHPWRCPUI FCT L
CPUIFCT L
TL MIF CTLCM DIFC TL
DUART DOUTDUARTDIN
DF BT LM [1:0 ]
DI AG IO
WDENB
SPCK_1 PPS
ADCCT L
BEBCTL
T IMCO UNT
CLK/CMD /1HZ
PCBCTL
SDRAM PWR
DFBADR
DFBDAT
DFBDM ACT L
DFBIF CTL
DFBIF CTL
FL ASHDATFL ASHADR
F LASHCPUCTL
F LASHDMACT L
F LASHDMACT L
F LASHDMACT L
Telemetry Ctl/UART
T LM IFCT L SCT LM
Command Ctl/UART
CM DIFC TL
SCCMD
TL MDATTL MADR
T LMDM ACTL
CMDDATCM DADRCMDDM AC TL
CPUIOCT L
DBG UART -DAT /CT L/STAT
REGSDAT
SDRAMCT L
SDRAMDAT
TIM /INT STAT
T IM /INT ST AT TIM CT L
TI MCT L
SPINT IMSC1PPSTI M
SPI NTIMSC1PPSTIM
FDM AST AT
F DMAST AT
SDMASTAT
SDM AST AT
M DMASTAT `
MDM AST AT
CLK16. 78MRSTTIM COUNT
G lobal
Overall Block DiagramDCB FPGA15 August 2008
DF BIFSTAT
D FBIF STAT
TLMIFSTAT
TLMIFSTAT
CMDIFSTAT
CMDIF STAT
CPUIF STAT
553-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGABasic Subsystems (1)
• Relevant Documentation– Data Controller Board FPGA Specification (RBSP_EFW_DCB_001F_Specification.pdf)
– Z80 Core Specification (RBSP_EFW_DCB_002_CZ80_Spec.pdf)
– Data Controller Board Specification (RBSP_EFW_DCB_003C_Specification.pdf)
– Backplane Specification (RBSP_EFW_BPL_001G_Specification.pdf)
– ICD for the EFW Investigation (APL 7417-9083, Rev c)
• Basic Subsystems
– CPU Core and Support Circuitry• Z80 – Processor running at 16.78MHz
– CPU starts up from ROM, copies data to SRAM; steady state operation from SRAM
– Patching capability via EEPROM
• Memory Bus– MBUS houses SRAM, EEPROM, PROM
– Paged memory map expands CPU addressing capability to 512Mbytes (229)
– SRAM shared by CPU and DMA Clients
6
EFW – Data Controller Board FPGABasic Subsystems (2)
– Spacecraft Interface• Glitch filter applied to all inputs (pulses 200 nanoseconds or less rejected)• 1PPS/SPINPULSE detection via pulse width• Command Reception (115Kbaud UART)
– Packetized data transferred to SRAM via DMA
– Up to 4Kbytes/second allocation
– Parity as per APL ICD (parity and framing errors flagged)
• Telemetry Transmission (115Kbaud UART)– CPU generates CCSDS packets
– Telemetry subsystem generates Instrument Transfer Frame (ITF) Wrapper
– ITFs are transferred from SRAM or SDRAM via DMA
– Parity as per APL ICD
– Timekeeping• Internal 24 bit counter provides instrument timebase
• Timestamps Spin Pulse and 1PPS
• Generates CPU Interrupts and Watchdog Timer Reset
• Provides Instrument DMA Buffer Swap “ticks”
63-4 Sept. 2008 EFW INST+SOC PDR
7
EFW – Data Controller Board FPGABasic Subsystems (3)
– BEB, PCB Interfaces• Synchronous serial data interfaces operate at 1MHz
• CPU writes commands via I/O Interface; Logic handles serial protocol
• Management of DACs & Controls (relays, analog mux addresses, etc.)
• AC Test Stimulus Generation for BEB
– DFB Interface - Mode Setup and Data Ingest• Data transfer at 8.4MHz – 24 bit data/parity checked
• Command Interface – CPU writes as I/O; Logic handles serial protocol
• Instrument data received/transferred via DMA
– Bulk Volatile Storage (Dynamic RAM) Management• R/W and DMA access for a 256Mbyte SDRAM array
• Upper quadrant is devoted to ECC
– Bulk Non-volatile Storage (FLASH) Management• DMA access for a 32Gbyte FLASH array
• CPU or DMA accessible
• DMA mode incorporates ECC implemented over 512byte blocks
73-4 Sept. 2008 EFW INST+SOC PDR
8
EFW – Data Controller Board FPGA Memory Paths
83-4 Sept. 2008 EFW INST+SOC PDR
SDRAM256MB
INST-DFB
FLASH
SRAM128KB
INST-DFB
FLASH
CPU
SC-TLM
SC-CMD
CPU
SC-TLM
SCRUBBER
FLASH32GB
CPU
ECC-MNGR
9
EFW – Data Controller Board FPGA Memories - SRAM
• MBUS Bus Dynamics– CPU allocated bus as highest priority device
• Clients obtain bus between processor r/w cycles, wait states added as necessary
– SRAM DMA Loading:• S/C Commands: 0.35% peak loading at 115200 bps
– Average loading (depends on command volume): ~0.1% at 4Kbytes/sec
• S/C Telemetry: normally this transfer is from SDRAM
– SRAM option included as a failure mode
– Peak loading is 0.35%, average (based on 12kbps) is less (< 0.1%)
• DFB DMA: normally this transfer is to SDRAM
– SRAM option included for housekeeping APID option, or as a failure mode
– Housekeeping packet into SRAM -> <0.1% loading
– Peak loading at maximum DFB transfer rate is 32%
• FLASH DMA: normally this transfer is to/from SDRAM
– SRAM option included as failure mode
– Transfer rate throttling option to limit loading to < 5%
93-4 Sept. 2008 EFW INST+SOC PDR
10
EFW – Data Controller Board FPGA Memories – SDRAM
• SDRAM Memory– Heritage design (Themis Data controller board)
• During the ~1.5 years of operation, we have seen transient bit flips (ECC very effective in this respect) and one stuck bit (corrected with a power cycle); but otherwise no major problems
– Consists of a stacked memory module (3D-Plus MMSD08256804S-C-1S)• 256M x 8 configuration
• Uses four ELPIDA 64Mbyte die
– Array is isolated -- switchable power• Defaults to off at power on
– Mode set every second • Minimizes impact of Single Event Functional Interrupts (SEFI)
– Error correction option• Correction applied to 32 bit words, scrubbing occurs continuously when enabled
– DMA clients include: DFB, S/C Telemetry, FLASH – CPU can read/write (with wait states) as a random access device
• Used for insertion of CCSDS packet headers
103-4 Sept. 2008 EFW INST+SOC PDR
11
EFW – Data Controller Board FPGA Memories – FLASH
• FLASH Memory– Consists of eight stacked memory modules (3D-Plus MMFN08408808S-F-1S)
• Each module is 2G x 8, using eight MICRON 256M x 8 FLASH components
– Each 3D-Plus FLASH Module is independently isolated -- switchable power• Defaults to off at power on; turns off with watchdog reset
• Devices are kept off during periods of inactivity– Optimize TID lifetime and minimize power drain
– Reset command issued once/second • Minimizes impact of Single Event Functional Interrupts (SEFI)
– Error correction option – Hamming code• Correction applied to 512 byte segments for DMA writes
• Error detection/correction during readout
• No continuous scrubbing (unlike the SDRAM)
– DMA mode: transfers data to/from SDRAM and/or SRAM– CPU sets up DMA; handles buffer allocation and bad block management– Processor mode: CPU can read/write as a device in memory mapped mode
• Allows for diagnostic backdoor
113-4 Sept. 2008 EFW INST+SOC PDR
12123-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA Design/Verification Process (1)
• FPGA Status/Utilization– Estimated module utilization: 50%
• Potential use of spare modules for diagnostic amenities
– Estimated I/O utilization: 70%• Spare pins can be allocated to diagnostic functions
– Timing margin: target FPGA can handle the 16.78MHz System Clock• Themis FPGA, an older generation, no problems at 20MHz
• FPGA Design/Verification Process– Process described in FPGA Development/Verification Plan
• RBSP_EFW_PA_006A_FPGA_Verification_Plan.doc
– Prototype boards use FLASH part (Actel A3P1000) - reprogrammable– Migration to fuse based flight part (Actel RTAX2000SL) – Coded in VHDL, testbenches/simulation at module as well as top-level– Top level simulations use the processor, running Z80 coded diagnostic programs – Static timing analysis
13133-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA Design/Verification Process (2)
• IP Core– Purchased from CAST, Inc.
• Delivering IP cores since 1996• Offering over 550 core licenses to approximately 400 customers (including
commercial, military as well as NASA based projects)– Core is delivered as routed netlist for the target FPGA– VHDL Model used for functional simulation– Routed version reverified during top-level simulation
• Testing/Debug Environment (using the DCB Protoboard)– ROM Monitor successfully ported from Themis DCB
• Ability to download and run diagnostic programs
– The following FPGA modules have been tested/verified– CPU CORE and CPUBUS control– MBUS control– UARTS (both S/C and diagnostic ports)– SDRAM Controller– Timekeeper (1PPS and Spin Clock reception logic verified with S/C Emulator)
14143-4 Sept. 2008 EFW INST+SOC PDR
EFW – Data Controller Board FPGA Schedule/Issues
• Status– Detailed design about 50% complete
• CPU Core has been exercised extensively– Detailed design completion (supporting DCB Protoboard) expected by the
end of 2008– Ongoing activities during DCB Protoboard and ETU Test/Verification
• Migration to engineering/flight DCB using FLASH FPGA• Support flight software development• Instrument Integration (verify DFB, BEB and PCB Interfaces)• Spacecraft Integration (verify Command and Telemetry Interfaces)• Retarget VHDL for flight part; simulate, test and verify
• Issues– ICD (Spacecraft Interface) – designing to the “working copy”
• No problems with current interface definitions
