Rasit Onur Topaloglu [email protected] University of California at San Diego Computer Science and Engineering Department La Jolla, CA, 92093, USA Mismatch

Rasit Onur Topaloglu [email protected] University of California at San Diego Computer Science and Engineering Department

La Jolla, CA, 92093, USA

Mismatch Modeling of MOS Transistors for Deep Sub-micron

Technologies

Outline

-Mismatch at transistor, circuit and VLSI levels-Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch-Past and Present Mismatch Modeling Approaches:

-Electrical & Empirical Models-Layout-based Models-BSIM-based Models-Physics-based Models

-Insights for Future Models for Mismatch-Summary & Conclusions

silicon

silicon dioxidesilicon •Wafer is oxidized

silicon dioxidesilicon

photoresist

•Wafer is covered with photoresist


photoresistphotomask

•A photomask is placed on wafer

Semiconductor Manufacturing Steps

•Wafer is created

Semiconductor Manufacturing Steps


photoresistphotomask

UV radiation

•Wafer is exposed to ultra-violet (UV) radiation


photoresist •Unexposed regions dissolved


photoresist•Unprotected oxide etched


•Photoresist removed. Wafer is ready for doping

Possible Causes of Mismatch


doping

•Wafer is doped

silicon dioxidedoped regions •Doping creates n or p-type wells

•These variations can depend on the process (PVE), or they can be random effects (RE) •Mismatch negatively influences the design, which assumes accurate matching of electrical parameters between matched transistors

•Mismatch is caused by variations in the processing stagesex. photomask misalignment, difference in doping gradients, etc.

Transistor Operation and Mismatch

VGS

VG

VDD

ID

VDS

GD

S

GND

VG

Increasing VGS

ID

VDS

Vth=threshold voltage

D=drain

G=gate

S=source

V=voltage

I=current

L=channel length

W=channel width

n=channel mobility

Cox=oxide capacitance

Mismatch = variation in drain current of matched transistors

21

2D n ox GS th

WI C V V

L

Drain current formula:

Schematic view of transistor

G

DS

VG VDDGND

ID

L

Physical view

Vth

ID

VGS

quadraticincrease

Impact of Mismatch on a Circuit

Vi1

•Proper circuit operation requires precision matching of certain transistors

M1 M2

Vi2

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

Mismatch = variation in drain current of matched transistors

M=transistori=inputG=gain

•Mismatch most important in analog circuits•Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters

VOUT


W1=300mW2=300m

W=width

•Proper circuit operation requires precision matching of certain transistors A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

Mismatch = variation in drain current of matched transistors•Mismatch most important in analog circuits•Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters

Vi1

Vi2

VOUT


Vth1=0.7V

•Proper circuit operation requires precision matching for certain transistors

Vth2=0.7V

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

Vth=threshold

voltageG=gain


Vi1

Vi2

VOUT


Id1=1mAId2=1mA

Id=drain current

•Proper circuit operation requires precision matching for certain transistors A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)


Vi1

Vi2

VOUT

Process Variations and Mismatch

Iref

300 300

300+2+1300+2+-2

300 303

W1 W2 GNominal :300 300 100PVE+RE causing mismatch:303 303 102297 297 98PVE+RE not causing mismatch:303 300 99297 300 90

PVE RE PVE RE

W1when W2=300

G G

W1when W2=W1

•PVE and RE’s add up; they may or may not create a mismatch that effects circuit operation according to specifications

•Mismatch deteriorates circuit performance, in the limit, causes the circuit to escape optimal operating region

PVE=process variation effectsRE=random effects

Vi1

Vi2

VOUT

Impact of Mismatch on VLSI Design

Mismatch causes soft errors (reduction in gain, higher output R)

-Yield loss

-Increased time to market

•We need to design for mismatch

•We need to estimate effects of mismatch : both require models

Critical mismatch necessitates re-design

-Optimization of circuit without accurate consideration of mismatch is barely lost time

Mismatch effects are not easily predictable

Why Mismatch Models Necessary for Analog Design Flow?

Manual design

SPICE simulations

Select architecture and technology

Optimizations

Test & diagnosis after production

Behavioral level design and simulations

Costly redesign needed due to late observation of mismatch effects

SPICE simulations

Optimizations

Manual design

SPICE simulations


Optimizations



Essential to help model mismatch as soon as possible so as to accomplish heavy reduction in number of iterations

Costly redesign needed due to late observation of mismatch effects

Manual design

Why Mismatch Models Necessary for Analog Design Flow?

Outline




Model Requirements for each Step of the Design Flow

Manual design


SPICE simulations


Optimizations


Manually applicable models

Accurate models for simulation

Mismatch Predictive models

Models for Test and diagnosis

Worst-Case Estimations Fail in Deep Sub-Micron

Iref

Current mirror

•Worst-case propagation between blocks results in overestimation of errors

•Designing while considering such large variations impossible in DSM

•Correlations between parameters accentuate this error

Bandgap reference circuit

Iref

Vb1

Vb2

Vb3

OpAmp

99 % falls in this range

actual pdf

New models should avoid worst-case estimations

Worst-case limits for an output parameter

RE

Fabrication accuracy cannot keep up with feature size shrinkage rate, as: •Errors occurring from diffusion cause PV distributions that have similar across different technologies

Wafer radius

tox (x40nm)

Wafer radius

tox (x4nm) newer technology

The Increasing Importance of Random Effects

•Mismatch groups closer than ever before, therefore: REs assume increased importance compared to previous technology

PVE

New models should be able to consider random effects

Outline




Layout Optimizations

A B

standard layout style

•Layout optimizations try to disperse the effects of on-chip gradients between matched transistors A and B equally

•Statistical average of a parameter would differ a lot on matched transistors without optimizations causing significant mismatch

Common centroid layout style

A B B A

iso-parameter contours for a physical parameter such as tox

tox=4.0nm

tox=4.1nm

tox=4.2nm

tox=4.0nmtox=4.1nm

tox=4.2nm

tox=oxide thickness

-Connecting gates, or avoiding from deteriorating effects of other blocks on layout may be problematic

+Sufficient for minimal to moderate matching-Suffers linear optimization limitations as transistors rectangular, yet physical parameter distributions have curves

Common centroid layout style

Criticism of Layout Optimization

A B B A

-Not quite suitable for matching ratios other than unity

iso-parameter contours for a physical parameter such as tox

tox=4.0nmtox=4.1nm

tox=4.2nm

Circuit Optimizations

The

rmom

eter

Enc

oder

I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995

.

.x[n]

.

. y[n]

x1[n]

b

x2b[n]

y1[n]

y2[n]

y2b [n]

1-BitDAC1-BitDAC

1-BitDAC

A Digital-to-Analog Converter (DAC)

x[n]

y[n]

frequency

PSD

PSD=power spectral densityDAC=digital to analog converter

•The circuit implements an ideal staircase transfer function between input and output

•Mismatch within DAC’s cause a related performance parameter, PSD, to fail specifications


The

rmom

eter

Enc

oder


Scra

mbl

er..

x[n]..

.

. y[n]

x1[n]

b

x2b[n]

y1[n]

y2[n]

y2b [n]

1-BitDAC1-BitDAC

1-BitDAC

•Scrambler randomly selects 1-Bit DACs to be used in computation

A Low Harmonic DAC

frequency

PSD


The

rmom

eter

Enc

oder


Scra

mbl

er

.

.x[n]..

.

. y[n]

x1[n]

b

x2b[n]

y1[n]

y2[n]

y2b [n]

1-BitDAC1-BitDAC

1-BitDAC

•Scrambler randomly selects 1-Bit DACs to be used in computation

•Mismatch in 1-Bit DAC blocks averaged, compensating deteriorating effects of mismatch on distortion

A Low Harmonic DAC

frequency

PSD

-Architecture specific, hence requires design time

+May be the best way to optimize for a single parameter

-It is usually necessary to optimize a circuit for more than one parameter

Criticism of Circuit Optimizations

The

rmom

eter

Enc

oder

Scra

mbl

er

.

.x[n]..

.

. y[n]

x1[n]

b

x2b[n]

y1[n]

y2[n]

y2b [n]

1-BitDAC1-BitDAC

1-BitDAC

A Low Harmonic DAC

Outline




Electrical / Empirical Parameter-based Mismatch Modeling

•Classical ad-hoc approach by designers

•Threshold voltage mismatch is the most common model

•Worst-case conditions algebraically calculated for parameters

2211 RIRI DD

Derivation of Vos starts with equating drain voltages:

21

2D n ox GS th

WI C V V

L

Drain current formula:

B. Razavi, “Analog CMOS Integrated Circuits,” McGraw-Hill, 2000

Ex:Mismatch modeled at input as common-mode offset voltage for a differential pair

Vos

Iref

VGS1 VGS2

ID1 ID2

+

-

+

-

R1 R2Vos=offset voltage

R=resistance

Differential stage

Derivation of Optimization Equations

21 GSGSos VVV

Vth

LW

LW

R

R

LW

C

IV

D

D

oxn

Dos

/

/2

2

1

•Terms with come from first order Taylor series expansion

Derive Vos to compensate for mismatch:

+

Iref

Vos

VGS1 VGS2

ID1 ID2

+

- -

R1 R2

•Assumption: Independence between parameters

•By adding Vos, mismatch caused degeneration of some parameters like CMRR avoided

CMRR=common mode reject ratio

C. J. Abel, C. Michael, M. Ismail, C.S. Teng and R. Lahri, “Characterization of Transistor Mismatch for Statistical CAD of Submicron CMOS Analog Circuits,” ISCAS, 1993

Consideration of Correlations Between Parameters

•First order Taylor series taken around nominal bias point

,..),( GSth VVfI

Method of Moments formula is applied this formula:

n

ij

n

iji

jiij

n

ii

in PP

P

f

P

fP

P

fPPf

1 11

221

2 )()())((2)()()),..,((

Pi=parameters to be matched

•Correlations are considered through second term in the sum

•Effect of each parameter on the variance of a function of these parameters is individually added by first term in the sum

Critical Analysis of Electrical-Empirical Parameter-based Mismatch Modeling

-Usually used to acquire a worst-case estimation

+Suitable for back-of-the-envelope calculations

-Real results are seldom worst-case, but occur according to a non-uniform probability distribution

-No layout consideration

+Used when starting a design

Outline




Layout Dependent Mismatch Modeling

WL

AP p

22 )(

K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,” JSSC, 1986

Ap=fitting constant for area

•Variance of deviation in a parameter is inversely proportional to the area of the transistors to be matched

J. M. Pelgrom, C. J. Duinmaijer and P. G. Welbers, “Matching Properties of MOS Transistors,” JSSC, 1989

Layout Dependent Mismatch Modeling

22 2 2( ) p

p

AP S D

WL

•Variance of deviation in a parameter is inversely proportional to the area of the transistors to be matched

•Variance of deviation in a parameter is directly proportional to the squared distance between the transistors to be matched

K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,” JSSC, 1986

Ap=fitting constant for area, WL

Sp=fitting constant for distance D

between matched transistors

•A consequent design strategy is laying out matched pairs closer and selecting their areas as large as possible

Extending Distance Parameter in the Fitting Model

G. Tulunay, G. Dundar and A. Ataman “A New Approach to Modeling Statistical Variations in MOS Transistors,” ISCAS, 2002

PyxfP ),()(2

•Distance parameter in Pelgrom’s model extended to a polynomial model by including first order terms => higher accuracy

x,y is location on wafera,b,c,d fitting constants

dcybxyxayxf )(),( 22

•Change in parameter P is modeled as a function of systematic and local variations

•Function f is obtained by fitting regression curves on factory provided manufacturing data

Improved Stochastic Estimation

M. Conti, P. Crippa, S. Orcioni and C. Turchetti, “Layout-Based Statistical Modeling for the Prediction of the Matching Properties of MOS Transistors,” IEEE TCAS-I, 2002

•Extensions to include inter-digitated and cross-coupled geometries through usage of stochastic theory

x

y

M1 and M2 are matched transistors in common-centroid layout style

M1 M2

•Parameters (x,y) formulated using integration over pairs’ areas

•A covariance matrix for (x,y) is formulated using Gaussians as an autocorrelation function•Levenberg-Marquardt least squared method used to fit parameters in the formulations to on-chip measurement data

Incorporation of Effective Lengths

S. J. Lovett, M. Welten and B. Mason “Optimizing MOS Transistor Mismatch,” JSSC, 1998

•Suggestion of usage of effective width and lengths instead, as dotted effective area important for matching

equal initial areas

for MOS channels

(solid lines)

M2M1

transistor channels

•Pelgrom’s equation used with effective lengths of transistors

•Algebraic estimation of L is possible using SPICE models

•Equal nominal mask areas for differing transistor shapes may result in mismatch when lengths in real chip are considered

•If L is nominal, L-L is the effective length caused by penetration of doping under channel region L

Leffective

Higher Regression Order for Area Term

MN

mnm

mn

n

nm

LLWW

CP

,

,

2

)()()(

T. Serrano-Gotarredona and B. Linares-Barranco, “Systematic Width and Length Dependent CMOS Transistor Mismatch Characterization and Simulation,” Analog IC and Signal Processing, 1999

•Higher order regression using Cnm terms as fitting constants

Cnm : fitting constants

•The choice of maximum regression order is questionable

•Builds on previous work and uses effective lengths in denominator

Criticism of Layout Dependent Mismatch Modeling

222

2 )( xpp DS

WL

AP

+Practical for an initial estimate

-More accurate ones requires a costly extraction procedure of fitting constants from the process

-Pelgrom’s model loses accuracy for longer distances

All models based on improving Pelgrom’s Equation:

Outline




C. Michael and M. Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992

Statistical Mismatch Modeling

2

M

M MI II

P A R

•Model for space dependent mismatch:

ij : standard deviation between Pi and Pj

Pi : a parameter of i’th transistor

Ri : independent N(0,1) random numbers

AMI : coefficients of the random numbers

R2

-space for parameter P :

|13||23|

|12|P1

P2

P3

MNPMN Ds

•Distances represent variances in -space analysis :

DMN : distance between transistors

sp : fitting constant

R3

A22 A32

A33

-space analysis relates variances in parameters to distances between transistors thus preserving space correlations

•Once P1 is fixed to origin, location of other transistors are found using geometry, then Aij values can be extracted on the axes


Principal Component Analysis (PCA) for Preserving Correlations

p

pPP

` •Normalize each parameter

n

i iPQ QPn

ρ1

``1

•Find correlations

•PCA helps preserve parameter correlations by writing each parameter as a function of independent principal components

P,Q : parametersP` : normalized parameter

`12/1 PUC

CUP 2/1` C : principal component vector : diagonal eigenvalue matrixU : eigenvector matrixP` : normalized parameter matrix

•Apply PCA by finding eigenvalues and eigenvectors of C first


An Example of PCA Application

654321 19.026.009.046.041.069.0` CCCCCCVFB

654321 12.049.033.009.077.005.0` CCCCCCMUZ

•P` values are unit normal, they are used in -space analysis as random numbers so that parameters correlations are preserved

•Area relationship is obtained through using a fitting constant

VFB` : normalized flat-band voltageMUZ` : normalized zero bulk bias mobilityCi : principal components, chosen unit normal

•PCA helps formulate normalized parameters in terms of independent principal components:

CUP 2/1`

•Remember that -space preserved distance based correlations

Q. Zhang, J. J. Liou, J. R. McMacken, J. Thomson and P. Layman, “SPICE Modeling and Quick Estimation of MOSFET Mismatch Based on BSIM3 Model and Parametric Tests,” JSSC, 2001

An Approach for SPICE Implementation

1xdelvtthV

•Unit normal random numbers, x1 and x2, generated

•SPICE parameters, delvt and delu0, are perturbed using different x1 and x2 each time to simulate a new process

)1(0 22

1/ xrxrdeluVthVth

x1, x2 : unit normal random numbers

r : correlation constantdelvt=deviation in threshold voltagedelu0=deviation in mobility

•SPICE parameters are perturbed directly:

Criticism of BSIM-based Mismatch Modeling

+Considers correlations

-Correlation constants are somewhat inaccurate themselves

-Requires fitting and process related constants

-Does not provide an intuitive understanding of mismatch

+Considers layout

-Parameter inaccuracies due to extraction from wafer may be magnified through PCA

Outline




P. G. Drennan and C. C. McAndrew, “Understanding MOSFET Mismatch for Analog Design,” JSSC, 2003

Physics-based Mismatch Modeling

2

2 2

ie pi i

e

p

•Basic idea : Mismatch is a physical phenomenon and physical parameters are independent

•If enumeration factors are such that |e| > |i|, estimation of physical parameter variances from electrical measurements is also possible

•pi’s can be Vfb, Tox, W, L, 0, Nsub, etc.

e : electrical parameterp : physical parameter

• Variance in electrical parameters written in terms of geometry dependent variances of physical parameters

pi’s are dependant on size and distance of transistors

•Due to complex formulas, CAD tools required

gm

Independent Normal

Correlated?

pdf?Level1

Level4

Level0

•Random effects mimicked through assigning pdf’s to Level0 parametersAn Tractable Physics-based Mismatch Model

nVFBNSUBLW

Vth Cox

tox

ID

k Level2

Level3

Correlated?

pdf?

Correlated?

pdf?

Correlated?

pdf?

R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004

Graph structured using SPICE formula hierarchy

Each node is a parameter

Connectivity Based Traversal•Proposed approach provides a manually tractable estimation

Vth

VT0

NSUB

PHI

Vth=f3(PHI,VT0)

VT0=f2(PHI,NSUB)

VT0=f1(NSUB) L1

L0

L2

L3

SVth = SVth * SPHI + SVth * ( SVT0 + SVT0 * SPHI )NSUB PHI NSUB VT0 NSUB PHI NSUB


•Chain rule used to relate a high level parameter to physical onesL0 : level 0

x

y

y

xS x

y

Connectivity Based Traversal

Vth

VT0

NSUB

PHI

Vth=f3(PHI,VT0)

VT0=f2(PHI,NSUB)

VT0=f1(NSUB) L1

L0

L2

L3



•Proposed approach provides a manually tractable solution•Chain rule used to relate a high level parameter to physical ones

Connectivity Based Traversal

Vth

VT0

NSUB

PHI

Vth=f3(PHI,VT0)

VT0=f2(PHI,NSUB)

VT0=f1(NSUB) L1

L0

L2

L3



•Proposed approach provides a manually tractable solution•Chain rule used to relate a high level parameter to physical ones

Bridging Physical Aspects to Circuit Parameters

circuit parameters

design parameters

SPICE parameters

L0

L1

L2

L3

L4

L5

L6

L7

L8

gm

CMRRrout

W LNSS T NSUB TOX

COX

GAMMA

PHI

egap

Vth

Id

PHIms

VFB

VT0

+Obviates the need for the use of correlations

+Provides an intuitive understanding for mismatch

Critical Analysis of Physics-based Mismatch Modeling

-Are all physical reasons accounted for?

+Suitable for diagnosis

-May physical reasons be correlated to chemical or even quantum-based reasons?

Outline




Sense Amplifier

CLK M2

M3 M4

M5 M1

Dependence of gain to variations in M4 when M3 nominal @800MHz

Gain vs NCH Gain vs TOXGain vs W

Insights for Future Models

Techniques for estimation of non-Gaussian distributions necessary

•Higher level circuit parameters for large variations indicate highly non-linear relationships; as opposed to linear ones observed for lower level parameters•Signifies that a Gaussian assumption is not accurate since linear sums of Gaussians are Gaussians, which can be completely described by (,)

Differential stage biased with current mirror

Iref

A simulation-based Proof by Contradiction

•Matched transistor group G1 introduced random mismatch to predict probability distribution function (pdf) of circuit gain

G1

pdf of gain

~Gaussian


Iref

G2

G3

pdf of gain

•Matched transistor groups G2 and G3 introduced random mismatch to predict probability distribution function (pdf) of circuit gain

non-Gaussian



Iref

G2

G3

G1

pdf of gain

Closer-to-real probability distribution should be estimated through models

non-Gaussian

•High level circuit parameters may not exhibit a Gaussian-like pdf when physical input parameters are assigned independent Gaussian distributions.


Summary:

•Circuit optimizations : remedy for a single circuit parameter

•Layout optimizations : used whenever possible yet insufficient

•Electrical / Empirical models : used when starting a design

•Layout-based models : Pelgrom’s Equation used to incorporate layout information

•BSIM-based models : used for direct SPICE implementation

•Physics-based models : used for better intuition and accuracy

Conclusions

•Deep sub-micron modeling needs has been identified as avoiding worst-case limits, consideration of random effects and an early estimation of mismatch

•Future models should target to obtain closer-to-real probability distribution functions of performance parameters

•A spectrum of mismatch models has been presented

Documents

Rasit Onur Topaloglu [email protected] University of California at San Diego Computer Science and Engineering Department La Jolla, CA, 92093, USA Mismatch