RAM Testing Algorithms for Detection Multiple

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RAM Testing Algorithms for Detection MultipleLinked Faults

V.G. Mikitjuk, V.N. Ym nolik, A.J. van de Goor*

Beloruss ian State Univ. of Informatics and Radioelectronics, P.Brovki 6 , Minsk, Belarus

*Delft Univ. of Technology, P.O.Box 5031,2600GA Delft, The N etherlands

Abstract

Many fault models for RAMs and tests for aults of these

models are available. In most cases these tests allow for

the detection of single faults only. This paper contains

fault coverage analysis of march tests which detect

multiple faults. It is shown there ar e faults which are not

detected by any of the existing march tests. So we proposenew test algorithms which c over multiple faults and

particularly are effective to detec t linked fau lts while, at

the same time, having short test time.

Key words: traditional RAM ault models, ,multiple linked

faults, march tests, inductive ault analysis.

1. Introduction

Testing Random Access Memories for all possiblefailures is not feasible. We have to restrict the class of

faults to be considered. This restricted class is called afault model. Many fault models for RAMs have beenproposed.

In this paper we consider traditional fault models and

tests which allow to detect not only single but also

multiple faults. We choose only march test algorithms

which require test times on the order of n (where n is the

number of bits on the memory). A1 orithms which require

test time on order of n2 or n3f2 are impractical for

modern high density RA M chips (16 megabits and more).Memory faults can be single or multiple. Multiple faults

additionally can be linked or unlinked. A fault is linkedwhen that fault may influence the behaviour of otherfaults [l]. A fault is unlinked when that fault does not

influence the behaviour of other faults. In [1,2] it isshown that faults are linked when they affect the samecell. The "link" between faults can cause the test not tofind any faults; this effect is called masking.

We show that not all linked multiple faults are detectedby existing tests. So we propose new effective algorithms

for testing linked faults. We prove that new algorithmshave higher fault coverage than existing march tests forlinked multiple faults.

Then, we consider fault models based on physicaldefects analysis [3,4] and show that the new tests are

effective for these faults too.

2. Concept of march tests

Many types of tests for RAMs have been proposed inthe past. Currently, one family of the tests, called march

tests [5 ,6] , has proven to be superior for test time andsimplicity of the algorithms.

A march test consists of a sequence of march elements.

A march element consists of a sequence of operation

applied to each cell in the memory, before proceeding to

the next cell. An operation can consist of writing a 0 into

a cell (WO), writing a 1 (wl), reading a cell with expectedvalue (rO and rl). The address of the next cell isdetermined by the address order. Two exist: an increasing

address order from address 0 to n-1 denoted by the *symbol; and a decreasing address order denoted by the e

symbol. When the address order is irrelevant, the a s

used.

3. Traditional RAM fault models

For the development of a fault model, a RAM s dividedinto three blocks:1) The address decoder.

2) The memory cell array.3) The RiW logic.

3.1.Faultsin th e memory cell array.

Many different faults can occur in a memory cell array.The following notation [2,7] will help to describe thefaults:? - denotes a w 1 operation to a cell containing a 0;

5 - denotes a WO operation to a cell containing a 1;

435;1066-1409/96 5.000 1996 EE E



-H - denotes a wx operation to a cell containing an x;

V - denotes any operation;

<S /F> - denotes a fault in a single cell;S - describes the value/operation sensitizing the fault;

ST - says that the sensitization effect appears after atime TF - describes the faulty value of the cell; FE(0,l)

SE { O , l , t , .1,e l ;

Failt A (1+2)I I

Fault B (1+3) I Fault C ( 2 4 ) Fault D (3+4)

<Si&, ..., S,1; F> - denotes a fault involving m cells.

Si, a , ...,S,1 describes the conditions of the m-1 cellsrequired to sensitise the fault in the cell m, the faulty

value is denoted by F.A stuck-atfault (SAF) means that the logic value of the

cell can not be changed by any action on the cell or by

influences from other cells. The notation <V /b denotes

an SA 1 fault and <V/O> - SA0 fault.

A memory cell with a transition faulr (TF) fails to

undergo at least one of the transitions O+l (<T/O>) or 1+

An inversion coupling fadt (CFin) [2,5-71 involvestwo cells i and j ; the fault is sensitised by a transitionwrite operation to a particular cell j . Cell j is called the

coupling cell and inverts the contents of cell i, which iscalled the coupled cell. Two different CFins can be

recognized: the <T;++> and thed;e>.An idempotent coupling fault (CFid) [2,5-71 involves

two cells i and j . The fault is sensitized by a transitionwrite operation to a cell j , which forces the contents ofanother cell i to a fixed value (0 or 1). In this paper we

consider CFs for which one cell may influence to anothercell by one way only. So four different CFih can be

recognised: <T;O>, <?;1>, <&;O>, <.1;1>.

Linked faults may occur between faults of the same typeor between faults of the different types. The S AF is alwaysdetected even when TFs or CFs are linked with the SA F[21. So we have to consider next linked faults i n thememory array: W-CF, CFid-CFid, CFid-CFin, CFin-CFin. These linked faults can involve not only two butany number of faults of these types.

O(<L/l>) .

3.2. Address decoder faults (AFs)

~

Figure 1.Combinations of address decoder faults

Functional faults that occur in the address decoder canbe the next [2]:0 Fault 1.With a certain address, no cell will be accessed.

0 Fault 2. A certain cell will not be accessible.

Fault 3. With a certain address, multiple cells areaccessed simultaneously.

Fault 4. A certain cell can be accessed with multiple

addresses.Because there are as many cells as addresses, none of

the above faults can stand alone. When fault 1 occurs

either fault 2 or fault 3 must also occur. With fault 2, atleast fault 1 or fault 4 occur; with fault 3, at least fault 1

or 4; with fault 4, fault 2 or 3. These four faultcombinations are shown in Figure 1 [2].

Faults A and B are inherently unlinked: it is notpossible to mask the fault when one reads Ax Faults C as

well as fault D may be linked.AFs linked and unlinked are detected by march tests for

the memory cell array if they satisfy the conditions ofTable 1 [2]. If the technology of RAM s known (i.e.

whether the memory device returns the AN D function orthe OR function when multiple cells are read), theconditions of Table 1 can be simplified. The simplifiedconditions are depicted in Table 2 [2].

3.3. Faults in the R/W logic

The RIW logic passes the data information from YO

pins to the memory array and vice versa. All faults in theRIW logic can be regarded as faults in the memory array[ 2 ] . t means that no separate tests for read/write logic arerequired.

4. March tests for detection linked multiple

faults.

There are many march tests optimized for a particularset of functional faults [2]. Descriptions of theiralgorithms are presented in the Table 3. Table 4 containsfault coverage analysis of these march tests. The columnsCFin-CFin, CFin-CFid in this table are empty. It says thatthere is a problem to detect these faults.

Table 1. Conditions for detecting AFs

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Description of algorithm

MATS++

March X

-(WO); fi(ro,wI); U(rI,wo,rO)

@(WO); fi(ro,wl); b(r1,wO); a ( r 0 )

March C-

March A

March B

The new test March M which we present in this paper

detects all linked multiple faults under the fault models.Note that, in general, not every linked CFin can be

detected by march tests. To simplify the discussion, thefollowing notation will be usedfi<S;F> - fault in which the coupled cell has a higher

address then a coupling cell;UcS;F> - fault in which the coupled cell has a lower

address then a coupling cell.

So there are four different types of inversion CFs: f i <? ; ~

Theorem 1. Linked inversion CFs are not detected by anymarch test if they contain an even number (or 0) ofinversion CFs of each type.

Proof : if there are these faults, any march element willgenerate an even number of inversions in the coupled cell

>, fi<l;H>,<?;->, U<l;w>.

-(WO); fi(ro,wl); fi(r1,wO); U(ro,wl);

b(r1 WO);

-(WO); fi(rO,wl,wO,wl); fi(rl,wO,wl); 8(rl wO,w 1 WO);U(rO,wl,wO);

-(WO); fi(r0,wl ,rl,wo,rO,wl);

fi(rl,wO,wl);

U(rl,wO,wl ,WO);U(r0,w 1,wo);

with the expected state as result. Thus no fault can bedetected.

So March M also cannot detect the faults which satisfytheorem 1. But these faults constitute only small part ofall linked inversion CFs. So, in Table 4 nd further, bylinked minswe will mean faults which do not satisfytheorem 1.

Table 5 contains a description of the new 16n-length

test algorithm. This test is shorter than March B (the mostuniversal march for traditional RAM faults) and has

higher fault coverage. It can be proven that March Mdetects all these faults.

Theorem 2. March M detects all SAFs.Proof: it is easy to show that March M detects all SAFs.

A 0 and 1 is written into and read from every memory cell(for example in Ml) , so S A F O and SAFl are detected.Theorem 3. March M detects all TFs and TFs linked withCFs.Proof : these faults are detected by M1 and M5. M1

generates an 1' transition in every cell and immediately

thereafter the cell is read, so <l'/O> faults are detected. Asno other cells are written in between, the TF cannot be

masked by a CF. faults will be detected by M5

and cannot be masked by a CF for reasons similar tothose for <T/o> TFS.

Theorem 4. March M detects all CFids.Proof :march elements M1 and M5 which contain 2 write

operations and the following march elements M2 and M6

which contain only one read operation allow to detect

every CFid. The address order of these march elements is

irrelevant. M1 sensitizes and then detects any faults fi<?;l>, fi<&;l>. oreover M1 sensitizes any faults k ? ; l > ,

k & l > which afterwards are detected by r0 operations in

M2. Note: if M1 would have the address order+, t

435'



Table 5. Test March M.

~

sensitizes and then detects any faults k ? ; I > , Ikl;l>,and sensitizes any faults fi<?;I>, fi<L;l> which then are

detected by M2. Similarly we can show that faults fit?;O>,hc.!.;O> and -k?;O>, I k L ; O > are detected by march

elements M5 and M6.Theorem 5. March M detects every CFid-CFid

Proof : for detection of every linked CFids the addressorders of march elements M I and M5 have to coincide as

in table 5. In this case one of the -ids which are linked

will be always detected :

- the CFid with the shortest distance between a coupledand a coupling cell if the coupled cell has a larger address

than the coupling one (QcT;l>,<$;l> re detected by

M1; fl<?;O>, % d ; O > are detected by M4);

- the CFid with the largest distance between a couplingand a coupled cells if the coupled cell has a smalleraddress than the coupling one (k?;l>,<$;l> are

detected by MI and M2; k? ;O> , k & ; O > are detected by

M5 and M6).These faults never can be masked by another CFid in

these march elements and so they will be detected.Theorem 6 . March M detects every CFin-CFid.Proof :march elements M1, M2 and M5, M6 detect everyCFin-CFi$. k ? ; b and fl<&;l> Fids are detected by

M I and they can be masked in this march element only by

an odd number of h c ? ; ~ >r fi<&;w> Fjns, if the thecoupling cells of these CFins have larger addresses thanthe coupling cell of the CFid .But such linked faults will

be detected by M5. &?;1> and &&;I> CFids aresensitized by M1 and are detected by M2; they can be

masked only by an odd number of kt;++>r k L ; e >

CFins, if the coupling cells of these CFins have largeraddresses than the coupling cell of the CFid .But suchlinked faults will be detected by M5 and M6.

Similarly we can show that CFids k ? ; O > , n<L;O> and

k ? ; O > , I k L ; O > , if they are masked by CFins in march

elements M5 and M6 will always be detected by marchelements M I and M2.Theorem 7. March M detects all CFins and linked CFins.

Proof : as follows from theorem 1 linked CFin can be

detected by march tests only if it involves an odd numberof faults if only one from four types of CFins.

March element M3 is surrounded by march elementsM2 and M4 which do not generate CFins, what rules outthe possibility of compensation one another CFins whichare initiated by neighbouring march elements. M3sensitizes and detects any faults If<?;@> and linked

CFins which involve an odd number of fi<?;~>.Moreover M3 sensitizes d<f;++>aults and linked Wins

which involve an odd number of U<?;++> These faults

are detected by read operation in M4.Then it remains to be proved that March M detects kl

;@>and k$ ;w> Fins and linked CFins which involve

an odd number of fl<L;@>or .kL;@> faults (but do not

involve an odd number of<?;e>aults as they detects by

M3 and M4). These faults will be detected by marchelement M5 and M6. fl<$;++> aults will be sensitized

and detected by M5 but a<&;@>aults will be sensitized

by M5 and then will be detected by the read operation inM6.Theorem8. March M detects all AFs.

Proof :March elements M3 and M7 satisfy the conditionof table 1,so AFs are detected.

We have proved that the new 16n test detects all linkedmultiple faults. As follows from proofs of theorems 2-8march element M7 is required only for the detection ofAFs. So we present two new 14n algorithms March M--OR and March M - - m which allow to detect all linkedmultiple faults when the technology of the RAM is

known.Descriptions of their algorithms are presented below.

March M--oR:

-(WO); =@,wl,rl ,WO); e( r0) ; *(rO,wl); e ( r1); 9

(rl,wO,rO,wl); -(rl)

March M - - A ~ :a(w 1); -(rl,wO,rO,wl); W r l ) ; *(rl,wO); w(r0 ); *(rO,wl,rl,wO);*(rO)

Theorems 2-7 prove that all linked multiple faults inthe memory array are detected by the new 14n tests. Boththese algorithms satisfy the conditions of Table 2, so theyallow to detect AFs if the technology is known.

5. Development of the new tests to detect

faults based on real phisi-cal defects

The traditional fault models were largely based uponthe mathematics and not on the actual manufacturingdefects. Dekker et. al. [3] applied defect orientedinductive fault analysis (FA) to evolve a SRAM faultmodels. Spot defects were the basis of this analysis.

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Oberle [4] attempted a similar approach on DRAMs.Efficient fault models of the circuits can be derived fromthis analysis:

1. A memory cell is stuck-at 0 or stuck-at 1.2. A memory cell is stuck-open.3. A memory cell is coupled to another cell.4.

A memory cell has multiple access faults.5. A memory cell suffers from a data retention fault.

As we see two new fault models there are in this list.

A stuck-open fault (SOF) means that a cell cannot beaccessed, perhaps because of an open word line [3,7].When a read operation is performed on a cell, the

differential sense amplifier (SA) has to sense a voltagedifference between the bit lines of that cell. In the case ofSOF, both bit lines will have the same voltage level;consequently the output value produced by the senseamplifier depends on the way it is implemented. If the SA

is combinational or if the SA has only a single input, it

will pass a defined logical value to the output pin. In thiscase a stuck-open fault will be detected as if it was a

stuck-at fault. However, some designs of sense amplifiersinclude a latch in the read path. Then a SOF may havethe effect that the latch is not update because the voltagedifference between the bit lines is too small. The previousoutput value is produced as the output value for the SOF.Dekker et al. [3] highlighted the problem of stuck-opendetectability for sequential R N ogic. They suggestedthat there must be a march element in which the value x

and the value x are read from a cell, and another, or

possibly the same, march element, where value x and the

value x are read from a cell. As march elements M1 andM5 in the new tests satisfy these conditions so tests whichwe presented allow to detect SOFs. It is easy to see that

SOF is always detected even if it linked.A datu retention fault (DFW) occurs when a cell fails to

retain its logical value after some period of time [3]. Twodifferent DRFs can be recognized (both may be

simultaneously present in a single cell): < 1 ~ / 0 > nd

c*/l>. When both are present in one cell, the cell

behaves as if it contains an SOF (because there will not beIvoltage difference between bit lines) [7].

Any march test can be extended to cover D W s [7]. Theletection of a DRF requires that a memory cell be broughtnto one of its logic states. A certain time (called delayime) must pass while DRF develops. Thereafter the:ontents of the cell are verified. This test must be repeatedivith the inverse logic value stored into the cell. So belowive present a development of the new tests to detect DRFs.

March M:s( w0 ); =+(rO,wl,rl,wO); Del; e ( r0 ) ; *(rO,wl); m(r1);

*(rl,wO,rO,wl); Del; e ( r1) ; c=(rl,wO).

March M--oR:

--

@(WO); *(rO,wl,rl,wO); Del; w(r0); *(rO,wl); a ( r 1 ) ;

*(rl,wO,rO,wl); Del; e ( r 1 )

March M--AND:a( w1 ); *(rl,wO,rO,wl); Del; a ( r i ; *(rl,wO); a(r0);

+-O,wl,rl ,wO); Del; e@)

The Del elements represent the delay time which one

must wait before applying the next march element. Theamount of time to wait depends on the amount of charge

stored in the capacitor of the node and magnitude of the

leakage current. For example the delay time for thePhilips 8k8 design can be up looms [3].

As our tests have march elements which contain only aread operation (M2 and M6) there is no need for theaddition of a special data retention test as in [3,7]. In our

case fault masking can not occur.

6. Conclusion

In this paper we have presented new efficient march

tests for RAMS.These tests allow to detect not only singlebut also multiple linked faults under the fault models.March M is the most universal test algorithm whichdetects 100% of the faults when the RAM echnology isunknown. If the RAM echnology is known March M--OR or March M--AND may be applied.

The proposed algorithms show excellent features inboth test time and fault coverage. They are shorter than

another algorithms for linked faults and have higher faultcoverage. Moreover new tests allow to detect faults basedon real phisical defects with minimal overheads.

References

1. C.A. Papachristou and N.B.Sagha1, "An Improved Methodfor Detecting Functional Faults in Random Access Memori-es", IEEE Trans. Computers, Vol. C-34, No. 2, 1985, pp.110-

116.2. A.J. van de Goor, Testing Semiconductor Memories, The-

ory and Practice, John Wiley & Sons, Chichester, UK , 1991.3. R.Dekker, F.Beenker and L.Thijssen, "Fault Modelling andTest Algorithm Development for Static Random Access

Memories", Proc. of Int. Test Conf., pp.343-352, 1988.4. H.D.Oberle and P.Muhmenthaler, "Test Pattern-Develop-ment and Evaluation for DRAMs with Fault SimulatorRAMSIM", Proc. of Int. Test Conf., pp.548-555, 1991.5. D.S Suk and S.M.Reddy, "A March Test for FunctionalFaults in Semiconductor Random-Access Memories", IEEE

Trans. Computers,Vol. C-30, No.12, 1981, pp.982-985.6. M.Marinescu, "Simple and Efficient Algorithms forFunctional RA M Testing", Proc. IEEE Int. Test Conf., 1982,

7. A.J. van de Goor, "Using March Tests to Test SRAMs",Design & Test of Computers, Vol. 10,No.1, 1993, pp.8-14

pp.236-239.

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RAM Testing Algorithms for Detection Multiple