Rajeev K. RanjanAdvanced Technology Group

Synopsys Inc.

On the Optimization Power of Retiming and Resynthesis Transformations

On the Optimization Power of Retiming and Resynthesis Transformations

Joint work with:Vigyan Singhal, Cadence Berkeley Labs, BerkeleyFabio Somenzi, Univ. of Colorado, BoulderRobert K. Brayton, Univ. of California, Berkeley

All circuit optimizations

(T+S)*

Re(T)iming

(S)ynthesis

MotivationMotivation

Optimization capability of retiming and resynthesis - an open question

Theoretical foundation for practical retiming and resynthesis based synthesis and verification

This WorkThis Work

C1 C2(Retiming + Resynthesis)*

(special 2-way split + merge)*

Circuit

G1 G2StateGraph

This WorkThis Work

(Retiming + Resynthesis)*

G2(special 2-way split + Merge)*

C1 C2Circuit

G1StateGraph

OutlineOutline

Background

Complexity Result

Extensions to retiming and resynthesis

Summary

Background:Sequential CircuitBackground:Sequential Circuit

•Gates and memory elements

•Edge triggered

•Single global clock

Background:State Transition Graph (STG)Background:State Transition Graph (STG)

States(values of latches)

Transitions(input minterms)

baCIRCUIT:

0 1

11 0-, -00-, -0

11

STG:

Background:Combinational SynthesisBackground:Combinational Synthesis

Primary Inputs Primary Outputs

Latch InputsLatch Outputs

Background: RetimingBackground: Retiming

[Leiserson & Saxe]

Retime by +1

Retime by -1

Iterative Retiming and Resynthesis:(T + S) *Iterative Retiming and Resynthesis:(T + S) * Retiming changes interaction between different

combinational blocks

Combinational synthesis generates new candidate latch locations

Sequence of retiming and synthesis provides powerful sequential optimization technique [Malik and Sentovich] [Iyer and Ciesielski] [Hassoun and Ebling]

Retiming & Resynthesis:Optimization CapabilityRetiming & Resynthesis:Optimization Capability

Previous Work [Malik91]:

Fixed states and transitions:- arbitrary state encoding

General STG transformations:- incomplete classification

STG (states, transitions, encoding) transformation

Our Work:

General STG transformations:- Complete and tight classification

State Transformations: Split and Merge [Malik91]State Transformations: Split and Merge [Malik91]

s

v

b

uac

d

s1

s2v

bb

ua

a

c

d

SPLIT

MERGE

Definition:1-Step Equivalence of StatesDefinition:1-Step Equivalence of States

Defined over a pair of states in an STG.

s

tv

bb

ua

a s and t indistinguishable

in 1 step

p

p

Definition:1-Step Equivalent TransformationDefinition:1-Step Equivalent Transformation

Defined as 2-way merge and split involving

1-step equivalent states

Definition:1-Step Equivalent GraphsDefinition:1-Step Equivalent Graphs

Class of graphs obtained by applying a

sequence of 1-step equivalent

transformations

1 Step Equivalence

Applied to sufficiently delayed configuration of circuits

Definitions: Summary Definitions: Summary

States Given an STG,states with identical transitions.

Transformations

Merge two states

Split a state into two states

Given an STG,

GraphsGiven two STG’s

transformations

G1 G2

OutlineOutline

Background

Complexity Result

Extensions to retiming and resynthesis

Summary

C1(S+T)*

C2G1 G2 Prove for single transformation (generalize by induction).

Prove for 2-way split.

2-way merge follows: C2 can generate C1 (reversible transformations). “2-way merge” on G2 leads to G1.

Strategy: Generate internal points for new codes. Move latches to these internal points.

Generate New State CodesGenerate New State Codes

Trivial mapping for all states except s

For s, split state (t or u) can be obtained by current state (s1) and input (c)

Trivial mapping back to original codes

s

s4b

s3ac,d

s2

s1

c,d

G1

t

us4

bb

s3a

a

s1

s2

c

d

c

d2-way split

G2

Implementing State SplitImplementing State Split

C1

IN

C

C’

Synthesis

C1

IN

C

C’

Retiming Synthesis

C1

IN

: Code for C1: Code for C2

C2

IN

C1(S+T)*

C2 G1 G2

Synthesis does not change STG

Retiming = (Basic retiming) *

Basic retiming results in 1-step equivalent graphs

Composition:

G1 G2 G X G1 G X G2

Result follows by induction

Retiming Across NAND GateRetiming Across NAND Gate

Graphs are 1-step equivalent.

00

00

00

11 11

11

00 01

10 11

1

1

1

0

0 1

1111

0-, -0

0-, -0

10

Retiming Across Fanout JunctionRetiming Across Fanout Junction

0 1

01

1

0

00 110 0 11

01 1001 10

00 11

01

00 110

1

Graphs are 1-step equivalent.

Ignore transient states

OutlineOutline

Background

Complexity Result

Extensions to retiming and resynthesis

Summary

AnalysisAnalysis

Retiming and resynthesis optimization involves only a local notion of state equivalence

Covers only a subset of all valid STG transformations

Limitation of (S + T)* - 1st ExampleLimitation of (S + T)* - 1st Example

00 01 11 10

0 1 0 1

C1 C2

0 1

0 1

C1(S+T)*

C2 [Zhou97]

Extending Synthesis: Eliminate Floating LatchesExtending Synthesis: Eliminate Floating Latches

00 01 11 100 1 0 1

C1

0 10 1

00 11 01 100 1 0 1

Re-encoding

C2

Eliminate floating latch

Limitation of (S + T)* - 2nd ExampleLimitation of (S + T)* - 2nd Example

001

001

001

--0 --0

--0 --0

x

ye

eC1

xy

eC2

00 01

10 11

0

0

0

1

C1(S+T)*

C2

else else

0 1

111

0-1, -01

10

Extending Retiming: Retiming Enabled LatchesExtending Retiming: Retiming Enabled Latches

ee

xy

e

RETIME

x

ye

e

xy

e e

xy

e

All circuit optimizations

SummarySummary

Characterized wrt STG transformations

(S+T)*

Re(T)iming

(S)ynthesis

Obtain tight bounds for extended transformations