Radius-wise track identification

Radius-wise track identification

February 28, 2012

Vladimir GromovNikhef, Amsterdam, the Netherlands

TWEPP-09 V.Gromov 222/09/09

Micro-pattern gas detectors: layout and features

- particle track image (projection)- particle track image (projection)- 3D track reconstruction3D track reconstruction- no sensor leakage current compensation- low parasitic capacitance (less than 10fF)-micro-discharges in avalanche gap

-Gas volume = Correlated layers

Cluster3

Cathode (drift) plane

Gas Amplification Structure

Cluster2 Cluster1

Readout chip

1mm …1m → Drift gap

400V50um → Avalanche gap

Gas-avalanche detector combining a gas layer as signal generator with a CMOS readout pixel array

Front-endcircuit

Cpar

Timepix-3 V.Gromov 313/03/12

Task definition: Lorenz force and particle trajectory

F = q (V x B)

B

V

F

items to clarify:-mathematic formula describing trajectory of charged particle moving in magnetic field- definition of momentum of moving particle check: … /Common doc/Conferences/TWEPP-10/physics for pedestrians.pdf and http://en.wikipedia.org/wiki/Momentum


Detector layout

items to clarify:-pT = transverse momentum or the momentum that is perpendicular to the beamline of a particle detector- why a high-pT particle moves radius-wise whereas a low-pT particle has a curved track

Z coordinate = don’t care dimensionCilindric 3D coordinate system → Polar 2D coordinate system (transverse to Z-axis)2D geometry : r = radius φ = azimuth angle

high-pTB

low-pT

many rows

a few rows

Pixel readout array

Pixel array: 256rows x 32 cols

z

φ

55µ

Gas Volume drift gap @ 8mm

E

z

Pixel array 2cm2 : 256 rows x 32 columns

480µ

Periphery circuit

Contact pads

Common OR path ???

The first fullscale prototype FE-I4A consists of an array of 80x336 pixels with a size of 50x250 µm2

organized in double-columns, and a periphery of height approx. 2

mm.

80cols●0.25mm = 20mm

33

6ro

ws●

0.0

5m

m =

16

.8

mm


Pixel matrix : charge collection related dead time

One-pixel- hit – the-whole-column-dead approach causes 1% data loses at the rate of 0.25 ● 106 tracks ● cm-2 ● sec-1

Occupancy: 0.25 ● 106 tracks ● cm-2 ● sec-1

6 ● 106 hits ● cm-2 ● sec-1 ( 8mm drift gap @ 3e-/mm)12 MHz / chip50kHz / column (every 20msec there is a hit pixel in the column)Assume 25ns is needed for column-wise readout (the whole column is dead) Chance to get a new hit during the dead time = 25ns / 20ms = 0.1%Charge collection-related dead time : Vdrift ● L gap = 25ns/mm ● 8mm = 200ns Common-column OR signal will be kept for 200ns (dead time) Data losses = 200ns / 20ms = 1 %

220µ

φ

z

55µ


W4

W3


Pixel matrix : readout structure

∑

z-

1

z-

1

z-

1

z-

1

∑ ∑ ∑

Finite Impulse Response Integrator (FIRI)

Col.1 Col.2 Col.3 Col.4

Com

OR

1

W1

BXID

z-

1

z-

1

z-

1

BXID Pipeline

min BXID ≠ 0

BXID Pipeline &FIRI

BXID Pipeline &FIRI

BXID Pipeline &FIRI

∑W2

min BXID ≠ 0

> THR_track

W1+W2+W3+W4 W1 W2 W3 W4 Track ID Track type below THR_track don’t care don’t

caredon’t care

don’t care 0 No Track

above THR_track 1 0 0 0 1 Highest-pT ↓ 1 1 0 0 2 High-pT ↓ 1 1 1 0 3 Low-pT ↓ 1 1 1 1 4 Lowest-pT

Track ID

BXID_hit_4

BXID_hit_1

BXID_track

Region Track Status Resolver

Track ID

BXID_track

Com

OR

2

Com

OR

3

Com

OR

4

ComOR 2

ComOR 5 ComOR 4

ComOR 3 Region Track

Status Resolver

Global Track Status

Resolver

BXID_track

Track ID

Columns are rows in factCoordinate of the track = row with min BXID

THR is not a level but transition 6 →7

Definition of the row width, and dependence angle (pT) number of rows involved (pT)

Ncsim simulation with a realistic data = Matrix (rows state , BX) 128 x 128

Correlated rows archtecture

W4

W3


Pixel matrix : readout structure

∑

z-

1

z-

1

z-

1

z-

1

∑ ∑ ∑

Finite Impulse Response Integrator (FIRI)

row.1 row.2 row.3 row.4

Com

OR

1

W1

BXID

z-

1

z-

1

z-

1

BXID Pipeline

min BXID ≠ 0

BXID Pipeline &FIRI

BXID Pipeline &FIRI

BXID Pipeline &FIRI

∑W2

min BXID ≠ 0

THR_track 6 → 7

W1+W2+W3+W4 W1 W2 W3 W4 Track ID Track type below THR_track don’t care don’t

caredon’t care

don’t care 0 No Track

above THR_track 1 0 0 0 1 Highest-pT ↓ 1 1 0 0 2 High-pT ↓ 1 1 1 0 3 Low-pT ↓ 1 1 1 1 4 Lowest-pT

Track ID

BXID_hit_4

BXID_hit_1

BXID_track

Region Track Status Resolver

Track ID

BXID_track

Com

OR

2

Com

OR

3

Com

OR

4

ComOR 2

ComOR 5 ComOR 4

ComOR 3 Region Track

Status Resolver

Global Track Status

Resolver

BXID_track

Track ID

Coordinate of the track = row with min BXIDTHR is not a level but transition 6 →7

Has been ch

arged la

ter

on

high-pTB

low-pT

many pixels

a few pixel

Pixel readout array

Gas Volume drift gap @ 8mm

E

φ

z


1

2

3

φ

z

1

2

3

Leftward Shift register Rightward Shift registerColumns are rows in factCoordinate of the track = row with min BXIDTHR is not a level but transition 6 →7


Col. 1

low-pTB

E

Col. 2

Col. 3

Col. 4

8mm

Columns are rows in factCoordinate of the track = row with min BXIDTHR is not a level but transition 6 →7

High-pT track response

Timepix-3 V.Gromov 1

013/03/12

BX k-1 k k+1 k+2 k+3 k+4 k+5 k+6 k+7 k+8 k+9 k+10 k+11 k+12 k+13 k+14 k+15 k+16

Col. 1

W1

Col. 2

Col. 3

Col. 4

THR_hit

THR_track

BX_hit.1

Col. 1 = coordinatehigh-pTB

E

Col. 2

Col. 3

Col. 4

8mm

BX W1 W2 W3 W4 W1+W2+W3+W4

Track ID BXID track

k 1 0 0 0 1 0 kk+1 2 0 0 0 2 0 kk+2 3 0 0 0 3 0 kk+3 4 0 0 0 4 0 kk+4 5 0 0 0 5 0 kk+5 6 0 0 0 6 0 kk+6 7 0 0 0 7 0 kk+7 8 0 0 0 8 1 kk+8 7 0 0 0 7 0 k+1k+9 6 0 0 0 6 0 k+2

θ = arctg [1●55µm/ 8mm ]

THR_track

Columns are rows in factCoordinate of the track = row with min BXIDTHR is not a level but transition 6 →7



113/03/12


FIRI out

THR_track

BX_hit.1

8row OR

low-pT

B

row47

θhigh-pT

row14

row37

drift gap (10mm)

Low- pT track response


213/03/12

BX k-1 k k+1 k+2 k+3 k+4 k+5 k+6 k+7 k+8 k+9 k+10 k+11 k+12 k+13 k+14 k+15 k+16 k+17

Col. 1

W1

Col. 2

Col. 3

Col. 4

THR_hit

BX_hit.1

Col. 1 = coordinatelow-pTB

E

Col. 2

Col. 3

Col. 4

8mm

θ

W2

W3

W4

BX_hit.2

BX_hit.3

BX_hit.4

THR_hit

THR_hit

THR_hit

BX W1 W2 W3 W4 W1+W2+W3+W4

Track ID BXID track

k 1 0 0 0 1 0 kk+1 2 0 0 0 2 0 kk+2 2 1 0 0 3 0 kk+3 2 2 0 0 4 0 kk+4 2 2 1 0 5 0 kk+5 2 2 2 0 6 0 kk+6 2 2 2 1 7 0 kk+7 2 2 2 2 8 4 kk+8 1 2 2 2 7 0 k+1k+9 0 2 2 2 6 0 k+2

Low- pT track response


313/03/12

BX k-1 k k+1 k+2 k+3 k+4 k+5 k+6 k+7 k+8 k+9 k+10 k+11 k+12 k+13 k+14 k+15 k+16 k+17

Col. 1

W1

Col. 2

Col. 3

Col. 4

THR_hit

THR_track

BX_hit.1

Col. 1 = coordinatelow-pTB

E

Col. 2

Col. 3

Col. 4

8mm

θ

θ = arctg [4●55µm/ 8mm ]

W2

W3

W4

BX_hit.2

BX_hit.3

BX_hit.4

THR_hit

THR_hit

THR_hit

Columns are rows in factCoordinate of the track = row with min BXID

Destrete-time digital fimit impule response filter

A discrete-time FIR filter of order N. The top part is an N-stage delay line with N + 1 taps. Each unit delay is a z−1 operator in Z-transform notation.

OR

Types of Digital FiltersThe input xn and output yn sequences of a digital filter both represent signals sampled at discrete, uniformly spaced, time increments t n. A finite impulse response (FIR) digital filter takes N+1 of the most recent input samples of xn, multiplies them by N+1 coefficients, and sums the result to form yn. For an infinite impulse response (IIR) filter, the M previous output samples of yn are weighted and added in as well. In other words, an IIR filter uses feedback. This is expressed mathematically by

All of the a's are zero for a FIR filter. The main advantage of IIR filters is that they can produce a steeper slope for a given number of coefficients. The main advantage of FIR filters is that the group delay is constant. This provides the capability of obtaining both a steep cutoff and perfect phase response. This is impossible to achieve with an analog filter.

Filter Transfer Functions and the z-transformThe frequency domain response, or transfer function can be obtained from a z-transform, which is defined by

With r=1, equation (2) is the discrete Fourier transform of y, so evaluating Y with r=1 yields the frequency response. Using the fact that

The z-transform of equation (1) is

Then the transfer function is given by

$display - Print to screen a line followed by an automatic newline.$write - Write to screen a line without the newline.$swrite - Print to variable a line without the newline.$sscanf - Read from variable a format-specified string. (*Verilog-2001)$fopen - Open a handle to a file (read or write)$fdisplay - Write to file a line followed by an automatic newline.$fwrite - Write to file a line without the newline.$fscanf - Read from file a format-specified string. (*Verilog-2001)$fclose - Close and release an open file handle.$readmemh - Read hex file content into a memory array.$readmemb - Read binary file content into a memory array.$monitor - Print out all the listed variables when any change value.$time - Value of current simulation time.$dumpfile - Declare the VCD (Value Change Dump) format output file name.$dumpvars - Turn on and dump the variables.$dumpports - Turn on and dump the variables in Extended-VCD format.$random - Return a random value.

...) ; $fstrobe (arguments) ; $fmonitor (arguments) ; $readmemb ("file", memory_identifier [,begin_address[ ... data from a file and store it in memory, use the functions: $readmemb and $readmemh . The $readmemb task reads binary data and $readmemh reads hexadecimal data. Data has to exist ... [3:0] memory [15:0] ; initial begin $readmemb ("data.bin", memory) ; end Loading data in...http://www.verilog.renerta.com/source/vrg00016.htm

2. Verilog - PLA Modeling Tasks - verilog.renerta.com ... tasks are used to model content addressed memories i.e., memories that are read at locations that an input address matches a stored address. The PLA devices can be synchronous or asynchronous (type is defined by array_type : sync and async ). All patterns should be loaded into memory using the $readmemb and $readmemh system tasks or assigned by procedural assignments. Both the input_terms and the output_terms should be concatenations of scalar variables,

but all variables from the output_terms should be declared as a reg data type. The input_terms should have the length equal to the memory word size...http://www.verilog.renerta.com/source/vrg00034.htm

The $readmemb system task in Verilog allows a program to read data from a text file with binary formatted data. For example, if a file test_data_bin.dat contains the data 00000001000000010000000100000001 11111111111111111111111111111111 01010101010101010101010101010101 00000000000000000000000000000000 10101010101010101010101010101010 01010111110101111110101111101111 11111111111111111111111111111111 10101010101010101010101010101010 Then this snippet can read in this data and display itmodule verilog_readmemb;reg [31:0] data_ram [0:7];integer ii;initial begin $readmemb("test_data_bin.dat",data_ram); for (ii=0;ii<8;ii=ii+1) $display("%x",data_ram[ii]); $stop;endendmodule

Task definition


713/03/12

- High pT threshold ( 3Gev/c) → θ = 5.7°8 rows in the group 8● 0.11mm / 10mm = arc tangens (5.7°)

- Drift Gap = 10mm →Drift time = 200ns = 8BX

low-pT

B

row47

θhigh-pT

row14

row37

drift gap (10mm)


821/03/12

Pixel matrix : readout structure1

28

row

s (

pix

el :1

10

µm

x

220

µm

)

∑

z-

1

z-

1

z-

1

z-

1

∑ ∑ ∑

8 BX Frame Integrator

BXID

z-

1

z-

1

z-

1

BXID Pipeline (9BX deep)

min BXID ≠ 0

Digital Time Filter (DTF)

Common-row-OR

DTF

IN

IN

OUT

OUT

COMPTHR

8-Row Group

FIFO

COMP

DTF COMP

DTF COMP

DTF COMP

DTF COMP

DTF COMP

DTF COMP

Redundancy Correction

End-of-Chip FIFO

Peri

ph

ery

B

us

z-

1

z-

1Pipeline (4BX deep)

z-

1

z-

1

VETOfrom 7 rows UPfrom 7 rows DOWN


FIFO






PeripheryPixel Array

VETO

VETO

VETO

VETO

VETO

VETO

VETO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

High_pTBX_ID

& ROW_ID

High pT Trigger V.Gromov 1

915/03/12

Format of the input data

0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000010000000000000000000010000000000000000000001000000000000000001000000000000000000010000000000000000000000010000000000000000100000000000000000010000000000000000000000000100000000000000010000000000000000010000000000000000000000000001000000000000001000000000000000010000000000000000000000000000010000000000000100000000000000010000000000000000000000000000000100000000000010000000000000010000000000000000000000000000000001000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

RowID = 0 RowID = 127

BXID = 0

BXID = 12

8 BX = 200nsTrack Appearance

Time

Common OR / ROW / BX

LOW pT (neg. charged)

LOW pT (pos.

charged)

HIGH pT


021/03/12

Proposed readout structure : RTL simulation00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

RowID = 8BXID_hit = 3

RowID = 8BXID_hit = 3510= 2316

high pTtrack

high pTtrack



413/03/12


Integrator

THR_track

BX_hit.1

8row OR

low-pT

B

row47

θhigh-pT

row14

row37

drift gap (10mm)

0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000010000000000000000000000000000000000001000000000000000000000000100000000000000000000000000000000000100000000000000000000000001000000000000000000000000000000000010000000000000000000000000010000000000000000000000000000000001000000000000000000000000000100000000000000000000000000000000100000000000000000000000000001000000000000000000000000000000010000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100000000000000001111111100000000000000000000000000001111111100000000000000000111111110000000000000000000000000001111111100000000000000000011111111000000000000000000000000001111111100000000000000000001111111100000000000000000000000001111111100000000000000000000111111110000000000000000000000001111111100000000000000000000011111111000000000000000000000001111111100000000000000000000001111111100000000000000000000001111111100000000000000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100000000000000001111111100000000000000000000000000002222222200000000000000001222222210000000000000000000000000003333333300000000000000001233333321000000000000000000000000004444444400000000000000001234444432100000000000000000000000005555555500000000000000001234555543210000000000000000000000006666666600000000000000001234566654321000000000000000000000007777777700000000000000001234567765432100000000000000000000008888888800000000000000001234567876543210000000000000000000007777777700000000000000000123456776543210000000000000000000006666666600000000000000000012345666543210000000000000000000005555555500000000000000000001234555543210000000

0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100000000000000000000001100000000000000000000000000001111111100000000000000000000001110000000000000000000000000001111111100000000000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

BC #0

BX#12BC #0

BX#12

BC #0

BX#12

BC #0

BX#12

row #0 row #60

Original data

Dynamic Frames (8 OR)

Integration in time (8 BX)

Comparator output (THR=7)

High pT tracks

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111110000000000000000000000000000000000000000000011111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111110000 0000000000000000000000000111111111111111111111111111111000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111110000 0000000000000000000000000222222222222222222222222222222000000000000 00000000000000000222222222222222222222222222222 00000000000000000000000000000222222222222222222222222222222 00000000000000000000000000000222222222222222222222222222222 0000000000000000000000000000022222222222222222222222222222200000000000000000000000000000222222222222222222222222222222 00000000000000000000000000000222222222222222222222222222222000000000000000000000000000001111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

BC #0

BX#12

BC #0

BX#12

BC #0

BX#12

row #0 row #60

Low pT tracks

Original data

Dynamic Frames (8 OR)

Integration in time (8 BX)

Row dynamic frame definition


713/03/12

High pT threshold ( 3Gev/s) → θ = 5.7°

8 rows in the group 8● 0.11mm / 10mm = arc tangens (5.7°)

low-pT

B

row47

θhigh-pT

row14

row37

drift gap (10mm)

Col. 1 = coordinateB

high-pT

E

Col. 2

Col. 3

Col. 4

8mm

z-

1

z-

1

Pipeline (4BX deep) + OR

IN

OUTz-

1

Encounter 09.12-s159_1 (64bit) (Linux 2.6) Power Domain used: VDD Voltage: 1.4

* Primary Input Activity: 0.200000* Power Units = 1mW* Clock: clk_40 Clock Period: 0.020500 usec ----------------------------------------------------------------------------------------- Switching Leakage Total Power Power Power ----------------------------------------------------------------------------------------- 2.811mW 2.507mW 5.318mW

16 row layout and power

Uses all 8 metal layers

31

Some ideas of the Gas pixel L1 trigger organization:Status registersStatus registers

BX-9*25

BX-8*25

BX-7*25

BX-6*25

BX-5*25

BX-4*25

BX-3*25

BX-2*25

BX-25

BX

BX-9*25

BX-8*25

BX-7*25

BX-6*25

BX-5*25

BX-4*25

BX-3*25

BX-2*25

BX-25

BX

Each pixel has 8 (4) bit status registers covering250 ns. Each BX all registers shift by 25 (50) ns

Shows bit in the present BX

Shows bit in the 250 ns before BX

250 ns is a drift time

BX-9*25

BX-8*25

BX-7*25

BX-6*25

BX-5*25

BX-4*25

BX-3*25

BX-2*25

BX-25

BX

OR

OR

OR

Amp.

Analog sumAnalog sumover all the pixels over all the pixels in the columnin the column

Local Pixel RoI

Spare slides


323/11/10

Common-per-column OR cell

OR EoC logic

C load= 118fF

1 Column = 32 pixels = 440μm x 32 = 1.408cm

RC - transmission line55μm x 8 = 440μm

OR

ch

arg

ing

Pixel N

from pixel N-1

Pixel N+1

OR OR

Pixel N+2

Cin_OR = 17.6fF real OR & real RC-line

real OR & ideal RC-line

16ps

32ps

56ps

Ideal OR & real RC-line

delay = 60 ps / pixel


423/11/10

Through-column Propagation of the Common OR signal

Typical case: process corner=tt , vdd=1.5V, temp=27°C

posedge skew ≈ 2ns


523/11/10


Slow case = worst case: process corner=ssf , vdd=1.2V, temp=70°C

posedgeskew ≈ 4ns

negedgeskew ≈ 8ns


623/11/10


posedgeskew ≈ 2.6 ns

Typical case: process corner=tt , temp=27°CPower supply voltage effects


723/11/10


posedgeskew ≈ 2.2 ns

Typical case: process corner=tt , vdd=1.5VTemperature effects


823/11/10


12 ● 10-12A ● sec● hit -1 ● 50 000 hit ● sec-1 ● column-1 ● 1.5V = 1 µW ●

column-1

Typical case: process corner=tt , vdd=1.5V, temp=27C

Power consumption

Power = 256 µW / chip

Documents

Radius-wise track identification