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DS629 August 8, 2007 www.xilinx.com 1Product Specification

2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respectiveowners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinxmakes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expresslydisclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claimsof infringement and any implied warranties of merchantability or fitness for a part icular purpose.

Introduction

The 3GPP RACH Preamble Detector core provides anoptimal solution for implementing RACH detection in

a 3GPP uplink. The core includes all of the logic

required for scramble-code generation, correlation and

preamble detection. The RACH Preamble Detector

combines an optimal core and a flexible wrapper

design, allowing custom implementation of detection

algorithms and easy integration with a DSP or micro-

processor.

Features

Device families supported: Virtex-4, Virtex-5,Spartan-3A DSP

Scalable solution for femto-cells up to macro-cells

Algorithm Features

- Compact, scalable correlation unit

- Streamed correlation calculations, allowing

minimal hardware use for femto and pico

applications

- Coherent and non-coherent result generation in

parallel with correlation.

- Sorted and filtered PDP results

Design scales with following parameters to

minimize resource utilization, based on:

- Search window size

- Coherent accumulation window size

- Number of antenna

- Oversample rate

- Quantization

Easy integration to microprocessor/DSP viaOCP-compatible interfaces

- Pipelined read of RACH results for improved

performance

For use with Xilinx CORE Generator software

v9.2i or later

System Overview

Figure 1 shows a typical use of the 3GPP RACHPreamble Detector core. The core is designed to act as a

co-processor attached to a microprocessor or DSP

across a system bus. The open core protocol (OCP)

interfaces allow easy adaptation to other bus protocols.

During operation, the RACH runs on every antenna on

every slot. The processor can configure the RACH core

over the OCP-compatible bus to determine the size of

the cell being processed and the nature of the algorithm

used to combine the RACH correlation data to form a

decision. The antenna data stream can come directly

from a radio interface, but could also be streamed via

DMA across the system bus.

At the end of each slot, the RACH core produces a

power delay profile (PDP) for each of the possible

RACH preambles. These PDPs can then be read by the

DSP. The core also produces an AICH recommendation

based on the PDPs. This recommendation can be used

by the processor, or it can interpret the PDPs to form its

own decision. The PDPs are also required to initialize

the searcher (see the 3GPP Searcher v1.0 data sheet,

DS628).

0

3GPP RACH PreambleDetector v1.0

DS629 August 8, 2007 0 0 Product Specification

Figure Top x-ref1

Figure 1: Typical Application

Antenna

Data

DSP Processor

System Bus

3GPP RACH

Core

RACHConfigurations

RACHResults

xmp002_01_062007
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3GPP RACH Preamble Detector v1.0

2 www.xilinx.com DS629 August 8, 2007Product Specification

Background

RACH Detection

The 3GPP RACH Preamble Detector is used to detect a RACH preamble transmission from user

equipment (UE). The RACH transmission from the UE is one of 16 possible preambles, consisting of

256 repetitions of one of the Hadamard code sequences listed in Table 1.

Each preamble of 4096 chips long is transmitted from the UE after scrambling, using the scrambling

code assigned to the PRACH channel. The base station (BS) receives the antenna data, where it is

descrambled by the RACH preamble detector and correlated against the preamble sequences.

Detection is achieved when a peak is found in the correlation results exceeding a detection threshold.

Figure 2 illustrates a simple radio channel environment. In this environment, the received RACH

preamble is offset by the channel delays associated with each path. The offset is determined by theround trip time from the BS to the UE. Figure 3shows the effect of path delays on the transmitted

preamble. When a signal appears at the BS, it is delayed relative to the start of the slot by a delay equal

to twice the path delay to the UE. In the RACH, the amount of this delay becomes the search window.

To correlate for the full RACH preamble, the RACH has to perform a correlation over 4096 samples,

beginning at every sample within the search window, and compare the result against the 16 possible

preamble sequences. The RACH preamble detection is, therefore, performed over a period of the search

window + 4096 chips.

Table 1: Hadamard Code

PreambleSignature

Value of n

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

P0(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P1(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P2(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P3(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P4(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P5(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P6(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P7(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P8(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P9(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P10(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P11(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P12(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P13(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P14(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P15(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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According to the 3GPP W-CDMA specification, section 6 of the 3GPP specification TS25.214 V6.11.0

Physical Layer Procedures (FDD) (Release 6)), the RACH must respond to a detected preamble with an

AICH response. Failure to receive a response causes the UE to increase its transmission power and

resend the RACH preamble.

Figure Top x-ref2

Figure 2: Simple Radio Channel Environment

Figure Top x-ref 3

Figure 3: Transmitted Preamble Delay

BS

UE

Path1

Path4

Path2

Path

3

ds629_02_062107

Path Delay

Search Window

ds629_03_062707

TransmittedSequence at

Chip Rate

ReceviedDataat

Sample Rate

1.5 AccessSlots= 7680 Chips

1 AccessSlot = 5120 Chips

4096 Chips

(4096 + Window) Chips

Path Delay

AICHResponse Time

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The received RACH preamble is generally subjected to multipath delays and has multiple correlation

peaks in the received stream (Figure 4), producing a power delay profile (PDP). The RACH has to

identify each of these individual peaks and pass the power and delay information associated with each

to the Searcher, providing the Searcher with an initial estimate of the channel in which it is trying to

track transmitted data.

System Operation

Overview

The RACH consists of two parts: a RACH core, available through CORE Generator software, and a

reference design incorporating the RACH core into a post-processing algorithm for the correlation

results produced by the core. The RACH reference design is delivered as VHDL source code along with

the RACH core.

The RACH 's overall structure is illustrated in Figure 5, showing the VHDL source files comprising the

reference design, and the RACH core generated by the CORE Generator software.

The RACH core performs the correlations operation on the received antenna data. The core is designed

to process these correlations in the most efficient manner possible.

The RACH reference designs role is to reduce the load on the DSP by filtering and sorting the results

from the core. The reference design is also responsible for calculating the non-coherent and coherent

power in the RACH correlation results. Furthermore, the reference design produces an AICH recom-

mendation for the processor to use in determining the next AICH signal to send.

The further role of the RACH reference design is to act as a bridge between the RACH core and the DSP.

Therefore, the reference design uses OCP-compatible interfaces for connecting with the system bus.

The user can edit the reference design source code to change the system bus the RACH uses to connect

to the DSP. It is also possible to change the AICH decision algorithm and allow the possibility of imple-

menting a proprietary selection algorithm.

Figure Top x-ref4

Figure 4: Simple Radio Channel Power Delay Profile

Delay

Power

Path 1

Path 2

Path 3

Path 4

Window Delay Search Window

ds629_04_062107

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RACH Reference DesignThe RACH reference design is supplied as unencrypted VHDL files, allowing the user to implement

proprietary versions of the RACH detection algorithm. The supplies, standard reference design takes

the raw correlation results from the RACH core and compares them to a finger threshold to determine

if the correlation peak is large enough to be considered as a matching finger. Matching fingers are then

sorted on a per preamble basis, along with the offset associated with them.

The sorted fingers are then combined to generate a figure for the total power contained in each

preamble. This power estimate is then compared to an AICH detection threshold to determine if the

preamble contains enough power to be considered as being a detected preamble. Detected preambles

are then indicated to the DSP. The DSP also has access to the nlargest fingers for each preamble via the

OCP RACH Result (RR) interface. This access allows the processor to accessthe size of each finger and

its offset. The offset can then be used to set up the searcher.

Figure Top x-ref5

Figure 5: RACH Inner and Outer Core Structure

rach_3gpp_config

_regs.vhd

rach_3gpp_ocp

_result_rd.vhd

rach_3gpp_sorter.vhd

rach_3gpp_preamble_sort.vhd

rach_3gpp_non_coh_add.vhd

rach_3gpp_non_coh_ram.vhd

Bypass ifc_min_coh_win_len = 256

RACH PreambleDetector Core

RACH

Config

Interface

AntennaInterface

RACH

Result

Interface

ds629_05_072607

rach_3gpp

_aich.vhdAICHrecommendation

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The VHDL blocks provided for the reference design are listed in Table 2and shown in Figure 5.

The interface to the RACH reference design is shown in Figure 6. Connection to the reference design is

achieved using OCP-compatible interfaces. The reference VHDL can be edited to implement alter-

native bus architectures.

When the RACH reference design is generated via CORE Generator software, the parameters which

apply to the reference design are created as a package of constants and are included in the reference

design. Adjusting the parameters requires the core to be regenerated.

Port Descriptions

The 3GPP RACH Preamble Detector is designed to be used as co-processor to a general purpose

processor or DSP. OCP-compatible interfaces are used to provide a consistent interface adaptable to

many system bus types (refer to Register and Memory Mapsfor details on data transferred across the

OCP data and address signals).

Table 2: Reference Design Blocks

Block Description

rach_3gpp_ref_v1_0_main.vhd Top-level reference design.

rach_3gpp_sorter.vhd Implements the sorting of all of the results from the RACH core.

rach_3gpp_preamble_sort.vhd

Performs RACH result sorting for each preamble. One instance is used

per preamble. This block is instantiated from within

rach_3gpp_sorter.vhd.

rach_3gpp_non_coh_add.vhd:

Implements non-coherent accumulation of the coherent sub-windows

generated by the RACH core. If the RACH core is selected without

non-coherent accumulation enabled, this block is not necessary. This

block incorporates the I2+ Q2calculation.

rach_3gpp_non_coh_ram.vhdRAM required to store the partial non-coherent results during

non-coherent accumulation.

rach_3gpp_power_calc.vhd Performs the I2+ Q2calculation for the power calculation.

rach_3gpp_aich.vhd Implements the AICH recommendation.

rach_3gpp_ocp_result_rd.vhd Decodes the OCP reads of the RACH results.

rach_3gpp_config_regs.vhd Decodes the OCP writes of the RACH configuration registers

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Port Diagrams

Figure 6shows the top-level interface to the reference design (fields within the OCP port are shown in

brackets).

Port Descriptions and Definitions

Clocks and Reset

Table 3lists the clock and reset for the 3GPP RACH Preamble Detector core.

Figure Top x-ref6

Figure 6: 3GPP RACH Preamble Detector Reference Ports

Table 3: Clock and Reset(1)

Port Name I/O Width Description

CLK I 1 Chip Rate Processing Clock.Used to synchronize all

OCP-compatible interfaces

CE I 1 Clock Enable (optional). Clock Enable halts all internal

clocks when asserted.(2)

RESET I 1 Reset Active High Synchronous Reset.(3)

Notes:

1. Clock and Reset is common to all blocks.2. CE is not defined in OCP specification. Asserting CE during OCP accesses could lead to the block notcomplying with OCP specification.

3. OCP reset is specified as being active Low. Active High reset is adopted to be compatible with other LogiCOREmodules. Place an inverter before reset if using OCP reset signal.

ds629_06_072407

CLK

CE

MRESET

RC_MCMD

RC_MADDR

RC_MDATA

RC_SCMDACCEPT

RC_SINTERRUPT

A_MCMD

A_MDATA

A_MDATAINFO

A_SCMDACCEPT

A_SINTERRUPT

3GPP

RACH

Preamble

Detector

Reference

Design

RR_MCMD

RR_MADDR

RR_SDATA

RR_SDATAINFO

RR_SRESP

RR_SCMDACCEPT

RR_SINTERRUPT

HostConfiguration

OCP

Interface

AntennaInterfa

ce

HostResult

OCP

Interface

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RACH Configuration Interface

The core OCP interface port definitions are listed Table 4.

Antenna Data Interface

Table 5defines the antenna data OCP interface ports for the core.

Table 4: RACH Configuration OCP Interface Ports(1)


RC_MCMD I 3 OCP Master Command.Only supports the followingcommands:

0xb000: Idle

0xb001: Write

RC_ADDR I 4 OCP Master Address.(2)

RC_MDATA I 32 OCP Master Data.(2)

RC_SCMDACCEPT O 1 OCP Slave Command Accept.Indicates Slave has accept

command from master.

RC_SINTERRUPT O 2 OCP Slave Interrupt.Bit 0 indicates that core is ready for

another configuration to be written.

Notes:

1. OCP Interface for writing RACH configuration registers.

2. See "Antenna Interface Register Map" on page 15.

Table 5: Antenna Data OCP Interface Ports(1)


A_MCMD I 1 OCP Master Command.Only supports the following

commands:

0xb000: Idle

0xb001: Write

A_MDATA I 16 Antenna Data. Consists of I/Q data components.(2)

A_MDATAINFO I 1 OCP Master Data Info.Bit 0 is set when sample data is

synchronized to global sync signal. Only set for data on

antenna 0.

A_SCMDACCEPT O 1 OCP Slave Command Accept. Indicates Slave has accept

command from master.

A_SINTERRUPT O 1 OCP Slave Interrupt.Indicates that slave is expecting

sample synchronized to global sync signal. Cleared when

data written with A_MDATAINFO[0] is set.

Notes:

1. Antenna data is time-interleaved on the interface.2. See "Antenna Interface Register Map" on page 15.

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RACH Results Interface

Table 6defines the RACH results OCP interface ports.

RACH Core

Internal to the RACH Preamble Detector is the RACH core. The RACH is a CORE Generator core

implementing the scrambling-code generation, correlation, and preamble detection. This core is config-

urable using a subset of the parameters listed in Generation and Customization. Variation of the

parameters controls the size of the search window that the core is designed to process and the numberof sub-windows which the correlation can be broken down into, allowing for non-coherent accumu-

lation across the window (see Coherent and Non-Coherent Processing for details on non-coherent

processing). Changes to this core can only be achieved by adjusting the parameters in the CORE

Generator GUI.

The architecture of this core is based on a fully streamed correlation of the incoming antenna data. This

architecture is ideally suited to femto- and pico-cell RACH implementations, as it minimizes the

amount of hardware resources required to perform the RACH detection.

Preamble detection is achieved using a fully streamed fast-Hadamard transform (FHT). The FHT is the

optimal method of decoding the RACH correlation into the original RACH preambles. To enable

non-coherent accumulation, the FHT can access the correlation results throughout the correlation

window. Thus, a set of preamble results can be produced for a sub-window. These correlation results

can be accumulated externally to the core to produce a non-coherent accumulation. This non-coherent

accumulation takes place within the reference design.

The RACH core is based on an implementation for a single antenna with an oversample rate of two

samples per chip. This combination provides the optimal use of hardware within the core. To achieve

higher oversample rates and additional antennas, multiple instances of the RACH core are instantiated

Table 6: RACH Results OCP Interface Ports


RR_MCMD I 3

OCP Master Command.Valid commands are:0b000: Idle

0b010: Read

RR_MADDR I 23 OCP Master Address.(1)

RR_SDATA O 18 OCP Data.(1)

RR_SDATAINFO O 1 OCP Data Information.Bit 0 indicates that saturation has

occurred.

RR_SRESP O 2 OCP Slave Response.Valid values are:

0b00: null response

0b01: data valid response

RR_SCMDACCEPT O 1 OCP Command Accept.RR_SINTERRUPT O 1 OCP Slave Interrupt.Indicates Completion of a RACH

search and results can be read from results memory. Cleared

by reading memory.

Note:

1. See "RACH Results Memory Map" on page 15.

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inside the RACH reference design. Using separate instances per antenna enables the user to alter the

algorithm used to combine the antenna results to form a RACH detection decision.

Coherent and Non-Coherent Processing

There are two modes of correlation:

Coherent

. For coherent processing, all of the repetitions of the preamble are added across the full4096 bits prior to decoding with the FHT and calculating the magnitude. Coherent processing is the

simplest method to implement since the partial result just accumulates until all the bits are seen.

Non-coherent: For non-coherent processing, the 4096-bit preamble is split into equally sized

windows (size selected by the DSP). Each of these windows is coherently summed, and the

magnitude of the results taken. These magnitudes are then summed to produce the final power

density spectrum. This method uses the same hardware as coherent detection. However, after each

coherence window is completed, the partial result stored is reset, and the FHT is applied to the

correlation results in that window. The magnitudes of each preamble produced at the end of the

window is stored and accumulated in RAM following the FHT. After all the windows are

correlated, the threshold is compared against the non-coherent results stored in the RAM.

Port Descriptions

The RACH core produced by CORE Generator software has the interface shown in Figure 7.

Knowledge of the interface is only required if the user is intending to edit the outer reference design. If

the standard RACH detection algorithm is used, the interface to this core is made via that reference

wrapper.

Core Port Diagram

Figure Top x-ref7

Figure 7: 3GPP RACH Preamble Detector Core Ports Diagram

scramble_code_init

coherence_win_len

CLK

antenna_data_I

sample_write

antenna_data_Q

sample_accept

fht_data_out_q

fht_data_out_i

fht_data_out_valid

fht_data_out_sync

last_fht_running

MRESET

CE

slot_sync

3GPP

RACH Preamble

Detector

Core

ds629_14_072407

Result Interface

Returns thecorrelation results

from the RACH

Configuration Interface

Config values driven by

registers in thereference design

Antenna Interface

I/Q Data Supplied

from the Antenna

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Core Port Names and Descriptions

Table 7: Core Port Names and Descriptions


CLK I 1 Chip Rate Processing Clock.Same as Reference Design Clock.

CE I 1 Clock Enable (optional). Clock Enable halts all internal clocks whenasserted.(2)

Sclr I 1 Reset Active High Synchronous Reset.(3)

Scramble_code_init I 25

Scramble Code initialization: Connects to the register in the

reference design configuration interface to pass the scramble code

initialization to the RACH core.

Coherence_win_len I 9

Coherence Window Length:Connects to the Coherence Window

Length register in the RACH reference design to pass the

dynamically selected coherent window length to the RACH core. The

value passed to the core is 1/16thof the value in the reference

register.

Sample_write I 1Sample Write Strobe:Indicates new antenna data samples.

Equivalent to A_mcmd in the reference design.

Antenna_data_q I 4-8Antenna Data input:Antenna sample for Q-channel. Extracted

from Antenna OCP interface in the reference interface.

Antenna_data_i I 4-8Antenna Data input:Antenna sample for I-channel. Extracted from

Antenna OCP interface in the reference interface.

Slot_sync I 1Slot Synchronization:Indicates the start of a RACH slot and

initiates RACH processing.

Sample_accept O 1

Sample Accept:Acknowledgement of antenna sample. Used to

generate the A_SCMDACCEPT signal in the reference designs

OCP interface.

Fht_data_out_valid O 1FHT Data Valid: Indicates that the RACH core is outputting a valid

PDP. The RACH core produces an unfiltered PDP.

Fht_data_out_sync O 1FHT Data Sync:Indicates that the RACH core is outputting the first

preamble result of a PDP.

Fht_data_out_q O 16-20FHT Data Q: The Q-channel output of the RACH core. I2+ Q

2

combination of the PDP is performed in the RACH reference design.

Fht_data_out_i O 16-20FHT Data I: The I-channel output of the RACH core. I2+ Q

2

combination of the PDP is performed in the RACH reference design.

Last_fht_running O 1

Last PDP Output: Indicates that the PDP being output is the final

one for the current search window. Used by the reference design

during non-coherent processing to complete non-coherent

processing.

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Generation and Customization

The 3GPP RACH Preamble Detector can be generated and parameterized through the customize

option in the CORE Generator software.

XCO Parameters

Table 8: XCO Parameters

XCO Parameter Values Description

Clock_Enable true, falsetrue = component has CE pin

false = component does not have CE pin

Oversample_Rate 1, 2, 4

Number of samples per chip in antenna data stream. The

number of samples per chip times the search window size

is restricted to a maximum of 1024.

Antennae 1 ...16

Number of Antennae. Must be smaller or equal to number

of clocks per sample, for example, Clock_Rate divided by

Oversample_Rate.

Quantization 4 8 Number of bits used to represent samples.

Maximum_Search_Window

_Size1-512

Sets the maximum number of chips over which a RACH

search can be performed. Effectively sets the operating

radius for the cell. Targeted at pico and femto applications.

Clock_Rate 32 128 Number of clock cycles available to process one chip.

Minimum_Coherent_Window

_Size

32, 64, 128, 256,

512, 1024, 2048,

4096

Sets the number of chips involved in the coherent portion

of a non-coherent summation. Selecting 4096 chips

generates a fully coherent correlator.

Number_of_Results_Per

_Preamble1-32

Selects the number of sorted peaks which are available at

the results interface for the DSP.

Power_Shift0-18

Determines the output power scaling of the RACH PDP

fingers.

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Register and Memory Maps

RACH Configuration Interface Map

The RACH core is controlled by a configuration interface. The RC_MADDR input is used to access the

configuration registers via the OCP-compatible interface. The interface register map is defined in

Table 9.

r

Table 9: RACH Configuration Register Map

Address Description

0x00RACH Search Window Length Register. Defines the dynamic length of the search

window used in the RACH.

0x04RACH Coherence Window Length Register.Defines the Length the coherent window

uses in non-coherent operation.

0x08RACH Scrambling Code Register.Configures scrambling code used in the RACH

receiver.

0x0CRACH Preamble Mask Register. Register to mask out certain Preamble results from

the AICH recommendation.

0x10AICH Threshold Register.Configures Threshold which must be passed to qualify for

recommendation for an AICH.

0x14Finger Threshold Register.Configures Threshold which must be passed to count as a

finger, and hence contribute to the AICH.

Table 10: RACH Window Length Register (RC_MADDR = 0x00)

Range Field Description

31:10 RSVD Reserved. Set to 0.

9:0 SEARCH_WIN

Search Window Length.This field dynamically controls thenumber of chips the RACH search is performed over and is

restricted to between 1 and the

Maximum_Search_Window_Size XCO parameter.

Table 11: RACH Coherence Window Length Register (RC_MADDR = 0x04)



12:0 COH_WIN

Coherence Window Length.This field dynamically controls the

number of chips combined in the coherent portion of a

non-coherent search. Valid values are 32, 64, 128, 256, 512,

1024, 2048, 4096. This value must be greater than the minimumdefined in the Minimum_Coherent_Window_Size XCO

parameter. 4096 indicates a fully coherent operation.

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Table 12: RACH Scrambling Code Register (RC_MADDR = 0x08)



24:0 SCRAM_CODE

Scrambling Code.Defines the 25-bit scrambling code

initialization value used to generate the de-scrambling codeinternally.

Table 13: RACH Preamble Mask Register (RC_MADDR = 0x0C)

range field Description


15:0 PRMBL_MSK

Preamble Mask.15-bit register defining valid preambles in the

sector. Only enabled preambles are considered for AICH

recommendation.

Table 14: RACH AICH Threshold Register (RC_ADDR = 0x10)


31:16 RSVD Reserved.Set to 0.

15:0 AICH_THRSH

AICH Threshold.Defines the power which a RACH PDP must

contain in order to be considered for an AICH recommendation.

The total power is the sum of all the fingers in the PDP. If the PDP

is larger than this threshold, the preamble is marked as detected.

Table 15: RACH Finger Threshold Register (RC_ADDR = 0x14)

range Field Description

31:16 RSVD Reserved.Set to 0.

15:0 FNGR_THRSH

FNGR Threshold.Defines the power which a finger must have

to be included in the RACH PDP. Only fingers exceeding this

threshold are included in the total power calculation to determine

AICH.

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Antenna Interface Register Map

RACH Results Memory Map

The fingers comprising the RACH PDPs generated by the core are filtered and sorted in the reference

design. The set of largest fingers are stored in the RACH result memory, where the number of fingers in

each set is determined by the XCO parameter, Number_of_Results_Per_Preamble. This memory can be

accessed via the RACH result interface, giving the processor access to the data used in forming the

AICH recommendation.

Table 16: Antenna Data (A_MDATA[15:0])


15 8 QDATAQ Component of Sample(1).Valid values are 2Quantizationto

+2Quantization-11.

7 0 IDATAI Component of Sample(1). Valid values are 2Quantizationto

+2Quantization-11.

Note:

1. I and Q antenna data is written in parallel to the RACH.

Table 17: RACH Results Address: RR_MADDR[10:0](1)

Range Field Width Description

10 7 PREAMBLE 4

RACH Preamble Identifier. Specifies

which of the 16 Preambles the results are

being requested for.

6 2 DLY 10

RACH Finger Identifier.Specifies which

Preamble finger is being requested.

Fingers are sorted in descending order,

with the largest finger appearing at

address 0x00.

1 0WORD

ALLIGNMENT2 OCP Word Alignment.Bits set to 0.

Note:

1. Address space is configured for the maximum number of fingers per preamble. Unused bits for smaller designsshould be set to 0.

Table 18: RACH Results Data: RR_MDATA[25:0](1)

Range Field Width Description

25 10 POWER 16

Power of Result Finger. Maximum value is determined by

the power-shift XCO parameter, which also determines

saturation value for power calculation.

9 0 DLY 10

Delay Offset of Result.Maximum value is

Maximum_Search_Window_Size Oversample_Rate 1

up to a maximum of 1023.

Notes:

1. Returns power and delay for each finger in a given PDP.

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Timing Diagrams

The 3GPP RACH Preamble Detector uses OCP-v2.0-compatible interfaces for each of the main inter-

faces, allowing the interfaces to be easily adapted to a variety of bus protocols.

RACH Reference Timing

The Reference design has three OCP-compatible ports. The timing diagrams for these ports are shownin Figure 8through Figure 14.

RACH Configuration Interface Timing

The RACH configuration interface is a write-only, OCP-compatible interface used to write to the RACH

control registers. These registers can be updated at any time. However, the change only takes effect at

the start of the next slot on antenna 0. The registers are written with configuration data as specified in

the register map (see "RACH Configuration Interface Map" on page 13).

Figure 8shows the timing when updating a control register value in the RACH.

Antenna Interface Timing

The antenna interface is a write-only, OCP-compatible interface. Data is written as a block starting withthe smallest number antenna, repeating every sample period (Figure 9). The signal A_SCMDACCEPT

indicates when antenna data is expected.

The timing is dependent on a number of the core parameters. The number of antennas specifies the

length of the burst transferred. The sample period is determined by the core's clock rate divided by the

oversample rate. In this example (Figure 9), the number of antennas is 4, the clock rate is 20, and the

oversample rate is 2, giving a sample period of 10 clock cycles.

Figure Top x-ref8

Figure 8: RACH Configuration Timing

Figure Top x-ref9

Figure 9: Antenna Interface Basic Transfer

IDLE WR WR WR WR WR WR WR WR IDLEIDLE IDLE

0X00 0X04 0X08 0X0C 0X00 0X04 0X08 0X0C

CLK

RC_MCMD

RC_MADDR

RC_MDATA

RC_SCMDACCEPT

ds629_07_062607

IDLE WR WR WR WR WR WR WR WR IDLEIDLE

A0 A1 A2 A3 A0 A1 A2 A3

Sample Period

CLK

A_MCMD

A_MDATA

A_SCMDACCEPTds629_08_062607

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The signalA_SCMDACCEPTforces master data transfers to synchronize to the internal processing rate of

the RACH (Figure 10). If the master writes data to the core early, then A_SCMDACCEPTis not asserted

until the cycle count reaches the correct value, thus throttling the master data transfer rate.

Figure Top x-ref11

Figure 10illustrates the case of the master throttling the core processing rate. In this case, the master

does not supply data on the expected clock cycle and the core is stalled. Because processing in the core

is stalled, additional clock cycles are required to meet the real-time processing requirement of the core.Figure 11 shows the synchronization of the core to the 3GPP framing references. The signal

A_MDATAINFOis asserted when writing the first sample of antenna 0 when the frame sync occurs. The

signalA_SINTERRUPTindicates that the core is expecting the frame synchronization onA_MDATAINFO

and occurs at the same time the core is synchronized.

Figure Top x-ref10

Figure 10: Core Throttling Master Transfer Rate

Figure Top x-ref12

Figure 11: Antenna Data Frame Synchronization

IDLE WR WRWRWR IDLE

A0 A1 A2 A3

CLK

A_MCMD

A_MDATA

A_SCMDACCEPT

ds629_09_062607

IDLE WR WR WR WR IDLE

A0 A1 A2 A3 A0 A1 A2 A3

WR WR WR WR IDLEA_MCMD

A_MDATA

A_SCMDACCEPT

A_MDATAINFO

A_SINTERRUPT

ds629_10_062607

CLK

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RACH Results Interface Timing

The RACH results interface is a pipelined read-only, OCP-compatible interface. The signal

RR_SINTERRUPTis used to indicate when a RCH detection completes and the results can be read. The

first read from the memory clears the interrupt.

The results are read for each PDP using the address specified in the memory map (see "RACH Results

Memory Map" on page 15). After issuing an OCP read command, there is a three-clock latency fromRR_SCMDACCEPTbeing asserted to the data valid as indicated via the signal RR_SRESP. See Figure 12.

RACH Core Timing

Antenna Interface Timing

The RACH core has two interfaces that the reference design wraps around. Knowledge of these inter-

faces is required when altering the RACH reference design to ensure correct data transfer data to the

core.

Each RACH core is responsible for processing a single antennas worth of data. The interface to the core

is similar to the interface for the RACH reference antenna, except that the antenna data is no longer a

block of time-multiplexed antenna data, but rather the demultiplexed data for a single antenna.

Furthermore, the write instruction has been reduced to a single bit write flag (Figure 13).

Figure Top x-ref13

Figure 12: RACH Results Timing

IDLE RD RD RD RD IDLE

A3A2A1A0

D0 D1 D2 D3

VALIDVALIDVALIDVALIDNULL NULLNULL

3 Clock Latency

CLK

RR_SINTERRUPT

RR_MCMD

RR_MADDR

RR_SCMDACCEPT

RR_SRESP

RR_SDATA

ds629_11_062607

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Figure Top x-ref15

RACH Results Interface Timing

The RACH core produces a correlation result for each of the 16 possible preambles, for every sample in

the search window, and for both I and Q data channels. This data is streamed out of the RACH(Figure 14) with results appearing for preamble 0 through preamble 15 in a burst of 16 clock cycles. The

blocks of preamble data follow the order: P0, P1, P2 ... Pn, where P0is the RACH search result starting

at sample 0,and where Pn consists of the Inresult and Qnresult.

Figure Top x-ref14

Figure 13: RACH Core Basic Antenna Data Transfer

Figure Top x-ref16

Figure 14: RACH Core Results Interface

Sample Period

CLK

SAMPLE_WRITE

ANTENNA_DATA_Q

ANTENNA_DATA_I

SLOT_SYNC

SAMPLE_ACCEPT

ds629_12_062607

P0 P1 P15 P0 P1 P15 P0 P1 P15

CLK

FHT_DATA_OUT

FHT_DATA_OUT_VALID

FHT_DATA_OUT_SYNC

FINAL_FHT_OUT

ds629_13_062607

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Performance Characteristics

Table 19through Table 21show the performance of the 3GPP RACH Preamble Detector core in terms of

resource usage and maximum achieved operating frequency for different device families. The resource

count and speed of the core can change depending on the surrounding circuitry of the user design.

Therefore, these figures should be taken only as a guide.

The tool settings to achieve these results were as follows and were obtained with ISE v9.2i tools:

map -c 1 -ol high

par -ol high

Note: Tool settings can have a significant effect on area use and speed. The Xilinx Xplorer script can beused to find the optimal settings.

Table 19: Spartan3A-DSP Engine Resource Utilization

XCO Parameter Case 1 Femto Cell Case 2 Pico Cell

Clock_Enable False False

Minimum_Coherent_Window_Size 4096 512

Maximum_Search_Window_Size 16 128

Quantization 4 4

Utilization

Xilinx device XC3SD3400A XC3SD3400A

Slices(1) 663 1193

LUTs 881 1376

FFs 772 1742

Block RAMs (18k) 1 8

DSP blocks 0 0

Maximum clock frequency(2) 155 145

Notes:

1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinximplementation tools.

2. Maximum clock frequencies are shown in MHz for -4 parts. Clock frequency does not take jitter into accountand should be de-rated by an amount appropriate to the clock source jitter specification.

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Table 20: Virtex-4 Engine Resource Utilization





Quantization 4 4

Utilization

Xilinx device XC4VLX15 XC4VLX15

Slices(1) 417 588

LUTs 507 740

FFs 608 873


DSP blocks 0 0

Maximum clock frequency(2) 283/310 266/ 310

Notes:1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinx

implementation tools.

2. Maximum clock frequencies are shown in MHz for -10/-12 parts. Clock frequency does not take jitter intoaccount and should be de-rated by an amount appropriate to the clock source jitter specification.

Table 21: Virtex-5 SP Engine Resource Utilization





Quantization 4 4

Utilization

Xilinx device XC5VLX30 XC5VLX30

LUT/FF Pairs(1) 796 1128

LUTs 532 726

FFs 610 871

Total Block RAMs(3)



DSP blocks 0 0

Maximum clock frequency(1,2) 297/310 251/ 320

Notes:

1. Area and maximum clock frequencies are provided as a guide. They may vary with new releases of the Xilinximplementation tools.

2. Maximum clock frequencies are shown in MHz for -1/-3parts. Clock frequency does not take jitter into accountand should be derated by an amount appropriate to the clock-source jitter specification.

3. Represents the total number of36k block RAMs used when map is run. In reality, two 18k block RAM primitivescan usually be packed together, giving an absolute minimum total block RAM usage of block RAMs (36k) +(block RAMs (18k) /2) (rounded up).

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Support

Xilinx provides technical support for this LogiCORE product when used as described in the product

documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in

devices that are not defined in the documentation, if customized beyond that allowed in the product

documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

Ordering Information

The 3GPP RACH Preamble Detector core is provided under the SignOnce IP Site Licenseand can begenerated using the Xilinx CORE Generator software v9.2i or higher. The CORE Generator software isshipped with Xilinx ISE Foundation Series Development software.

After purchase, the core may be downloaded from the Xilinx IP Centerfor use with the Xilinx COREGenerator software v9.2i and higher. The Xilinx CORE Generator software is bundled with the ISEFoundation software at no additional charge.

Contact your local Xilinx sales representative for pricing and availability of additional Xilinx

LogiCORE modules and software. Information about additional Xilinx LogiCORE modules is

available on the Xilinx IP Center.

Revision History

Date Version Revision

08/08/07 1.1 Initial Xilinx release
http://www.xilinx.com/ipcenter/doc/xilinx_click_core_site_license.pdfhttp://www.xilinx.com/ipcenterhttp://www.xilinx.com/company/contact.htmhttp://www.xilinx.com/ipcenterhttp://www.xilinx.com/ipcenterhttp://www.xilinx.com/company/contact.htmhttp://www.xilinx.com/ipcenterhttp://www.xilinx.com/ipcenter/doc/xilinx_click_core_site_license.pdf

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