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Metro-LAN 10 Gigabit Ethernet Switching or OC-192 Packet over SONET Switching B

Two IXP 2800 Network Processors

Top IXP 2800(Ingress Processing)

Bottom IXP 2800(Egress

Processing)

Framer

Fabric Interface Chip

DRAM buffers linked together by

linked lists maintained in SRAM

The IXP2800 supports an aggregate rate in excess of 60 million queue operations per second on one

The smallest configuration of DRAM that supports the maximum bandwidth (3 DRAM components

bytes of storage.

OC-48 (4 X OC-12 OR 16 X OC-3) SWITCHING BLADE

single IXP2800 network processor is used for both ingress and egress processing

The ingress processing is distrIXP2800 network processors

The egress processing is accomIXP2800

The entries in the SRAM rings the processing of the packet aon to the2nd ingress IXP2800

10GB/S MULTI-SERVICBLADE

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THE IXP2800 MICROARCHITECTURE

The IXP2800 and IXP2400 has 10 major internal units also has 10 major units

The Media-Switch-Fabric Interface

Transmit and receive interfaces can be separately configured

on IXP2800

SPI-4(System Packet interface) for PHY devices

CSIX-L1 protocol for switch fabric interfaces

Each IXP2800 port has 16 data sign

signal, and a parity signal , all of wh

Differential Signaling(LVDS) and are

of clock

The IXP2800 supports 10Gb/s inbou

outbound or 15Gb/s inbound and 1

The RBUF and TBUF are both RAMs and store data in sub-blocks (referred to as elements), and

are accessed by either the microengines or XScale

The IXP Chassis

The chassis is the bus system,which interconnects all the units

within the IXP.

The chassis is used to retrievedata from the outbound transferregisters and deliver data to the

inbound registers

consists of data busses, wconnect the microengi

transfer registers to the vashared resources (i.e.,SR

DRAM, hash, cryptography

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THE MICROENGINE CLUSTERS

The IXP2800 has 16 microengines,configured as two clusters of eight

identical microengines.

More communication capabilitybetween the microengine and the

rest of the chip resources.

cluster has command a

The SRAM cluster

The SRAM cluster consists of four independent SRAM controllers, each of which controls ex

Rate (QDR) SRAMs.

Sufficient control information bandwidth for 10Gb network applications.

Functions of SRAM controllers

Atomic read-modify-write operations

Linked-list queueoperations.

Ring operations.

THE IXP2XXX The DRAM

Cluster

The

CryptographyUnit

The Hash Unit

The Scratch

Unit

The PCI Unit

Registe

MultiplThread

CAM

Event Signals

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Question and Answer

1)What are the tasks of Ingress and Egress processors in OC-192 packet over SONET

A)Ingress processing tasks may include classification, metering, policing, congestion avoida

segmentation, and traffic scheduling into a switching fabric.

Egress processing tasks may include reassembly, congestion avoidance, statistics, and traff

2)What is the limitation factor for the number of queues in IXP2800

A) The number of queues that an IXP2800 supports is limited only by the available SRAM c

any on-chip resource limit

3)

A)It is a name of protocol Common Switch Interface Specification-L1 (CSIX-L1) protocol im

top of the SPI-4.2 physical signaling in IXP 2800 processor

What is a CSIX-L1?