*FinFETQin ZhangEE 66604/19/2005

*OutlineIntroductionDesign FabricationPerformanceSummary

*IntroductionDouble-gate FET (DGFET) can reduce Short Channel Effects (SCEs)Reduce Drain-Induced-Barrier-LoweringImprove Subthreshold Swing SMedici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETsE J Nowak, I Aller, T Ludwig, K Kim R V Joshi, C-T Chuang, K Bernstein and R Puri, IEEE Circuits and Dev. Magazine, p20-31, Jan/Feb 2004

*IntroductionThree Types of Double-gate FETJ Kretz, L Dreeskornfeld, J Hartwich, and W Rosner, Microelectronic Eng. 67-68, p763-768, 2003Quasi-COMS structureRelatively simple FAB

*IntroductionFirst FinFET - DELTA (DEpleted Lean-channel TrAnsistor)

D.Hisamoto, T.Kaga, Y.Kawamoto, and E.Takeda, IEEE Electron Dev. Lett., vol.11, no.1, p36-38, Jan 1990

*Design - GeometryGen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002Effective channel length Leff = Lgate + 2LextEffective channel width W = Tfin + 2HfinH -J L Gossmann, et al., IEEE Trans on Nanotechnology, vol.2, no.4, p 285-290, 2003Hfin >> TfinTop gate oxide thickness >> sidewall oxide thickness

*Design - Dependence of Vth and S Swing on Hfin Gen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002The saturation of Vth roll-off and S is observed when Hfin is increased from 20 nm to 90 nmThe critical Hfin needed for saturation is dependent on TfinFor larger Tfin, the critical Hfin is correspondingly larger

*Design - Dependence of Vth and S Swing on TfinVth roll-off and S change more and more rapidly as Tfin changing from 10 nm to 60 nm, and slow down after thatFin thickness reduce can suppress short channel effects, but the variation will change the performance of the device a lot

Gen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002

*Design - SCEs with Leff/TfinKidong Kim, et al., Japanese J of Appl. Phys., vol.43, no.6B, p3784-3789, 2004 Leff/Tfin > 1.5 is desirable

*Design - Other OptimizationNonrectangular FinHydrogen annealing to round off the corners

Source-Drain Fin-Extension DopingTradeoff regarding SCEs and S/D series resistanceDielectric Thickness ScalingThreshold Voltage ControlChannel doping with symmetric poly-Si gateAsymmetric poly-Si gateMetal gate

Xusheng Wu, IEEE Trans on Electron Dev., vol.52, no.1, p63-68, 2005Weize Xiong, et al., IEEE Electron Dev. Lett., vol.25, no.8, p541-543, 2004Vishal Trivedi, IEEE Trans on Electron Dev., vol.52, no.1, p56-62, 2005Jakub Kedzierski, et al., IEEE Trans on Electron Dev., vol.51, no.12, p2115-2120, 2004

*Fabrication6.5 nm Si fin by Berkeley Team ---- Smallest in 2002Yang-Kyu Choi et al., Solid-State Electronics 46, p1595-1601, 2002Poly-SiSi fin

*Fabrication - Spacer LithographyYang-Kyu Choi et al., Solid-State Electronics 46, p1595-1601, 2002The thickness of spacer at the sidewalls determines the fin thicknessAlternative: Electron Beam Lithography (20nm gate length and 15nm fin thickness was achieved)W Rosner, et al., Solid-State Electronics 48, p1819-1823, 2004

*Fabrication - Process FlowChenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002Easy in concept----Tough to build(a) SiN is deposited as a hard mask,SiO2 cap is used to relieve the stress.

(b) Si fin is patterned

(c) A thin sacrificial SiO2 is grown

(d) The sacrificial oxide is stripped completely to remove etch damage

(e) Gate oxide is grown

(f) Poly-Si gate is formed 10 nm gate length, 12 nm fin width

*PerformanceChenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

*Performance - IV CharacteristicsThe drive currents are 446 uA/um for n-FinFET and 356 uA/um for p-FinFET respectivelyThe peak transconductance of the p-FinFET is very high (633uS/um at 105 nm Lg), because the hole mobility in the (110) channel is enhanced Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

*Performance - Speed and LeakageGate Delay is 0.34 ps for n-FET and 0.43 ps for p-FET respectively at 10 nm Lg

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002Gate leakage current is comparable to planar FET with the same gate oxide thickness

*Performance - Short Channel EffectsChenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002The subthreshold slope is 125 mV/dec for n-FET and 101 mV/dec for p-FET respectivelyThe DIBL is 71 mV/V n-FET and 120 mV/V for p-FET respectivelyMedici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETs

*SummaryDouble-gate FET can reduce Short Channel Effects and FinFET is the leading DGFETOptimization design includes geometry, S-D fin-extension doping, dielectric thickness scaling, threshold voltage control.Fabrication of FinFET is compatible with CMOS process10 nm gate length, 12 nm fin width device has been fabricated and shows good performance

Easy in concept----Tough to build