QUESTION BANK

Digital Logic

Objective: Main Objective is to know about properties of Logic gates, positive and negative logic, basic gates and universal gates, HDL1.Define Binary operator. 022.List out different postulate used for algebric structure.

02

3.Explain the commutative & Associative law 024.Discuss the following theorems with example i) x+x=x ii) x.x=0 iii) x+1=1 iv) x.0=0 v) x+xy=x vi) x(x+y) =x

02

5.Explain Duality principle with an example. 026.Explain complement of function with an example

02

7.Define truth table 028.Why NAND & NOR gates are called universal gates

02

9.Discuss canonical & standard forms of 04

Boolean functions with an example10.Convert the following Boolean function to Sum of Minterms for F=A+B1C

04

11.Convert the following Boolean function F=xy+x1z to product of Maxterm

04

12.Bring out the difference between Canonical & Standard forms

04

13.What are logical gates,mention different types of Logic gates

04

14.Explain the operation of different Logic gates with neat diagram

04

15.Demonstrate by means of Truth table the validity of following theorem of Boolean algebrai)Associative law ii) Demorgans law for Validity iii) Distributive law

06

16.Simplify the following Boolean function to minimum no. of literalsi) xy+xy1 ii) (x+y) (x+y1) iii) xyz+x1y+xyz1

iv) y(wz1+wz)+xy v) (A+B)1 ((A1+B1)1

06

17.Reduce the Boolean Expression to required number of literal i) BC+AC1+AB+BCD ii) [(CD1) +

06

A ]1+A+CD+AB iii) [(A+C+D) (A+C+D1) (A+C1+D) (A+B1)

18.Obtain Truth table for function F=xy+xy1+y1z

06

19.Convert the following to other canonical formi) F(x,y,z) =(1,3,7) ii) F(A,B,C,D)= (0,2,6,11,13,14) iii) F(x,y,z) =(0,1,2,3,4,6,12)

06

20.Show that dual of Exclusive-OR is equal to its complement

06

21.Implement the following function F=(CD+E) (A+B’) using Nand gates only.

*05

22.Simplify the Boolean function F using don’t care conditions d, in SOP and POS form F=A’B’C + A’CD + A’BCD=A’BC’D + ACD + AB’D’

*10

23.Implement the following function with no more than 2 NOR gates. Assume both normal and complement inputs are availableF=A’B’C’+ AB’D + A’B’CD’D=ABC+AB’D’

*10

24.Simplify the following and then complement using logic gates AB+ A(B+C)+B(B+C) [ AB’ ( C+BD) + A’B’] C

*08

25.Realize using NAND and NOR gates onlyAB’C + A’BC’ + ABXYZ + XY’Z + X’Y’

*08

26.Prove the following using Boolean identities A+A’B = A+B( A + B ) ( A + B’ ) ( A’ + C ) =AC

*05

27.Simplify the following Boolean expression using NAND gates only.A’B’C’ + A’B’C’ + B’C’( A + B’ + C ) ( A’ + B’ + C’ ) ( A’ + B )

*10

28. What are Universal gates ? Realize NOT, OR, AND functions using Universal Gates.

*06

29.Mention two categories of Boolean expressions based on their structure. Write these forms for any three variable expression T ( x,y,z ).

*08

30.Using algebraic procedure realize the Boolean expression

*06

F(w,x,y,z) = w z + w z ( x + y )31.Determine the Minterm canonical formula of the following: T ( x,y,z ) = x y + z + x y z

*04

32.Prove the Demorgan’s law x+y = x . y using Boolean postulates and theorems. *06

33.Implement the given Boolean function using NAND gate (A+B1)(CD+E). 08

34.Implement the given Boolean function using NOR gate A(B+CD)+BC1 08

35.Obtain the minimal sum for the following Boolean functionF(w,x,y,z) =m(0,1,3,5,7,9,11,14) + d(2, 8 , 10, 12)

*08

36.Simplify the Boolean function F using the don’t care conditions d, in 1. SOP 2. POSF= A’B’C’ + A’CD + A’BCD = ABC + AB’D’

*10

37.Implement the following function with no more than two NOR gates. Assume that both normal and complement inputs are available.F= A’B’C’+AB’D+A’B’CD’

*10

D=ABC + AB’D’38.Using graphical procedure , obtain a nor-gate realization of the Boolean expressionF(w,x,y,z) = w’z + wz’( x + y’)

*06

39.Prove that if w’x+yz’=0 thenWx+y’(w’+z’)= wx +xz +w’z’+w’y’z *06

40.Prove the following laws using Boolean expressionXy+yz+x’z=xy+x’z(x+y)(y+z)x’+z) = (x+y)(x’+z)

41.Implement the following function with no more than two nor gates. Assume that both normal and complement inputs are available.F=A’B’C’+AB’D+A’B’CD’ d=ABC+AB’D’

10

42.Implement a full subtractor with two half subtractors and an OR gate 10

43.Prove the following consensus laws using Boolean postulates

i) xy+yz+x’z = xy+x’zii) (x+y)(y+z)(x’+z) = (x+y)(x’+z)

4

44.Prove that if w’x+yz’ = 0 then 6

Wx+y’(w’+z’) = wx+xz+x’z’+w’y’z45.Mention the different methods available for manipulating Boolean formulas. Explain any three in detail

10

46.Using graphical procedure, obtain a nor-gate realization of the Boolean expression f(w,x,y,z) = w’z+wz’(x+y’)

6

47.Show that A B C D =∑m(0,3,5,6,9,10,12,15) 4

48.Write short notes on: Implies and subsumes 549.State and explain with examples shannon’s expansion and reduction theorems in Boolean algebra

4

50.Simplify the following using Boolean theorems:

i) f(x,y,z)=(x+y)[(x’(y’+z’)]’ + (xy)’ +(xz)’

ii) f(A,B,C) = (A+B+C)(A’+B+C)(A’+B+C’)

8

51.Transform each of the following canonical expressions into other canonical form in decimal notation and express in simplified form in decimal notation

8

i) f(x,y,z)= =m(0,1,3,4,6,7)ii) F(w,x,y,z) = ΠM(0,1,2,3,4,6,12)

52.What is don’t care condition? What are its advantages? 4

53.Obtain a NOR-gate realization of the Boolean function

i) f(w,x,y,z) =m(0,3,5,6,9,10,12,15)

8

54.Obtain a NAND-gate realization of the Boolean functionf(A,B,C) = (A+B’+C)(A’+B’+C’)(A’+B)

8

55.Explain the importance of enable input signal 6

56.Design and implement full subtractor using NAND gates only 10

57.What is high speed adder? Design and explain 2 bit carry lookahead adder 8

COMBINATIONAL LOGIC CIRCUITS

Objective: In this chapter we learn about different methods of simplifying Boolean

functions, Postulates of theorems & Boolean algebra. The laws such as commutative,Associative law,Identity,Inverse & Distributive Laws will be known. Canonical & standard forms of Boolean functions will be known. Advantage Of using K-map method for 2,3 & 4 variables, Quine McCluskey method by Determining Prime implicants (Tabulation method) . Simplification of Product of sums, Simplification of Boolean function which includes don’t care conditions .

1.Given the function T (w,x,y,z) = m(1,3,4,5,7,8,9,11,14,15). Use K-Map to determine the set of the prime implicants. Indicate the essential prime implicants. Find three distinct minimal expressions for T.

*08

2.Determine the set of prime implicants for the given function:-F(v,w,x,y,z) =m(13,15,17,18,19,20,21,23,25,27,29,

*16

31)+ Ф (1,2,12,24) and obtain the minimal expression.

3.Mention one advantage and one disadvantage of the Quine-McCluskey method for obtaining the prime implicants of a given Boolean function. Obtain all the prime implicants of the function.F(v,w,x,y,z) = m(4,5,9,11,12,14,15,27,30) + dc(1,7,25,26,31)Use Quine McCluskey method. Do you have any Essential Prime Implicants.

*12

4.Mention different methods of simplifying Boolean functions

02

5.Discuss K-map & Quine McCluskey methods for simplification of Boolean expressions

02

6.Discuss K-map & Quine McCluskey methods

02

7.Write advantages of K-map over Quine McCluskey method

02

8.Define term Don’t care condition 0

29.Explain K-map representation in detail

& discuss the merits & demerits *06

10.Explain the tabulation procedure in detail & discuss merits & demerits

*06

11.Compare K-map & Quine-Mcclusky methods for simplification of Boolean Expression

*06

12.Obtain the simplified expression in sum of products for the following:i) F(A,B,C,D,E) =

(0,1,4,5,16,17,21,25,29)ii) BDE+B1C1D+CDE+A1B1CE+A1B1C

+B1C1D1E1

iii) F(x,y,z)= x1z + w1xy1+w(x1y+xy1)

06

13.Obtain simplified expression in SOP & POS form i) x1z1+y1z1+yz1+xyz ii)

w1yz1+vw1z1+vw1x+v1wz+v1w1y1z1

and draw gate implementation using AND & OR gates

06

14.Using K-map simplify following Boolean expression & give implementation of same usingi) NAND gates only ii) AND,OR & Invert gates for F(A,B,C,D) =(2,4,8,16,31)+ D(0,3,9,12,15,18)

10

15.Using K-map obtain Simplified expression in SOP & POS form of functionF(A,B,C,D)=(A1+B1+C1+D1) (A1+B1+C+D1) (A+B1+C+D1) (A+B+C+D1)(A+B+C+D)

10

16.Simplify Boolean function using don’t care condition for SOP & POSi) F=w1(x1y+x1y1+xyz)+x1z1(Y+w),

d=w1x(y1z+yz1)+wyzii) F=ACE+A1CD1E1+A1C1DE, d=

DE1+A1D1E+AD1E1

10

17.Simplify the following Boolean function using K-map methodi) xy+x1y1z1+x1yz1 ii) x1yz+xy1z+xyz+xyz1

14

iii) F=A1C+A1B+AB1C+BCiv) f (w,x,y,z)=

(0,1,2,4,5,6,8,9,12,13,14)18.Simplify Boolean function by

Tabulation method i) F(A,B,C,D,E,F,G)= (20,28,52,60)ii) F(A,B,C,D,E,F,G)=

(20,28,38,39,52,60,102,103,127)

14

19. Give two simplified irredundant expression for F(w,x,y,z)= (0,4,5,7,8,9,13,15)

*14

20. Determine set of Prime implicants for function F(w,x,y,z)= (0,1,2,5,7,8,9,10,13,15)

*14

21.Implement following function with NAND & NOR gates.use only four gatesF=w1xz+w1yz+x1yz1+wxy1z, d=wxy+wyz

14

22.Minimize the following function with don’t care terms using Q.M. methodi) f(A,B,C,D)=

m(5,7,11,12,27,29)+d(14,20,21,22,

14

23)ii) f(A,B,C,D)=

m(1,4,6,9,14,17,22,27,28,)+d(12,15,20,30,31)

23.Implement the following function using NAND gates f(X,Y,Z)= (0,6)

14

24.Implement the following function using NOR gates F(x+y1) (x1+y)z1

14

25. Explain the Tabulation procedure in detail & discuss the merits & demerits

*14

26.Determine the set of Prime implicants for function F(w,x,y,z)= (0,1,2,5,7,8,9,10,13,15)

*14

27.Find the minimal two level NOR realization for each following functioni) f(A,B,C)= m(1,4,6,8)ii) f(A,B,C,D,E)=

m(3,5,7,12,23,27,28,30)

14

28.Find the minimal two level NAND realization for each following functioniii) f(A,B,C)= m(0,2,3,7)iv) f(A,B,C,D,E)=

14

m(4,5,6,7,25,27,29,31)29.Expand the following function into

canonical SOP form f( x1,x2,x3 ) = x1 x3 + x2 x3 + x1 x2 x3

06

30.Expand the following function into canonical POS form F( W, X, Q) = ( Q+W’ ) ( X+Q’)

06

31.With K-map obtain simplified expression in SOP F (A,B,C,D) = Σ(7,99,10,11,12,13,14,15)

*08

32.Simplify the following Boolean function using the tabulation methodF(A,B,C,D)= Σ( 0,1,2,8,10,11,14,15)

*12

33.Determine the minimal SOP using the tabulation method using only one decimal notationF(A,B,C,D,E) = Σm(13,15,17,18,19,20,21,23,25,27,29,31)+ Σd(1,2,12,24)

*10

34.Implement using K-map F(A,B,C,D) =

*1

Σm(0,2,4,6,8,16,18,20,22,24,26,28,30+ΣØ(3,7,11,15,19,23,27,31)

0

35.Using K-map obtain the minimal SOP and the minimal POS form of the function f(a, b, c, d) = Σm(1,2,3,5,6,7,8,13)

*08

36.What code is used to label the row headings and the column headings of a K-map and why?

*04

37.Mention one advantage and one disadvantage of the Quine-McClusky method for obtaining the prime implicants of a given Boolean function. Obtain all the prime implicants of the function.F(v,w,x,y,z) = Σm(4,5,9,11,12,14,15,27,30)+dc(1,17,25,26,31)Use Quine Mc Clusky method. Do you have any essential prime implicants.

*12

38.Using K-map simplify the following Boolean expression and give implementation of the same using the

*10

Nand gates only(SOP form) and Nor gates only(POS form).F(A,B,C,D) = Σ (0,1,2,4,5,12,14)+ d(8,10)

39.Explain the procedure for loading a K map using MEV technique. Write the MEV K Map for the Boolean functionF(w,x,y,z) = Σm(2,9,10,11,13,14,15)

*10

40.Using K-Maps, determine the minimal sums and the minimal products forF(w,x,y,z) = пM(1,4,5,6,11,12,13,14,15)Is the answer unique?

*08

41.Explain the grouping and simplification process in K map using 3-variable and 4 variable map

*06

42.Using K-map method simplify following Boolean expression and give implementation of the same by using NAND and NOR gates only.

(i) The SOP form -

*10

F(a,b,c,d)= Σ (0,1,4,5,6,8,14,12)

(ii) The POS expression is given by

F(a,b,c,d)= π(2,3,6, 7,9,11,15) 43.Minimize the following using K-maps:-

(iii) The SOP expression is given by: -

F(a,b,c,d)= Σ m(0,1,2,3,5,9,14,15)+ΣΦ (4,8,11,12)

(iv)The POS expression is given by

F(a,b,c,d)= πM(0,1,5,8,9,10)Implement the minimal expressions thus obtained using basic gates(both normal and inverted inputs can be used)

*14

44.List the differences between combinational and sequential logic circuits.

*04

45.Determine the set of prime implicates *

for the given functionF(v,w,x,y,z)= Σ m(13,15,17,18,19,20,21,23,25,27,29,31) + ΣΦ (1,2,12,4) and obtain minimal expression

16

46.Simplify the given function by tabulation method and list the prime implicants. Use decimal notationF(A,B,C,D)= Σm(0,1,4,5,8,10,11,12,14) + d(2,6)

*10

47.Obtain the minimal sum for the following Boolean function using Tabulation methodF(a,b,c,d,e)= Σm(0,1,3,4,7,9,10,12,15,16,17,20,23,25,28,29,30,31)

*14

48.Using K-map, obtain simplified expression in sum of productsF(A, B, C, D)= Σ(7,9,10,11,12,13,14,15)

*08

49.Simplify the following Boolean function by tabulation methodF(A, B, C, D)= Σ(0,1,2,8,10,11,14,15)

*!2

50.Using K-map obtain the minimal sum and the minimal Product for the function f(a, b, c, d) = Σm(0,1,3,7,8,12) + dc(5,10,13,14) is your answer unique?

*10

51.Using quine Mccluskey method and prime implicant table reductions, determine the minimal sums for the incomplete Boolean functionf(v,w,x,y,z)= Σm(4,5,9,11,12,14,15,27,30) + dc(1,17,25,26,31)

10

52.Explain the procedure for loading a k-map using map entered variable technique. Write the map entered variable K-map for the Boolean function f(w,x,y,z)= Σm(2,9,10,13,14,15)

10

53.Determine minimal SOP expression for f(w,x,y,z)= Σm(0,2,4,9,12,15)+ Σd(1,5,7,10)

8

54.Using quine Mccluskey method and prime implicant table reductions, determine the minimal POS expression for the following using decimal notation

8

f(v,w,x,y,z)= Σm(1,2,3,5,9,12,14,15) + dc(4,8,11)

55.Reduce the given switching function using variable map techniqueF(A, B, C, D)= Σm(0,1,4,7,10,14)

4

56.Obtain minimal sum for the following boolean function using tabulation method f(a,b,c,d,e)=m(0,1,3,4,7,9,10,12,15,16,17,20,23,25,28,29,30,31)

14

Data-Processing Circuits Objective: To study about multiplexers, demultiplexers, decoders, encoders, ROM, PLA , PAL, PL. Also this chapter deals with how errors can be detected and corrected while transferring as well as receiving data. Also HDL implementation of the above circuits1.Discuss enable control inputs. 04

2.Explain the code conversion procedure.

04

3.Define parity generator and parity checker.

06

4.Give the main steps for designing combinational circuits.

06

5.Mention the limitations of designing logic circuit in practical design method

06

6.Explain code conversion , give Boolean function for converting BCD TO EXCESS-3 converterGive the logic diagram for the same.

06

7.Discuss about the analysis procedure for designing logic circuit.

06

8.Mention the steps to obtain output Boolean function, truth table from the logic diagram.

06

9.Discuss odd & even parity generation, checking with an example.

06

10.Give the logic diagram for 3-bit odd parity generator & checking.

06

11.Design BCD to 7 segment decoder using NAND gates only

06

12.Design combinational circuit to check for even parity of four bits. A logic 1 output is required when four bits do not constitute an even parity.

08

13.Using decoder implement the following Logic functions.i) Active High decoder with OR

gate.ii) Active Low decoder with NAND

gate.iii) Active High decoder with NOR

gate.iv) Active Low decoder with AND

gate.

10

14.Design 2-4 decoder with enable input E.

10

15.Design 3-8 decoder 1016.Design 4-16 decoder 1017.Mention the application of decoder. 1018.Design a code converter that converts

4-bit number from Grey code to binarycode.

10

19.Given 3x8 decoder , show that *05

construction of 4x16 decoder20.Give the truth table for half adder and

full adder, develop the simplified expression for sum & carry of a full adder & realize the full adder using only half adder

*10

21. Design a EXCESS-3 code to BCD code using NAND gates only.

*10

22. Design a full adder & full subtractor ,give their truth table,simplified expression and circuit diagrams

*20

23. What is decoder,what are it’s advantages.Design a decimal decoder which converts information From BCD to DECIMAL.

*20

24.With a neat diagram explain the internal logic construction of a 32X4 ROM

*10

25.List the PLA table for the BCD to Excess-3 Code converter.

*10

26.Explain the 4-bit parallel adder with *10

the carry look ahead scheme. Clearly indicate how this scheme improves the performance of the operation.

27.Write short notes on Binary Full Subtractor.

*05

28.Implement a full adder circuit with a decoder and two OR gates

*05

29.Design a circuit that compares two 4-bit numbers A and B, to check if they are equal. The circuit has one output x, so that x=1 if A=B and x=0 if A ≠ B.

*05

30.How does the architecture of PAL differ from ROM.

*10

31.What are the steps involved in design, programming and testing of the PLD

10

32.Implement the following Boolean expression using a PROM.F1( x2,x1,x0) = Σm(0,1,2,5,7)F2(x2,x1,x0) = Σm(1,2,4,6)

*06

33.Mention the different types of ROM and explain each of them.

10

34.With the help of block diagrams *04

distinguish between a decoder and encoder.

35.Give a 4-to-1 MUX implementation of the three variable function.F = Σm(1,4,5,7)

*06

36.Illustrate how a PLA can be used for the combinational logic design with reference to the functions F1(a,b,c) = Σm(0,1,3,4)F2(a,b,c) = Σm(1,2,3,4,5)Realize the same assuming that a 3X4X2 PLA is available.

*10

37.Implement the Boolean expressions.F1(x2,x1,x0) = Σm(1,2,4,5) and f2(x2,x1,x0) = Σm(1,5,7) with a decoder and two OR gates.

*06

38.Implement the Boolean function f(w,x,y,z) = Σm(0,1,5,6,7,9,12,15) using 8-to-1 multiplexer.

*06

39.Write short notes on Programmable Read Only Memories (PROMS)

*05

40.Implement the following Boolean function with a multiplexer.

*08

F(a,b,c,d) = Σm(0,1,3,4,8,9,15)41.Implement the following Boolean

expression using a PROM.F1(x2,x1,x0) = Σ m(0,1,2,5,7)F2(x2,x1,x0) = Σ m(1,2,4,6)

*06

42.Give a detailed short notes on PLAs *0543.Implement the following function,

with an 8X1 Mux, with A,B and D connected to selection lines S2, S1 and S0 respectively.F(A,B,C,D) = Σ(0,1,3,4,8,9,15)

*10

44.Design 8-bit magnitude comparator using 4-bit magnitude comparator(7485)

*06

45.What is an encoder? Explain an 8-to-3 line encoder

4

46.What is a PLA? Describe with a logic diagram the the principle of operation of a PLA. What are its advantages?

8

47.Implement the following function, with an 8X1 Mux,F(A,B,C,D) =A’BD’+ACD+B’CD+A’C’D

6

48.Design 8-bit magnitude comparator using 4-bit magnitude comparator

6

49.What is an encoder? Explain an 8-to-3 line encoder.

4

Arithmetic circuits

Objective: To learn about full adder, half adder, half and full subtractor , binary addition , subtraction, multiplication and division. Also HDL implementation of the above circuits1 Discuss the full adder with an

example.04

2 Discuss the Half adder with an example.

04

3 Explain the code conversion procedure.

04

4 Define full adder & half adder, explain the working of it with an example.

06

5 Mention the difference between full 06

and half adder.6 Implement the full subtractor with

two half adder and OR gate08

7 Design a combinational circuit that converts 4-bit reflected code number to a four bit binary number,implement the circuit with EX-OR gates.

10

8 Design 2-bit adder circuit using two level NAND gate circuit for each output. the inputs are 2- bit binary number’s a1a0 & b1b0,the output’s are the 2-bit binary sum s1s0 & carry output c1 only.

10

9 Using only half adder , draw a circuit that will add 3-bits xi, yi and zi

together, producing carry & sum bits Si, Ci as shown in following table:

10

10 Give the truth table for half adder and full adder, develop the simplified expression for sum & carry of a full adder & realize the full adder using only half adder

*10

11 Design a full adder & full subtractor ,give their truth table,simplified expression and circuit diagrams

*20

12 Explain the 4-bit parallel adder with the carry look ahead scheme. Clearly indicate how this scheme improves

*10

xi yi zi Ci Si

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

the performance of the operation.13 Write short notes on Binary Full

Subtractor.*05

14 Implement a full adder circuit with a decoder and two OR gates

*05

15 Implement a Full subtractor with two half subtractor and an OR gate.

*10

16 Implement a full adder circuit with a decoder and two OR gates.

*05

17 Explain a 4-bit parallel adder with carry lookahead scheme.

10

18 Implement a full adder circuit with a 3-to-8 line decoder and two OR gates

6

19 With a block diagram explain the principle of operation of a carry look ahead adder

6

20 Explain a 4-bit parallel adder with carry lookahead scheme

10

CLOCKS AND TIMING CIRCUITS

Objective: To study clock waveforms, TTL clock, Schmitt trigger, pulse forming circuits.

FLIPS FL0PS Objective: The main objective of this chapter is to design sequential circuits( i.e. circuits which include memory elements). Study of different flip-flops, Master slave JK flip-flops. Study of different state diagrams & state equations. Also HDL implementation of flip flop.1.

Mention the difference between combinational & sequential circuits with block diagram

04

2. Mention the difference between asynchronous & synchronous circuits with example.

04

3. Difference between Latch & Flip flop give example

04

4. Define clocked sequential circuit. 0

45. Difference between Characteristic &

Excitation table. 04

6. Clearly distinguish between synchronous & asynchronous circuits, Combinational & sequential ckts, Latch & flip-flop

10*

7. Design mod-3 counter using Jk flip-flops sketch waveforms for outputs when clock is Applied & verify it’s operations.

20*

8. Show that clocked D flip-flop can be reduced by one gate

05

9. Design BCD counter with JK flip flops 10

10.Discuss why condition S=R=1 leads to unstable condition for SR latch construct state diagram for following table, what is the logic equation for output variable Z.

0 1

10

A D/1 B/0

B D/1 C/0 C D/1 A/0 D B/1 C/0

11.Examine 7476 Jk flip flop, discuss why PRE1 & CLR1 inputs are refereed to as asynchronous inputs. While JK are called synchronous inputs.

05

12.Discuss how unstable condition S=R=1 is avoided in storage latch of the following a) D latch b) JK flip flop c) T flip flop

05

13.Give a block diagram of sequential circuit employing register as a part of sequential circuit.

08

14.Design synchronous BCD counter using 0

JK flip flops. 815.Construct Mod 12 counter using MSI

chip.10

16.Design a serial adder using sequential logic procedure

10

17.Explain bi-directional shift register with parallel load

10

18.Discuss asynchronous up/down counter & explain presettable counter

10

19.Explain Schmitt trigger 10

20.Explain the operation of one shot (Monostable multivibrator)

08

21.Write short notes on a. Schmitt trigger, b. Race around condition c. Johnson counter

*12

22.Distinguish between level triggering and edge triggering explaining the advantages.

*05

23.Write short notes on a. Triggering of Flip-Flops, b. Sequence detector

*08

24.Give the details of a master slave S-R *

flip flop . Draw the logic diagram. Explain the flip-flop action during the control signal. Also give the function table.

10

25.Design the mod-6 synchronous binary counter having the following repeated binary sequence using clocked JK flip flops.0,4,2,1,6,0,4,………….

*10

26.Explain the different types of flip flops along with their truth table. Also explain the Race-around condition in a flip-flop.

*08

27.Using the logic circuit, truth table and the timing diagram explain the operation of a J-K flip flop . Show the excitation table and the Characteristic equation.

*10

28.Design a MOD-12 asynchronous (ripple) up-counter using J-K flip flops. Explain the operation briefly using the timing-diagrams.

*10

29.Explain the 4-bit binary ripple counter with the state diagram, timing diagram

*1

and logic diagram using J-K, flip flop that triggers on negative edge.

0

30.Using T flip flops design Mod-10 synchronous up counter.

*12

31.Explain the operation of clocked JK Flip-Flop with AND and NOR gates with relevant characteristics table and equation

*10`

49.

Explain the different types of flip flops along with their truth table. Also explain the race around condition in a flip flop.

8

51

With a neat logic diagram and timing waveforms describe the operation of a master-slave JK flip flop

6

52

Using T flip flops design mod-10 synchronous up counter

12

REGISTERS

Objective: The main objective is to know the types of registers and applications. Also register implementation in HDL.1.Explain registers 082.Design Universal 4 bit shift register *103.Write short note on universal shift

register5

4.Explain how the shift registers can be used as counters.

08

5.Mention the capabilities of shift registerExplain universal shift register(74194)

08

6.Discuss shift registers. 087.Discuss serial transfer of information

from one register to other.08

8.Give logic diagram of 4 bit bi-directional shift register with parallel capability & briefly explain it’s operation.

10*

9.Explain bi-directional shift register with parallel load

10

COUNTERS

Objective: The main objective is to know the types of counters and applications. Also counter design in HDL.1 Design the binary counters having

following repeated binary sequence. Use IC flip flops Only : 0,4,2,1,6.

10*

2 Design mod-3 counter using JK flip-flops sketch waveforms for outputs when clock is applied & verify it’s operations.

20*

3 Design a counter with following binary sequence a) 0,1,2 b) 0,1,2,3,4 c) 0,1,2,3,4,5,6

10

4 Mention the difference between ripple & synchronous counters.

08

5 Give logic diagram of 4-bit binary ripple counter & BCD Ripple counter

10

6 Give logic diagram of ring counter & 10

Johnson counter7 Discuss binary up/down counters 108 Construct mod –6 counter using MSI

chip.10

9 Design synchronous BCD counter using JK flip flops.

08

10 Construct Mod 12 counter using MSI chip.

10

11 Discuss asynchronous up/down counter & explain presettable counter

10

12 Design the mod-6 synchronous binary counter having the following repeated binary sequence using clocked JK flip flops.0,4,2,1,6,0,4,………….

*10

13 Design mod-12 down ripple counter *0614 Using T flip flops design Mod-10

synchronous up counter.*12

15 Using T flip flops design mod-10 synchronous up counter

12

DESIGN OF SEQUENTIAL CIRCUIT

Objective: The main objective is to learn how to design a sequential circuit-model selection, design equations and circuit diagrams and analysis and design of asynchronous circuit.

D/A CONVERSION and A/D CONVERSION

Objective: The main objective is to learn about conversion, accuracy, resolution in A/D and D/A.

DIGITAL INTEGRATED CIRCUITS

Objective: The main objective of this chapter is to study switching circuits, about TTL , CMOS and interface between TTL and CMOS.

1. Explain with ckt diagram the working of a four input Schottky TTL NAND gate

*10

2. Explain the terms as applied to TTL and indicate their typical values.Noise Margin, Propagation Delay, Fan-out, Vtg parameters

*10

3. Bring out the advantages and dis-advantages of CMOS over TTL

*06

4. What do you understand by Schottky TTL gate? Draw a std TTL gate and explain its working.

*10

5. With a neat diag explain the operation of a CMOS NOT, NAND and NOR gates.

*10

6. Mention the members of the TTL logic family, compare their typical power dissipation per gate and propagation delay.

*05

7. Illustrate the concept of fan-out by taking loading consideration of the TTL gate.

*05

8. Explain the principle of the enhancement mode MOSFET

*08

9. Draw the ckt diag and explain the operation of the 2 input TTL NAND gate with Totempole output

*10

10.With ckt explain a) NMOS NAND b) NMOS NOR

*10

11.Enumerate the different TTL subfamilies. *06

12.Discuss how a resistor could be constructed using MOSFET. Give the resistor

*06

characteristics.13.Explain the 2 utilities of an open collector

output of a TTL gate*05

14.Explain the operation of a two input TTL nand gate with totem pole output with a neat circuit diagram.

*08

15.Explain with help of the a circuit diagram the operation of a two input CMOS nor-gate.

*06

16.What is the principle of operation of schottky TTL? Explain with circuit diagram the operation of a schottky TTL

8

17.A TTL gate is generated to sink 10mA without exceeding an output voltage VOL=0.4V and to source 5mA without dropping below VOH=2.4V. If Iih=100mA at 2.4V and Iih=1 mA at 0.4V, calculate the 0-state fan-outs

6

18.Write short notes on i)comparison of logic families. ii) CMOS inverter

5

19.Explain with the help of a circuit diagram the operation of a two input CMOS nor-gate

6