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1 Quantum Physical Synthesis: Improving Physical Design by Netlist Modifications Naser Mohammadzadeh, Mehdi Sedighi, Morteza Saheb Zamani Department of Computer Engineering and Information Technology Amirkabir University of Technology {mohammadzadeh,msedighi,[email protected]} Tehran, IRAN Abstract Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. To address the limitations imposed on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design processes, in this paper we introduce physical synthesis concept in quantum circuits to improve the objectives by manipulating layout or netlist locally considering layout information. We propose a technique for physical synthesis in quantum circuits using gate-exchanging heuristic to improve the latency of quantum circuits. Moreover, a physical design flow enhanced by the technique is proposed. Our experimental results show that the proposed physical design flow empowered by the gate exchanging technique decreases the average latency objective of quantum circuits by about 24% for the attempted benchmarks. Keywords: Quantum Computing, Physical Design, Physical Synthesis, Gate Exchanging 1. Introduction As the transistor size continues to shrink to atomic scales, Moore’s law confronts the small-scale limitation that prevents wires from being made thinner than atoms [1]. On the other hand, as the quantum regime is approached, quantum effects become increasingly significant. For example, in a system that one bit is encoded as the presence or the absence of an electron, since the location of the electron is not known very precisely, based on the Heisenberg uncertainty principle, its momentum cannot be determined with high accuracy [1]. Since there is no reasonable bound on the electron’s momentum, a large potential is needed to keep it in place, and significant energy should be expended during the logic switching [1]. Experts of NCSU, SRC and Intel [2] use the results of quantitative analysis of these phenomena to extract fundamental limitations on the scalability of any computing device which moves electrons. Although these quantum effects are great barriers in classical CMOS progress, they provide a radically different form of computation [3]. Theoretically, quantum computers, computers using the quantum effects, could outperform their classical counterparts when solving certain problems. Factorization [4], unsorted database search [5], and the simulation of quantum mechanical systems [6] are some classically hard problems that benefit from quantum algorithms. For example, successful large-scale implementation of Shor’s integer factorization [4] can have deep effect on the RSA cryptosystem used in the electronic commerce. Quantum computing may also be used for the public-key cryptography [7]. MagiQ Technologies [8] and IdQuantique [9] have built such cryptography systems based on the single-photon communication. A quantum algorithm requires a quantum circuit for a successful implementation. In a large picture view, the quantum circuit design flow can be divided into two processes: synthesis and physical design (Figure 1). The synthesis process takes a description and generates a technology-dependent netlist. The physical design process creates a specific layout of the circuit based on the target technology. Even though it might seem that taking the layout information into consideration during the

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Quantum Physical Synthesis: Improving Physical Design by Netlist Modifications

Naser Mohammadzadeh, Mehdi Sedighi, Morteza Saheb Zamani

Department of Computer Engineering and Information Technology Amirkabir University of Technology

{mohammadzadeh,msedighi,[email protected]} Tehran, IRAN

Abstract

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. To address the limitations imposed on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design processes, in this paper we introduce physical synthesis concept in quantum circuits to improve the objectives by manipulating layout or netlist locally considering layout information. We propose a technique for physical synthesis in quantum circuits using gate-exchanging heuristic to improve the latency of quantum circuits. Moreover, a physical design flow enhanced by the technique is proposed. Our experimental results show that the proposed physical design flow empowered by the gate exchanging technique decreases the average latency objective of quantum circuits by about 24% for the attempted benchmarks.

Keywords: Quantum Computing, Physical Design, Physical Synthesis, Gate Exchanging

1. Introduction

As the transistor size continues to shrink to atomic scales, Moore’s law confronts the small-scale limitation that prevents wires from being made thinner than atoms [1]. On the other hand, as the quantum regime is approached, quantum effects become increasingly significant. For example, in a system that one bit is encoded as the presence or the absence of an electron, since the location of the electron is not known very precisely, based on the Heisenberg uncertainty principle, its momentum cannot be determined with high accuracy [1]. Since there is no reasonable bound on the electron’s momentum, a large potential is needed to keep it in place, and significant energy should be expended during the logic switching [1]. Experts of NCSU, SRC and Intel [2] use the results of quantitative analysis of these phenomena to extract fundamental limitations on the scalability of any computing device which moves electrons.

Although these quantum effects are great barriers in classical CMOS progress, they provide a radically different form of computation [3]. Theoretically, quantum computers, computers using the quantum effects, could outperform their classical counterparts when solving certain problems. Factorization [4], unsorted database search [5], and the simulation of quantum mechanical systems [6] are some classically hard problems that benefit from quantum algorithms. For example, successful large-scale implementation of Shor’s integer factorization [4] can have deep effect on the RSA cryptosystem used in the electronic commerce. Quantum computing may also be used for the public-key cryptography [7]. MagiQ Technologies [8] and IdQuantique [9] have built such cryptography systems based on the single-photon communication.

A quantum algorithm requires a quantum circuit for a successful implementation. In a large picture view, the quantum circuit design flow can be divided into two processes: synthesis and physical design (Figure 1). The synthesis process takes a description and generates a technology-dependent netlist. The physical design process creates a specific layout of the circuit based on the target technology. Even though it might seem that taking the layout information into consideration during the

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synthesis process or the integration of two processes into one monolithic process can potentially lead to a better final layout, the synthesis and physical design processes are normally done separately to avoid increasing the complexity of the process to an unmanageable level [17].

The CMOS design flow was similar to above until the physical synthesis, the integration of logic synthesis with the physical design information, was born in the mid to late 1990s [10]. The physical synthesis deals with the local manipulation of netlist or layout considering the layout information to improve the objectives or meet the design constraints. Such an approach can also be useful in quantum circuit design, but the physical synthesis techniques proposed in the classical CMOS design are not directly applicable to the quantum circuit design because of the fundamental differences between CMOS and quantum technologies. Therefore, new physical synthesis techniques should be proposed for quantum circuits.

Focusing on this issue, this paper brings the physical synthesis idea to the quantum design flow and proposes a technique

for the physical synthesis in quantum circuits. The proposed technique takes a technology-dependent netlist and layout and manipulates the netlist locally considering layout information to reach an improved netlist with a lower latency. Moreover, a novel physical design flow embedding the proposed physical synthesis technique is suggested.

The rest of this paper is organized as follows: an overview of the prior work is presented in Section 2, followed by an introduction to the ion trap technology in Section 3. In Section 4, the physical synthesis concept and the details of gate exchanging technique are discussed. Section 5 contains the details of our physical design flow. In Section 6, the proposed technique and flow are illustrated by an example. Section 7 shows the experimental results, and Section 8 concludes the paper. 2. Related Work

Despite significant work done on quantum algorithms and underlying physics, few studies explored the quantum circuit design flow. Svore et al. [11] [12] proposed a design flow that starts with a quantum program and generates its corresponding physical operations. Their work outlined various file formats and provided initial implementations of some of the necessary tools. Their design flow which has four phases converts a high-level program specified in the mathematical abstractions of quantum mechanics and linear algebra into a low-level set of machine instructions scheduled on a fixed H-tree-based layout [12].

Similarly, Balensiefer et al. [13] [14] proposed a design flow. Their flow takes a quantum description in QCL [15] and synthesizes it to a technology-dependent netlist. In the physical design phase, the flow schedules the generated netlist on a fixed layout by the list-scheduling algorithm [16].

Synthesis

Technology-Dependent Netlist

Physical Design

Scheduled Layout

Figure 1. Current quantum circuit design flow

High-Level Description

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Whitney et al. [17] also suggested a quantum design flow that takes a description and generates its layout in ion trap technology. They proposed new heuristics for the layout generation and scheduling. Their physical design stage includes laying out and scheduling a fixed netlist.

Additionally, hand-optimized layouts have been proposed in the literature. Metodi et al. [18] proposed a uniform Quantum Logic Array architecture, and extended and improved it later in [19]. The focus of the work was on the architectural research and the details of physical layout or scheduling were not explored. The same group later [20] developed a tool to automatically generate a physical operations schedule, given a quantum circuit and a fixed grid-based layout structure.

All the works proposing a quantum design flow perform the synthesis and physical design processes separately. The algorithms proposed for physical design take a fixed netlist and lay it out. While the approach proposed in this paper builds upon some of these ideas, its concentration is on bringing physical synthesis into quantum design flow and proposing a physical design flow considering the technique.

3. Technology Abstraction Ion trap technology [21] [22] was chosen as the underlying technology to study the proposed flow. Trapped ions have

shown good potential for scalability [23]. In this technology, a physical qubit is an ion, and a gate is a location where a trapped ion may be operated upon by a modulated laser. Pulse sequences applied to discrete electrodes on the edges of ion traps cause the ion to be trapped or ballistically moved between traps. Figure 2a shows a layout that was experimentally demonstrated for a three-way intersection [24].

In this paper, the library of macroblocks defined in [17] are used for two reasons. First, by using the macroblocks, some

of the low-level details can be removed and the analyses can be insulated from the variations in the technology implementations of ion traps. Details such as ion species, electrode sizing and geometry, and exact voltage levels necessary for trapping and moving ions are all summarized within the macroblocks. Secondly, a carefully timed application of pulse sequences to electrodes in non-adjacent traps is required for ballistic movement along a channel. Using basic blocks consisting of a few ion traps has the benefit that building an interface between the basic blocks requires communication only between the two blocks involved.

Figure 3 shows the library defined in [17]. As this figure shows, each macroblock consists of a 3x3 structure of trap regions and electrodes with some ports to allow qubit movement between the macroblocks. The black squares are gate locations, which may not be performed at intersections or turns in the ion trap technology. Different orientations of each of these macroblocks can be used in a layout. Figure 2 shows a possible mapping of a demonstrated layout (Figure 2a) to macroblock abstractions (Figure 2b). As Figure 2c shows, the laser pulses are guided to the gate locations by an array of MEMS mirrors located above the ion trap plane in order to apply quantum gates [25].

Figure 2. a) Physical layout demonstrated for a T-junction (three-way intersection). b) Abstraction of the circuit in (a), built using the StraightChannel and ThreeWayIntersection macroblocks shown in Figure 3. c) MEMS mirrors placed above the ion traps plane guide the laser beams to gate locations [17].

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Figure 3. Library of basic macroblocks used in this paper. Ports (P0-P3) and electrodes of each marcoblock make it possible for ion to be moved and trapped. Some macroblocks contain a trap region where gates may be performed (black square) [17].

Some key characteristics of ion trap technology can be summarized as follows: Rectangular channels lined with electrodes make “wires” in ion traps. Atomic ions can be suspended above the channel

regions and moved ballistically [26]. The synchronized application of voltages on the channel electrodes causes qubits to move ballistically. Therefore, the movement control circuitry is required for each wire to handle any qubit communication.

Any operation available in the ion trap technology can be performed at each gate location. This makes it possible to reuse gate locations within a quantum circuit.

Fabrication and control of ion traps in the third dimension is difficult. Thus, scalable ion trap systems are two-dimensional [24]. This imposes a restriction on ion crossings, i.e. all ion crossings must be intersections.

Multiple ions may share any routing channel as long as control circuits prevent the multi-ion occupancy.

Aside from Manhattan distance, the geometry of the wire channel is also important in the calculation of movement latency of ions. Experiments have shown that a right angle turn takes substantially longer than a straight channel over the same distance [26].

4. Physical Synthesis of Quantum Circuits

Integrating the synthesis and physical design processes into one monolithic process cannot be done because of unmanageable complexity of the problem [17]. On the other hand, doing them separately and without any information sharing between two processes can limit the optimization. An intermediate solution is conceivable that changes layout and/or netlist locally considering the layout information to improve the metrics or meet the design constraints. Prior physical design approaches do not use this idea. They take a fixed netlist and generate a layout without the manipulation of the input netlist. This style of physical design causes the improvements to be limited because of fixing netlist after synthesis process while some local netlist and/or layout manipulations considering the physical layout information could improve circuit metrics. This idea is known as physical synthesis in classical CMOS design [10]. Gate sizing, buffer insertion, and wire sizing are the techniques proposed for the physical synthesis in classical CMOS design [10]. These techniques are not applicable to quantum designs, but the general idea can be used to improve quantum circuits. To address this issue, in this section a physical synthesis technique for quantum circuits is introduced that exchanges the gates after layout generation to improve the latency of quantum circuit execution. It is important to note that the initial and the modified netlists both have the same functionality and synthesis cost, defined as number of gates or circuit depth [27]. Therefore, so the existing synthesis algorithms cannot prefer one to another in terms of latency. In other words, in our technique post-layout information is used to properly exchange gates.

4.1 Gate Exchanging Technique

Definition 1: An important set of quantum gates are controlled gates. A controlled gate has a control set and a target. The control set includes qubits that determine if function U is to be applied to the target qubit. Figure 4 shows some controlled gates. For example, the control set of gate g0 includes only qubit Q1. Qubit Q0 is the target qubit of gate g0. If Q1 is ‘1’ function U is applied to Q0.

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Definition 2: We call two controlled gates “of the same type” if their corresponding function is the same. For instance, in Figure 4, g1 and g2 are of the same type.

Definition 3: We call two gates in a circuit consecutive if their levels in the dataflow graph of the circuit are consecutive. For example, in Figure 4, gates g1 and g2 are consecutive and their levels are two and three, respectively.

Lemma 1: Assume that gates A and B are two consecutive controlled gates such as controlled-NOT, controlled-Z, etc. and gate A has control set CA and target TA and gate B has control set CB and target TB. These two gates can exchange if, and only if, one of the following conditions is satisfied

1. A and B are of the same type and TA∉CB and TB ∉CA

2. A and B are of different types and TA∉CB and TB ∉CA and TB ≠ TA

For example, in Figure 4, since gates g1 and g2 meet the first condition of Lemma 1, they can be exchanged. Gates g3 and g4 satisfy the second condition of Lemma 1. Therefore, they can also be exchanged. The general idea of gate exchanging heuristic is to determine the proper order of two exchangeable gates based on layout information. The proper order of two exchangeable gates can decrease the latency of a quantum circuit.

5. Our Physical Design Flow In order to embed the proposed physical synthesis technique in the design flow, a novel physical design flow is proposed

in this section. Our physical design flow is shown in Figure 5. The flow starts with an initial layout generation step, followed by an optimization loop applying our physical synthesis technique. After generating an initial layout, in the first step of the optimization loop, the netlist is parsed to find an exchanging pair of gates following the condition of Lemma1. If such a pair is found, the gates are tentatively exchanged and the new netlist is evaluated by updating the scheduling of the circuit to reflect the gate exchanging effect on the latency of the circuit execution. Since the optimization loop may be iterated many times and update-scheduling procedure is located on the critical path of the flow, the updating algorithm should be as quick as possible. We follow a greedy approach in applying our optimization technique. In other words, if one exchanging increases the latency, it is rejected and the optimization loop continues with other exchanging pair; otherwise, the exchanging is accepted and the netlist is modified. The optimization loop continues until there is no pair for exchanging.

Once the optimization finished and layout and netlist are finalized, the classical control should be extracted. The classical control system is responsible for executing the quantum circuit on the layout. This includes determining where and when gate operations occur as well as managing and tracking every qubit in the system. In the rest of this section, the details of main building boxes of the proposed flow are discussed.

Figure 4. A circuit with controlled gate

g1 g2 Z Z U

g0

Q2

Q1

Q0 g3 g4

X

Y

2ψ 3ψ 0ψ

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5.1 Scheduled Layout Generation

The first part of the proposed flow in Figure 5, “scheduled layout”, takes the netlist and generates an initial layout through an iterative process. This process has two subprocesses that are done subsequently in a loop to generate a better scheduled layout. In the first subsection of this section, the placement and routing heuristic is described and the second one explains the instruction scheduling approach used in this paper.

5.1.1 Placement and Routing [17]

In this paper, dataflow-based layout generation algorithm proposed in [17] is used to place and route a circuit. This algorithm claims to offer the best latency by taking a technology-dependent netlist and generating a layout comprised of the macroblocks described in Section 3. The algorithm starts with creating dataflow graph of the circuit. In the dataflow graph, each node represents an instruction and each arc represents a qubit dependency (see Figure 6). In the next step, gate locations are placed in chronological order in the dataflow graph. Whereas this style of placement may waste space due to the uneven column sizes, a folding operation is performed. The folding operation joins a short column with the previous column in order to fill out the rectangular bounding box of the layout as much as possible and decrease area. Then, the columns are sorted to set the gate locations that need to be connected roughly horizontal to one another. After placing the gate locations, channels are routed to reflect dataflow edges. Since the initial layout has too many gate locations, the dataflow graph is collapsed using scheduler feedback. The algorithm identifies latencies of critical edges by using scheduler feedback and merges the two nodes connected by edge with the longest latency on the critical path. All instructions within a merged group are executed at

Scheduled Layout (5.1)

Update Scheduling (5.2)

No

Placement & Routing (5.1.1)

Scheduling (5.1.2)

Is Any More Gate Exchanging Possible?

Tentative Gate Exchanging

YEs

Is Latency Improved?

Accept this Gate Exchanging and Change the Netlist

YEs

No Reject this Gate Exchanging

Figure 5. The proposed physical design Flow

Classical Control Extraction

Technology-Dependent Netlist

Gate-exchanging technique

Physical Synthesis

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a single gate location. This new group graph is then placed, routed and scheduled again to find the next pair of node groups to merge and this merging and placing and routing procedure continues until a point is reached where congestion at some heavily merged node group is actually hurting the latency with each further merge.

5.1.2 Instruction Scheduling

The runtime execution order of the instructions is determined by the instruction issue logic. The instruction issue logic involves both preprocessing and online scheduling. First, the instruction sequence is preprocessed to assign priorities that will help during scheduling. The priority of an instruction is based on the length of its critical path to the end of dataflow graph. Since the gate locations are known in advance, the movement latencies can be incorporated in the prioritization of the instruction sequence. In other words, movement latencies can be considered as well as gate delays in the assignment of priorities to instructions during preprocessing. This gives a better approximation of each qubit’s critical path. The scheduling used in this paper is similar to the method used in [20], but it uses critical path with gate and movement latencies to set the priority of a gate rather than the size of the dependent subtree to that gate. The instruction sequence is traversed from the beginning to the end and instructions are scheduled as soon as the dependencies allow.

The scheduler implements a greedy scheduling technique. It maintains a list of instructions which have all their dependencies fulfilled and therefore, are ready to be executed. Among the ready instructions, the instruction with the highest priority will be run and is more likely to gain access to the resources it needs. These contested resources include both gates and channels/intersections. Once all the possible instructions are scheduled, time advances until one or more resources are freed and more instructions can be scheduled. This scheduling process continues until the full instruction sequence is executed.

It is worth noting that the proposed flow uses scheduling information to decide whether to accept or reject exchanges. In other words, our technique is not stuck at scheduling method and it has its advantage over different scheduling schemes. In other words, even if we use a scheduling method resulting in the best latency, our technique can still improve the latency. However, since exhaustive scheduling is impractical for large circuits, we use a greedy heuristic to schedule operations.

5.2 Update Scheduling

The scheduling information is used to accept or reject an exchanging operation. Therefore, it should be done in each iteration of the optimization loop. However, performing a complete scheduling in each iteration can dramatically increase total run time for large netlists. Considering that, since the gate exchanging often modifies a small part of the netlist tree, there may not be a need for performing scheduling completely in each iteration. Focusing on this fact, in the proposed flow, the scheduling is incrementally updated in each iteration of the optimization loop. This decreases the run time of each iteration and therefore, leads to overall run time reduction.

The scheduler selects the operations based on their dependencies and priorities. The gate exchanging process may change the priorities of the gates. Therefore, the update-scheduling operation must modify the priorities of the exchanged nodes and propagate the effects of these changes to the nodes located higher than the nodes in the dataflow graph. The priorities of exchanged nodes are calculated based on priorities of nodes located lower than them in the dataflow graph. Then, this modification is propagated to the nodes higher than the exchanged gates and their priorities are updated. The propagation continues up to the root of the dataflow graph (i.e., a dummy node with the first level gates as its children).

6. An Example

In this section, an example is given to illustrate the physical synthesis flow. Figure 6a shows a QASM [28] instruction sequence operating on qubits q0, q1, q2 and q3, with each instruction labeled with a letter. Figure 6b shows the equivalent quantum circuit. The dataflow graph of the circuit is shown in Figure 6c. Figure 6d shows the layout generated for the netlist by the dataflow-based algorithm described in Section 5.1.1. To make the analysis independent from the variations in the delays of ion movements and gates, the latency is calculated parametrically in terms of the latencies of physical operations (i.e. one-qubit gate delay (DSQG), two-qubit gate delay (DTQG), straight movement latency (M), zero preparation time (ZP), and turn operation latency (T)). The label of each edge shows the minimum delay between two nodes. The label of each node

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represents its delay from the end of the tree and is used as the node’s priority. The label zero on the edge between E and H and between C and F implies that they will execute in the same gate location. The node R is a dummy node used as the root of the circuit dataflow graph with nodes A, B, C, D as its children.

Initially, the latency of this circuit is calculated in four phases as shown in Figure 7. In the first phase, gates A, B, C, and D can be executed simultaneously. In the second phase, gates E and F are executed at the same time. In the third phase, only gate G can be executed. Finally, in the fourth phase, gate H is executed. The total latency (LTotal) can be calculated by adding the latencies of the phases together.

Then the gate pairs that can be exchanged are determined. Since gates H and G are of the same type and target qubit of one is not in the control set of the other, they can be exchanged based on Lemma 1. If gates H and G are exchanged, the circuit changes to circuit shown in Figure 8a. After exchanging, the update scheduling stage updates the nodes’ priorities and edges. If the priority of the root node increases after exchanging, the operation is denied; otherwise it is accepted. The priorities change as in Figure 9. The priority of the root has been decreased and therefore, the exchanging is accepted and the netlist is updated. Since there is no unattemped exchange, the optimization process is finished. The latency calculations for phases I and II for the updated netlist are the same as those for the initial netlist but they are different for phases III and IV. The details of the delay calculations for these phases are shown in Figure 8. As the calculated latencies show, the applied gate exchanging physical synthesis technique has improved the latency of the circuit by 2T.

Hq0

q1

q2

q3

(b)

A: H q0B: H q1C: H q2D: H q3E: CNOT q0,q1F: CNOT q2,q3G: CNOT q1,q2H: CNOT q0, q2

(a) (d)

A

HB

HC

HD

E

F

G H

A B C D

E F

G

H

(c)

R

PG= DTQG +(2M+2T)

2M+2T

2M+2T

PF= 2DTQG +(5M+4T)

3M+2T

PD= 3DTQG +(7M+5T)

3M+2T2M+2T

PA= 3DTQG +(7M+6T) PB= 3DTQG +(6M+6T) PC= 3DTQG +(5M+4T)

0

2M+T0

00 00

PG= 2DTQG +(4M+4T)

PR= 3DTQG + DSQG + (7M+6T) + ZP

M = Move Op LatencyT = Turn Op LatencyDTQG = 2-qubit gate delayDSQG = 1-qubit gate delayZp= Zero Preparation time

Figure 6 (a) Circuit netlist [H: Hadamard operation, CNOT: Controlled bit-flip operation], (b) circuit representation, (c) data-flow graph and (d) Generated layout by the dataflow-based algorithm [17]

F, C E, H

G

B D

A

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q2q3 q0q1

q3 q0

q1q2

Phase IA, B, C, DLPI = DSQG

Phase IIE,F

LPII = 3M + 2T + DTQG

Phase IIIG

LPIII = 3M + 2T + DTQG

Phase IVH

LPIV = 2M + 2T + DTQG

LTotal = Zp +8M + 6T + 3DTQG + DSQG

Figure 7. The latency calculation details for the netlist shown in Figure 6

H

H

H

H

q0

q1

q2

q3

q2q3 q0

Phase III H

LPIII = 3M + DTQG

q1q3 q2

q1

q0

Phase IV G

LPIV = 2M + 2T + DTQG

LTotal = Zp+8M + 4T + 3DTQG + DSQG

(a)

Figure 8 The phases III and IV for netlist shown in (a)

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7. Experimental Results

Relatively high error rates of operations in a quantum computer necessitate the heavy encodings of qubits [1]. As such, this paper focuses on the encoding circuits (useful for both data and ancillae) and error correction circuits to experiment with the proposed approach. A number of error correction and encoding circuits are used to evaluate the effectiveness of the proposed flow.

Latency is an important metric for the error encoding circuits [29]. A high latency circuit could introduce non-trivial errors due to increased qubit idle time. On the other hand, correction circuits are much more latency-dependent since they are on the critical path for the processing of data qubit blocks [29].

Table 1: List of the benchmarks, with quantum gate count and number of qubits processed in the circuit

# Circuit name [30] Qubit count Gate count # Circuit name [30] Qubit count Gate count

1 [[7, 1, 3]] L1 encode 7 18 10 [[24,3,7]] L1 encode 24 205

2 [[9,1,3]] Bacon-Shor encode [32] 9 16 11 [[25,1,9]] L1 encode 25 168

3 [[10,3,3]] L1 encode 10 44 12 [[27,1,9]] L1 encode 27 244

4 [[11,1,5]] L1 encode 11 47 13 [[30,20,4]] L1 encode 30 411

5 [[13,1,3]] Surface encode [33] 13 32 14 [[31,11,6]] L1 encode 31 339

6 [[13,1,5]] L1 encode 13 64 15 [[33,1,9]] L1 encode 33 316

7 [[16,3,5]] L1 encode 16 89 16 [[35,1,10]] L1 encode 35 389

8 [[18,1,7]] L1 encode 18 102 17 [[36,7,6]] L1 encode 36 395

9 [[21,1,7]] L1 encode 21 140 18 [[40,3,10]] L1 encode 40 483

A B C D

E F

H

G

R

PH= DTQG +(2M+2T)

2M+2T2M+2

T

PF= 2DTQG + 5M + 2T

3M

PD= 3DTQG +(7M+4T)3M+2T

2M+2T

PA= 3DTQG +(5M+4T) PB= 3DTQG +(4M + 4T) PC= 3DTQG + (5M + 2T)

0

2M+T0

00 00

PE= 2DTQG +(2M+2T)

PR= 3DTQG + DSQG +(5M+4T) + ZP

PG= 0

Figure 9 The circuit DFG after exchanging H and G

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The proposed flow was evaluated on the benchmarks shown in Table 1. Error probabilities and physical latencies shown in Table 2 are used for the gates and for the two types of move operations in ion trap technology [31]. The benchmarks include controlled-Z, controlled-X, controlled-Y, and Hadamard gates that are realizable in ion trap technology.

Table 2: The error probabilities and latency values for various physical operations in ion trap technology [31]

Physical Operation Latency Symbol Latency (μs) Error

One-Qubit Gate t1q 1 10-6

Two-Qubit Gate t2q 10 10-6

Measurement tmeas 50 10-6

Zero Prepare tprep 51 10-6

Straight Move tmove 1 10-8

Turn tturn 10 10-8

Table 3. The latency of the benchmark circuits achieved by prior physical design flow and ours

# Circuit name [30] # Tentative Exchanges

# Accepted Exchanges

Latency (μs)

Improvement (%) Prior Physical

Design Flow [17] Our Physical Design Flow

1 [[7, 1, 3]] L1 encode 3 1 331 312 6.1

2 [[9,1,3]] Bacon-Shor encode 2 1 207 177 16.9

3 [[10,3,3]] L1 encode 16 6 960 800 20

4 [[11,1,5]] L1 encode 9 3 842 728 15.7

5 [[13,1,3]] Surface encode 9 2 504 456 10.5

6 [[13,1,5]] L1 encode 10 6 1281 1085 18.1

7 [[16,3,5]] L1 encode 28 5 1757 1571 11.8

8 [[18,1,7]] L1 encode 18 5 1612 1417 13.8

9 [[21,1,7]] L1 encode 32 20 3068 2245 36.7

10 [[24,3,7]] L1 encode 38 11 4587 4058 13

11 [[25,1,9]] L1 encode 27 21 4491 3527 27.3

12 [[27,1,9]] L1 encode 98 41 5687 4079 39.4

13 [[30,20,4]] L1 encode 263 73 8626 6552 31.7

14 [[31,11,6]] L1 encode 350 66 7362 5120 43.8

15 [[33,1,9]] L1 encode 150 48 9026 6862 31.5

16 [[35,1,10]] L1 encode 96 21 7347 6540 12.3

17 [[36,7,6]] L1 encode 118 46 9805 7397 32.6

18 [[40,3,10]] L1 encode 500 73 11405 7900 44.4

Average 23.64

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Table 3 shows the latency of the benchmark circuits resulted from the prior physical design flow [17] and our physical design flow enhanced by the gate-exchanging physical design technique. The column “# of tentative exchanges” contains the number of exchanges that can be done and the column “# of accepted exchanges” includes the number of exchanges that have been done. The latency of circuits obtained by prior physical design flow and ours are shown in the columns “prior physical design flow” and “our physical design flow”, respectively.

Figure 10. The latency reduction achieved by our physical synthesis approach

The column “Improvement” shows the latency improvement resulted from the physical synthesis approach proposed in this paper. As can be seen, a considerable improvement of 23.64% (on average) has been achieved in the latency of the benchmarks. The results of Table 3 are summarized in Figure 10 that shows the latency reduction of our physical design flow using physical synthesis compared to the prior physical design flow. The behavior of latency reduction for the benchmarks are depicted in Figure 11. The horizontal and vertical lines show the number of accepted exchanges and the resulted latency, respectively. Each point on the line of each benchmark shows the latency after the nP

thP accepted exchange.

Since we follow a greedy way, the accepted exchanges always decrease the latency. In other words, we accept and apply only exchanges that improve the latency. The optimization loop continues until there is no unattempted exchange.

Number of Exchanges

Figure 11. The behavior of the latency vs. gate exchanging number

Benchmark Number

Late

ncy

(µs)

La

tenc

y (µ

s)

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7.1 Heuristic Algorithm Analysis As stated before, we follow a greedy approach to accept or reject one exchange. In other words, the gate exchnages

increasing the latency are rejected. To examine the impact of applying other heuristics on the result, we used simulated annealing (SA) heurisitc [34] in accepting or rejecting exchanges. Table 4 shows the results of using the heuristic. The column “Our Approach Based on SA” under “latency” shows the latency obtained by our physical design flow when we substitute simulated annealing heuristic for our greedy approach. The columns “Our Approach Based on Greedy” and “Our Approach Based on SA” under “Runtime” show the runtimes of our physical design flow using simulated annealing approach and greedy approach, respectively. The column “SA/Greedy Ratio” under “Latency” contains the ratio of the latency obtained by simulated annealing to that achieved by our greedy approach. The last column includes the ratio of the runtime of the flow based on simulated annealing approach to that based on our greedy approach. It can be observed from the table that simulated annealing has provided slightly better results than greedy approach in most cases. However, on average, the runtime of simulated annealing is almost 13 times longer. This observation might suggest that while various heuristics may provide

1 All results of this section are obtained on a 3 GHz Pentium IV with 1 gigabyte of memory. 2 As calculated by “Rational Quantify” suit [35]

Table 4: The latency of the benchmark circuits achieved by using simulated annealing heuristic instead of our greedy approach in accepting or rejecting exchanges1

# Circuit name # Accepted Exchanges

Latency (µs) Run Time (ms)2

Our Approach Based on Greedy

Our Approach Based on SA

SA/Greedy Ratio Our Approach

Based on Greedy Our Approach Based on SA

SA/Greedy Ratio

1 [[7, 1, 3]] L1 encode 1 312 312 1 4583 4800 1.05

2 [[9,1,3]] Bacon-Shor 1 177 177 1 4780 4880 1.02

3 [[10,3,3]] L1 encode 10 800 760 0.95 5373 51974 9.67

4 [[11,1,5]] L1 encode 6 728 708 0.97 6424 56094 8.73

5 [[13,1,3]] Surface 5 456 435 0.95 7928 44321 5.59

6 [[13,1,5]] L1 encode 7 1085 1093 1.01 7459 71409 9.57

7 [[16,3,5]] L1 encode 15 1571 1460 0.93 10171 99605 9.79

8 [[18,1,7]] L1 encode 12 1417 1432 1.01 8962 119153 13.26

9 [[21,1,7]] L1 encode 25 2245 2134 0.95 11817 191076 16.17

10 [[24,3,7]] L1 encode 22 4058 3603 0.89 13404 300889 22.45

11 [[25,1,9]] L1 encode 23 3527 3586 1.02 10795 256987 23.81

12 [[27,1,9]] L1 encode 64 4079 3908 0.96 16542 303465 18.35

13 [[30,20,4]] L1 encode 150 6552 6383 0.97 25410 352156 13.86

14 [[31,11,6]] L1 encode 108 5120 4997 0.98 18428 334475 18.15

15 [[33,1,9]] L1 encode 141 6862 6608 0.96 18196 315567 17.34

16 [[35,1,10]] L1 encode 57 6540 6120 0.94 23909 348678 14.58

17 [[36,7,6]] L1 encode 74 7397 7106 0.96 24121 349876 14.5

18 [[40,3,10]] L1 encode 134 7900 7698 0.97 33620 377653 11.23

Average 0.97 12.73

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slightly different results, it’s the execution time that varies the most among them. In other words, it appears that the execution time is the determining factor in choosing among the heuristic approaches. Based on this, we have chosen the greedy approach for the remainder of this paper. Figure 12 depicts the behavior of the latency obtained by the two approaches.

Figure 12: The behavior of the latency obtained by using two different approach in accepting or rejecting of exchanges

7.2 Error Analysis

To evaluate the proposed technique in term of reliability, we use critical error path calculation proposed in [31]. The critical error path is the sequence of qubit interactions that introduces the highest error into the circuit, in a way similar to the critical latency path through a circuit.

Figure 13 illustrates the process of estimating the critical error path. It uses a simple, but effective model of a complicated error propagation process to estimate a parameter referred to as Error Distance [31]. We use the method proposed in [31], but we also consider other physical operations as well as gates to calculate the critical error path. The model assumes that (1) each of gate, measurement, and zero prepare operations introduces one unit of error, (2) each of straight and turn movements introduces 0.01 unit of error, (3) all qubits interacting within a gate acquire the maximum error value out of those qubits. Error probabilities shown in Table 2 have been used to extract the error units of physical operations. Symbols S and T respectively show the number of straight and turn macroblocks that should be traversed by a qubit to reach the next gate

location.

Late

ncy

(µs)

Q0

Q1

Q2

# T = 2 # S = 10

# T = 0 # S = 0

2×0.01 (turn) + 10×0.01(straight) + 1(gate) = 1.12

Error Distance = 1.12 # T = 0 # S = 0

# T = 4 # S = 20

1.12 + 4×0.01(turn) + 20×0.01(straight) + 1 (gate) = 2.36

# T = 0 # S = 0

# T = 0 # S = 0

# T = 1 # S = 10

Error Distance = 2.36

Error Distance = 1×0.01+10×0.01+2.36 = 2.47

Maximum Error Distance

Figure 13: Simple model of counting errors

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Table 5 shows the maximum error distance for the benchmarks before and after applying our approach. Maximum error distance of circuits obtained by prior physical design flow and ours are shown in the columns “Prior Physical Design Flow” and “Our Physical Design Flow”, respectively. As can be seen, a considerable improvement of 22.8% (on average) has been achieved in the maximum error distance of the benchmarks.

Table 5: The maximum error distance of the benchmark circuits achieved by prior physical design flow and ours

Max Error Distance (10-6) Improvement

(%)

Max Error Distance(10-6) Improvement

(%) # Circuit name Prior Physical

Design Flow [17] Our Physical Design Flow # Circuit name Prior Physical

Design Flow [17] Our Physical Design Flow

1 [[7, 1, 3]] L1 encode 9.22 8.11 13.7 10 [[24,3,7]] L1 encode 114.21 100.67 13.4

2 [[9,1,3]] Bacon-Shor 7.11 6.9 3.1 11 [[25,1,9]] L1 encode 112.08 87.86 27.6

3 [[10,3,3]] L1 encode 29.61 23.72 24.8 12 [[27,1,9]] L1 encode 146.21 104.49 40

4 [[11,1,5]] L1 encode 26.18 22.49 16.4 13 [[30,20,4]] L1 encode 269.59 200.79 34.3

5 [[13,1,3]] Surface 15.03 12.75 17.9 14 [[31,11,6]] L1 encode 196.2 145.3 35

6 [[13,1,5]] L1 encode 36.51 31.01 17.7 15 [[33,1,9]] L1 encode 212.48 168.09 26.4

7 [[16,3,5]] L1 encode 52.34 46.43 12.7 16 [[35,1,10]] L1 encode 176.79 145.44 21.6

8 [[18,1,7]] L1 encode 46.03 40.96 12.3 17 [[36,7,6]] L1 encode 235.21 180.15 30.6

9 [[21,1,7]] L1 encode 77.69 58.06 33.8 18 [[40,3,10]] L1 encode 251.54 195.46 28.7

Average = 22.8

7.3 Time Complexity Analysis The time complexity of our physical synthesis technique can be calculated as follows. Since we follow a greedy approach

in our flow, our algorithm examines each two nodes connected to an edge for an exchange. On the other hand, each permanent exchange modifies at most four edges. Therefore, the permanent exchanges add a factor equal to “4*number of permanent exchanges” to the total number of edges that should be checked. This, in the worst case, is of order of number of edges.

The other factor in the time complexity is the runtime of the update-scheduling process in each iteration. As stated in Section 5, the scheduling result should be updated for each tentative exchange. The main part of the runtime of update-scheduling process is the runtime of updating the nodes’ priorities. The number of steps for updating nodes priorities for each tentative exchange is equal to the node’s depth. This is because when a node is exchanged with another, only the priorities of those nodes located between it and the root in the dataflow graph need to be updated. The upper bound of the node’s depth and the upper bound of the number of tentative exchanges are equal to the circuit depth and the number of edges, respectively. Therefore, the overall time complexity of the overhead of our approach can be calculated as

O(D×E)

where D and E are the number of gates. D is the upper bound of circuit depth and E is the upper bound of the number of edges.

8. Conclusion In this paper, a new quantum physical design flow was proposed that based on the concept of physical synthesis that has

been inspired by a similar concept in CMOS design. A physical synthesis technique was also proposed which modifies the circuit netlist considering the layout information to improve latency of quantum circuit execution. In the proposed technique, the gates that can be exchanged without changing the functionality of the circuits are identified and layout information is used to evaluate their exchange in terms of circuit latency. The proposed flow was applied to a set of error encoding quantum

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circuits. Experimental results showed that the proposed physical synthesis flow could improve the latency of quantum circuits up to 43.8% for the attempted benchmarks.

We are working on new physical synthesis techniques and improving the proposed design flow by adding new blocks in addition to gate exchanging. Moreover, since previous approaches to determine the error tolerance of a quantum circuitare very computationally-intensive may not be appropriate for circuits with more than a few dozen gates [36], we are looking into ways to incorporate fault tolerance directly as a metric.

Acknowledgements We would like to thank Prof. D. Wineland for his invaluable deliberation about Ion Trap technology.

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