Qualkitdo Rptgenext Qualificationreport SDD Cont

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SDD_cont.slx

Design Description

The MathWorks, Inc.


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SDD_cont.slx

2

SDD_cont.slx: Design DescriptionThe MathWorks, Inc.

Publication date 16-Aug-2013 11:35:17

Copyright © 2013

For Internal Distribution Only


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iii

Table of Contents

1. Model Version ............................................... ........................................................ ......... 1

2. Root System .......................... ....................................................... .................................. 2

Description ................................................. ....................................................... ......... 2

Blocks ....................................................................................................................... 2

Parameters ........................................................................ ................................. 2Block Execution Order ......................................................................................... 8

3. System Model Configuration ..... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... .. 10


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iv

List of Figures

2.1. SDD_cont ............................................... ........................................................ ............. 2


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1

Chapter 1. Model VersionVersion: 1.56

Last modified: Wed Mar 13 10:39:49 2013

Checksum: 1132089350 2106545894 2877672834 2771224181


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2

Chapter 2. Root System

Table of Contents

Description ........................................................ ........................................................ ......... 2

Blocks ..................................................... ........................................................ .................. 2

Parameters ....................................................................... .......................................... 2

Block Execution Order ................................................................................................. 8

Figure 2.1. SDD_cont

Copyright 2009-2011 The MathWorks, Inc.

(s-1)

s(s+1)

Zero-Pole

To

VarDelay

1

s +1

Transfer Fcn

TransDelay

x' = Ax+Bu y = Cx+Du

State-Space

Sine Wave6

Sine Wave5

Sine Wave4

Sine Wave3

Sine Wave2

Sine Wave1

Sine Wave

Simulink Report Generator (SDD Report) Test ModelSDD_cont

1s

Integrator

du/dt

Derivative

1

Constant

DescriptionSimulink Report Generator (SDD Report) Test Model

Blocks

Parameters

"Constant" (Constant)

Table 2.1. "Constant" Parameters

Parameter Value

Constant value 1


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Root System

3

Parameter Value

Interpret vector paramet-

ers as 1-D

on

Sampling mode Sample based

Output minimum []

Output maximum []

Output data type Inherit: Inherit from 'Constant value'

Lock output data type se-

tting against changes by

the fixed-point tools

off

Sample time inf

Frame period inf

"Derivative" (Derivative)

Table 2.2. "Derivative" Parameters

Parameter Value

Coefficient c in the trans-

fer function approximati-

on s/(c*s + 1) used for li-

nearization

inf

"Integrator" (Integrator)

Table 2.3. "Integrator" Parameters

Parameter Value

External reset none

Initial condition source internal

Initial condition 0

Limit output off

Upper saturation limit inf

Lower saturation limit -inf

Show saturation port off

Show state port off

Ignore limit and reset

when linearizing

off

Enable zero-crossing det-

ection

on


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Root System

4

Parameter Value

State Name (e.g., 'positi-

on')

''

"Sine Wave" (Sin)

Table 2.4. "Sine Wave" Parameters

Parameter Value

Sine type Time based

Time (t) Use simulation time

Amplitude 1

Bias 0

Frequency (rad/sec) 1

Phase (rad) 0

Samples per period 10

Number of offset sampl-

es

0

Sample time 0


ers as 1-D

on

"Sine Wave1" (Sin)

Table 2.5. "Sine Wave1" Parameters

Parameter Value



Amplitude 1

Bias 0


Phase (rad) 0



es

0

Sample time 0


ers as 1-D

on


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Root System

5

"Sine Wave2" (Sin)


Parameter Value



Amplitude 1

Bias 0


Phase (rad) 0



es

0

Sample time 0

Interpret vector paramet-ers as 1-D

on

"Sine Wave3" (Sin)


Parameter Value



Amplitude 1

Bias 0


Phase (rad) 0



es

0

Sample time 0


ers as 1-D

on

"Sine Wave4" (Sin)


Parameter Value



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Root System

6

Parameter Value


Amplitude 1

Bias 0


Phase (rad) 0



es

0

Sample time 0


ers as 1-D

on

"Sine Wave5" (Sin)


Parameter Value



Amplitude 1

Bias 0


Phase (rad) 0



es

0

Sample time 0


ers as 1-D

on

"Sine Wave6" (Sin)

Table 2.10. "Sine Wave6" ParametersParameter Value



Amplitude 1

Bias 0



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Root System

7

Parameter Value

Phase (rad) 0



es

0

Sample time 0


ers as 1-D

on

"State-Space" (StateSpace)

Table 2.11. "State-Space" Parameters

Parameter Value

A 0

B 1

C 1

D 0

Initial conditions 0


on')

''

"TransDelay" (TransportDelay)

Table 2.12. "TransDelay" Parameters

Parameter Value

Time delay 1

Initial output 0

Initial buffer size 1024

Use fixed buffer size off

Direct feedthrough of in-

put during linearization

off

Pade order (for lineariza-

tion)

0

"Transfer Fcn" (TransferFcn)

Table 2.13. "Transfer Fcn" Parameters

Parameter Value

Numerator coefficients [1]


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Root System

8

Parameter Value

Denominator coefficients [1 1]


on')

''

"VarDelay" (VariableTransportDelay)

Table 2.14. "VarDelay" Parameters

Parameter Value

Select delay type Variable time delay

Maximum delay 10

Initial output 0

Initial buffer size 1024

Use fixed buffer size off

Handle zero delay off

Direct feedthrough of in-

put during linearization

off

Pade order (for lineariza-

tion)

0


on')

''

"Zero-Pole" (ZeroPole)

Table 2.15. "Zero-Pole" Parameters

Parameter Value

Zeros [1]

Poles [0 -1]

Gain [1]


on')

''

Block Execution Order1. Constant [2] (Constant)

2. Sine Wave5 [6] (Sin)

3. VarDelay [8] (VariableTransportDelay)

4. Sine Wave [4] (Sin)

5. Derivative [3] (Derivative)

6. Integrator [3] (Integrator)



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Root System

9


9. State-Space [7] (StateSpace)


11. Transfer Fcn [7] (TransferFcn)


13. TransDelay [7] (TransportDelay)

14. Sine Wave6 [6] (Sin)15. Zero-Pole [8] (ZeroPole)


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Chapter 3. System Model Configuration

Table 3.1. SDD_cont Configuration Set

Property Value

Description

Components [SDD_cont Configuration Set.Components(1) [-

10], SDD_cont Configuration Set.Component-

s(2) [11], SDD_cont Configuration Set.Comp-

onents(3) [12], SDD_cont Configuration Set.-

Components(4) [13], SDD_cont Configuration

Set.Components(5) [15], SDD_cont Configur-

ation Set.Components(6) [16], SDD_cont Co-

nfiguration Set.Components(7) [17], SDD_co-

nt Configuration Set.Components(8) [18]]

Name Configuration

SimulationMode normal

Table 3.2. SDD_cont Configuration Set.Components [10](1)

Property Value

Name Solver

Description

Components

StartTime 0.0

StopTime 10

AbsTol auto

FixedStep auto

InitialStep auto

MaxNumMinSteps -1

MaxOrder 5

ZcThreshold auto

ConsecutiveZCsStepRelTol 10*128*eps

MaxConsecutiveZCs 1000

ExtrapolationOrder 4

NumberNewtonIterations 1

MaxStep auto

MinStep auto

MaxConsecutiveMinStep 1

RelTol 1e-3

SolverMode Auto

EnableConcurrentExecution off


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System Model Configuration

11

ConcurrentTasks off

Solver ode45

SolverName ode45

SolverType Variable-step

SolverJacobianMethodControl auto

ShapePreserveControl DisableAll

ZeroCrossControl UseLocalSettings

ZeroCrossAlgorithm Nonadaptive

SolverResetMethod Fast

PositivePriorityOrder off

AutoInsertRateTranBlk off

SampleTimeConstraint Unconstrained

InsertRTBMode Whenever possible

SampleTimeProperty


Property Value

Name Data Import/Export

Description

Components

Decimation 1

ExternalInput [t, u]

FinalStateName xFinal

InitialState xInitial

LimitDataPoints on

MaxDataPoints 1000

LoadExternalInput off

LoadInitialState off

SaveFinalState off

SaveCompleteFinalSimState off

SaveFormat Array

SignalLoggingSaveFormat ModelDataLogs

SaveOutput on

SaveState off

SignalLogging on

DSMLogging on

InspectSignalLogs off

SaveTime on

ReturnWorkspaceOutputs off


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StateSaveName xout

TimeSaveName tout

OutputSaveName yout

SignalLoggingName logsout

DSMLoggingName dsmout

OutputOption RefineOutputTimes

OutputTimes []

ReturnWorkspaceOutputsName out

Refine 1


Property Value

Name Optimization

Description

Components

BlockReduction off

BooleanDataType on

ConditionallyExecuteInputs on

InlineParams off

UseIntDivNetSlope off

UseFloatMulNetSlope off

DefaultUnderspecifiedDataType double

UseSpecifiedMinMax off

InlineInvariantSignals off

OptimizeBlockIOStorage on

BufferReuse on

EnhancedBackFolding off

StrengthReduction off

AdvancedOptControl

EnforceIntegerDowncast on

ExpressionFolding on

BooleansAsBitfields off

BitfieldContainerType uint_T

EnableMemcpy on

MemcpyThreshold 64

PassReuseOutputArgsAs Structure reference

PassReuseOutputArgsThreshold 12

FoldNonRolledExpr on

LocalBlockOutputs on


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UnderspecifiedInitializationDetection Classic

MergeDetectMultiDrivingBlocksExec none

CheckExecutionContextPreStartOutputMsg off

CheckExecutionContextRuntimeOutputMsg off

SignalResolutionControl TryResolveAllWithWarning

BlockPriorityViolationMsg warning

MinStepSizeMsg warning

TimeAdjustmentMsg none

MaxConsecutiveZCsMsg error

MaskedZcDiagnostic warning

IgnoredZcDiagnostic warning

SolverPrmCheckMsg none

InheritedTsInSrcMsg warning

DiscreteInheritContinuousMsg warning

MultiTaskDSMMsg warning

MultiTaskCondExecSysMsg none

MultiTaskRateTransMsg error

SingleTaskRateTransMsg none

TasksWithSamePriorityMsg warning

SigSpecEnsureSampleTimeMsg warning

CheckMatrixSingularityMsg none

IntegerOverflowMsg warning

Int32ToFloatConvMsg warning

ParameterDowncastMsg error

ParameterOverflowMsg error

ParameterUnderflowMsg none

ParameterPrecisionLossMsg warning

ParameterTunabilityLossMsg warning

FixptConstUnderflowMsg none

FixptConstOverflowMsg none

FixptConstPrecisionLossMsg none

UnderSpecifiedDataTypeMsg none

UnnecessaryDatatypeConvMsg noneVectorMatrixConversionMsg none

InvalidFcnCallConnMsg error

FcnCallInpInsideContextMsg UseLocalSettings

SignalLabelMismatchMsg none

UnconnectedInputMsg warning

UnconnectedOutputMsg warning


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UnconnectedLineMsg warning

SFcnCompatibilityMsg none

FrameProcessingCompatibilityMsg warning

UniqueDataStoreMsg none

BusObjectLabelMismatch warning

RootOutportRequireBusObject warning

AssertControl UseLocalSettings

Echo

EnableOverflowDetection off

ModelReferenceIOMsg none

ModelReferenceVersionMismatchMessage none

ModelReferenceIOMismatchMessage none

ModelReferenceCSMismatchMessage none

ModelReferenceSimTargetVerbose off

UnknownTsInhSupMsg warning

ModelReferenceDataLoggingMessage warning

ModelReferenceSymbolNameMessage warning

ModelReferenceExtraNoncontSigs error

StateNameClashWarn warning

SimStateInterfaceChecksumMismatchMsg warning

SimStateOlderReleaseMsg error

InitInArrayFormatMsg warning

StrictBusMsg ErrorLevel1

BusNameAdapt WarnAndRepair

NonBusSignalsTreatedAsBus none

LoggingUnavailableSignals error

SFUnusedDataAndEventsDiag warning

SFUnexpectedBacktrackingDiag warning

SFInvalidInputDataAccessInChartInitDiag warning

SFNoUnconditionalDefaultTransitionDiag warning

SFTransitionOutsideNaturalParentDiag warning

SFUnconditionalTransitionShadowingDiag warning

SFUndirectedBroadcastEventsDiag warningSFTransitionActionBeforeConditionDiag warning


Property Value

Name Hardware Implementation

Description


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Components

ProdBitPerChar 8

ProdBitPerShort 16

ProdBitPerInt 32

ProdBitPerLong 32

ProdBitPerLongLong 64

ProdBitPerFloat 32

ProdBitPerDouble 64

ProdBitPerPointer 32

ProdLargestAtomicInteger Char

ProdLargestAtomicFloat None

ProdIntDivRoundTo Undefined

ProdEndianess Unspecified

ProdWordSize 32

ProdShiftRightIntArith on

ProdLongLongMode off

ProdHWDeviceType 32-bit Generic

TargetBitPerChar 8

TargetBitPerShort 16

TargetBitPerInt 32

TargetBitPerLong 32

TargetBitPerLongLong 64

TargetBitPerFloat 32

TargetBitPerDouble 64

TargetBitPerPointer 32

TargetLargestAtomicInteger Char

TargetLargestAtomicFloat None

TargetShiftRightIntArith on

TargetLongLongMode off

TargetIntDivRoundTo Undefined

TargetEndianess Unspecified

TargetWordSize 32

TargetTypeEmulationWarnSuppressLevel 0TargetPreprocMaxBitsSint 32

TargetPreprocMaxBitsUint 32

TargetHWDeviceType Specified

TargetUnknown off

ProdEqTarget on


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SimParseCustomCode on

SimBuildMode sf_incremental_build

SimDataInitializer

SimGenImportedTypeDefs off


Property Value

Name Code Generation

SystemTargetFile grt.tlc

TLCOptions

CodeGenDirectory

GenCodeOnly off

MakeCommand make_rtw

GenerateMakefile on

PackageGeneratedCodeAndArtifacts off

PackageName

TemplateMakefile grt_default_tmf

PostCodeGenCommand

Description

GenerateReport off

SaveLog off

RTWVerbose on

RetainRTWFile off

ProfileTLC off

TLCDebug off

TLCCoverage off

TLCAssert off

ProcessScriptMode Default

ConfigurationMode Optimized

ProcessScript

ConfigurationScript

ConfigAtBuild off

RTWUseLocalCustomCode off

RTWUseSimCustomCode off

CustomSourceCode

CustomHeaderCode

CustomInclude

CustomSource

CustomLibrary


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Table 3.10. SDD_cont Configuration Set.Components(8).Components [19](1)

Property Value

Name Code Appearance

Description

ComponentsComment

ForceParamTrailComments off

GenerateComments on

IgnoreCustomStorageClasses on

IgnoreTestpoints off

IncHierarchyInIds off

MaxIdLength 31

PreserveName off

PreserveNameWithParent off

ShowEliminatedStatement off

OperatorAnnotations off

IncAutoGenComments off

SimulinkDataObjDesc off

SFDataObjDesc off

MATLABFcnDesc off

IncDataTypeInIds off

PrefixModelToSubsysFcnNames on

MangleLength 1

CustomSymbolStr $R$N$M

CustomSymbolStrGlobalVar $R$N$M

CustomSymbolStrType $N$R$M_T

CustomSymbolStrField $N$M

CustomSymbolStrFcn $R$N$M$F

CustomSymbolStrFcnArg rt$I$N$M

CustomSymbolStrBlkIO rtb_$N$M

CustomSymbolStrTmpVar $N$M

CustomSymbolStrMacro $R$N$M

CustomSymbolStrUtil $N$C

CustomCommentsFcn

DefineNamingRule None

DefineNamingFcn

ParamNamingRule None

ParamNamingFcn

SignalNamingRule None


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SignalNamingFcn

InsertBlockDesc off

InsertPolySpaceComments off

SimulinkBlockComments on

MATLABSourceComments off

EnableCustomComments off

InternalIdentifier Shortened

InlinedPrmAccess Literals

ReqsInCode off

UseSimReservedNames off

ReservedNameArray

Table 3.11. SDD_cont Configuration Set.Components(8).Components [19](2)

Property Value

Name Target

Description

Components

IsERTTarget off

TargetFcnLib ansi_tfl_tmw.mat

TargetLibSuffix

TargetPreCompLibLocation

GenFloatMathFcnCalls ANSI_C

TargetFunctionLibrary ANSI_C

CodeReplacementLibrary ANSI_C

UtilityFuncGeneration Auto

ERTMultiwordTypeDef System defined

ERTMultiwordLength 256

MultiwordLength 2048

GenerateFullHeader on

GenerateSampleERTMain off

GenerateTestInterfaces off

IsPILTarget off

ModelReferenceCompliant on

ParMdlRefBuildCompliant on

CompOptLevelCompliant on

ConcurrentExecutionCompliant on

IncludeMdlTerminateFcn on

GeneratePreprocessorConditionals Disable all

CombineOutputUpdateFcns off


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CombineSignalStateStructs off

SuppressErrorStatus off

ERTFirstTimeCompliant off

IncludeFileDelimiter Auto

ERTCustomFileBanners off

SupportAbsoluteTime on

LogVarNameModifier rt_

MatFileLogging on

MultiInstanceERTCode off

SupportNonFinite on

SupportComplex on

PurelyIntegerCode off

SupportContinuousTime on

SupportNonInlinedSFcns on

SupportVariableSizeSignals off

ParenthesesLevel Nominal

GenerateClassInterface off

ModelStepFunctionPrototypeControlCompliant off

CPPClassGenCompliant off

AutosarCompliant off

GRTInterface on

GenerateAllocFcn off

UseToolchainInfoCompliant on

ExtMode off

ExtModeStaticAlloc off

ExtModeTesting off

ExtModeStaticAllocSize 1000000

ExtModeTransport 0

ExtModeMexFile ext_comm

ExtModeMexArgs

ExtModeIntrfLevel Level1

RTWCAPISignals off

RTWCAPIParams off RTWCAPIStates off

RTWCAPIRootIO off

GenerateASAP2 off

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