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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
QorIQ™ Based Multicore LTE Layer 2 Software
Keith Shields
July 2009
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
LTE PHY Software3GPP Rel 8 -LTE
Physical Processing
Transport Processing
LTE L2 Software3GPP Rel 8 -LTE
X1 -S2
MAC/RLC
Freescale LTE System Enablement Overview: Software; Devices; AMC boards
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
M3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
Acceleration CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
CORENET FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
FABRIC
CONNECTIVITY
PCI ExpressRapidIO
etc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
M3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
LTE Support
Turbo Decode
ViterbiDecode
WIMAX Support
FFT/IFFT
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
e500Core3850Core
L2 Cache
AccelerationAC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
AC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
AC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
ACCELERATION CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
AC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
AC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
AC CELER ATION
CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
ACCELERATION CORENET FABRIC
CONNECTIVITYPCI Express
RapidIOetc.
10/100/1000EtherneteTSEC
QUICCEngine
SYSTEMFUNCTIONS
MEMORYCONTROL
L3 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
Pattern Matching
Decompression / Compression
Crypto Security
Table Lookups
Data Path ResourceManagement
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
e500Core
L2 Cache
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
PHYSICAL/DSP L2/MAC NETWORK IF
CONTROLLTE NODE B
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA U/D
Conv .RF
SmallSign.
RFPA
U/DConv .
RFSmallSign.
RFPA FPGA
PHYSICAL/DSP L2/MAC NETWORK IF
CONTROLLTE NODE B
MSC8156 P20/30/40x Enablement code developed to date is deployed in customer systems
Software “Reference”Software Reference
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
SRIOMessage
UnitDMA
PCIe
18-Lane 5GHz SERDES
PCIe SRIOPCIe
CoreNet™
1024-KbyteFrontsideL3 Cache
64-bitDDR-2 / 3
Memory ControllerP4080 Power Architecture™e500-mc Core
D-Cache I-Cache
128-KbyteBacksideL2 Cache
SRIO
WatchpointCrossTrigger
PerfMonitor
CoreNetTrace
Aurora
Real Time DebugSecurity
4.0
PatternMatchEngine
2.0
Queue Mgr.
Buffer Mgr.
eLBIU
M2SB
TestPort/SAP
Frame Manager
1GE 1GE
1GE 1GE10GE
Parse, Classify,Distribute
Buffer
32-Kbyte 32-Kbyte 1024-KbyteFrontsideL3 Cache
P4080 Multicore Architecture
64-bitDDR-2 / 3
Memory Controller
PAMU
Coherency FabricPAMUPAMUPAMU PAMU
1GE 1GE
1GE 1GE10GE
Parse, Classify,Distribute
Buffer
Frame Manager
Peripheral Access Mgmt Unit
eOpenPIC
Power Mgmt
2x USB 2.0/ULPI
SD/MMC
Clocks/Reset
DUART
2x I 2C
SPI
GPIO
PreBoot Loader
Security MonitorInternal BootROM
CCSR
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
Accelerating Customer Wireless QorIQ Development – It’s All About the Software
► Millions of lines of legacy LTE code need to be written in a parallel fashion to best utilize multi-core devices
► How to efficiently partition and run complex eNodeB functionality across a multi-core system
•SMP vs AMP vs LWE
•Scheduler, MAC, RLC, PDCP, IPSEC, GTP, SCTP……..
•Demonstrate Efficient and LTE SPECIFIC DPAA benefits
► Prove FSL QorIQ performance for LTE use-cases
•Understand and remove system bottlenecks
•Component benchmarks not sufficient, need full system functionality
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Single-threaded Legacy Software
CoreD-Cache I-Cache
L2 Cache
CoreD-Cache I-Cache
L2 Cache
CoreD-Cache I-Cache
L2 Cache
CoreD-Cache I-Cache
L2 Cache
Multicore Software
MPC8548
P4080P3xP2x
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
LTE Overview
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
3G Evolution and Architecture
► Radio Side (LTE – Long Term Evolution)• Improvements in spectral efficiency, user throughput, latency• Simplification of the radio network• Efficient support of packet based services
► Network Side (SAE – System Architecture Evolution)• Improvement in latency, capacity, throughput• Simplification of the core network• Optimization for IP traffic and services• Simplified support and handover to non-3GPP access technologies
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
LTE Protocol Stacks
PDCP
RLC
MAC
L1
PDCP
RLC
MAC
L1
GTP-U
UDP
L2
L1
IP/IPSec
GTP-U
UDP
L2
L1
IP/IPSec
GTP-U
UDP
L2
L1
IP/IPSec
UDP
L2
L1
IP/IPSec
GTP-U
IPIP
Application
LTE-Uu S1-U S5/S8 SGiPDN GWServing GWeNBUE
Relay Relay
RRC
RLC
MAC
L1
PDCP
RLC
MAC
L1
S1-AP
SCTP
L2
L1
IP/IPSec
SCTP
L2
L1
IP/IPSec
RRC
NAS
LTE-Uu S1-MMEMMEeNB
Relay
PDCP
S1-AP
NAS
Control Plane
User Plane
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
PDCP OverviewThe main services and functions of PDCP for the user plane include:
•Header compression and decompression: ROHC•Transfer of user data between RRC and RLC layers•Ciphering
The main services and functions of PDCP for the control plane include:•Ciphering and Integrity Protection•Transfer of control plane data between RRC and RLC layers.
IP Header Data
ROHC
Data
Cipher
Data
PDCP Header + Checksum
DataPDCP Header
CK
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
Protocol Stack Flow #1
Oct 1
Oct 2
Oct N
Oct N-1
Oct N-2
Oct N-3
...
Data
PDCP SNR R R
MAC-I
MAC-I (cont.)
MAC-I (cont.)
MAC-I (cont.)
Data from Network (01010101)
ROHC
Cipher (X%X$x)
RLC Header
Data
To MAC
PDCP
RLC
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
Protocol Stack Flow #2
LI2
E LI2
E LI1
LI1
D/C RF P FI E SN
SN
Data
Oct N
Oct 1
Oct 2
Oct 3
Oct 4
Oct 5...
LIK
E LIK
E LIK-1
LIK-1
Oct [2+1.5*K]
...
Oct [2+1.5*K-1]
Oct [2+1.5*K-2]
Oct [2+1.5*K+1]
MAC Header
Data
RLC MAC
To Layer 1 Phy
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
LTE Data Flow
RLC
RRC
MAC
PHY (DL-OFDM, UL-SC-FDMA)Layer 1
Layer 3
PDCP
MAC PDUs
RLC PDUs
PDCP Ctrl
MAC Ctrl
L1 Ctrl
Layer 2
PDCP PDUs
Physical Channels
Packet Network
PS NAS
RLC Ctrl
User Traffic
Radio Bearers
Logical Channels
Transport Channels
RRC PDUs
:20
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
LTE Data Flow
RLC
RRC
MAC
PHY (DL-OFDM, UL-SC-FDMA)Layer 1
Layer 3
PDCP
MAC PDUs
RLC PDUs
PDCP Ctrl
MAC Ctrl
L1 Ctrl
Layer 2
PDCP PDUs
Physical Channels
Packet Network
PS NAS
RLC Ctrl
User Traffic
Radio Bearers
Logical Channels
Transport Channels
DownlinkFlow
RRC PDUs
:20
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Freescale LTE Layer 2 Solution OverviewSoftware Support
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Freescale LTE Layer 2 Software DeliverablesCategory Specification / Features
RTOS Support •RTOS agnostic implementation •Example includes software ported to Linux user mode
API •Full software abstraction between data plane & control plane and data plane & scheduler through well-defined and documented APIs.
Validation/Test •Software tested on unit, integration and system levels •Software test environment is part of the software delivery package.
1.MAC - Medium Access Control Layer
•Compatible to standard: 3GPP 36.321 (MAC) (V.8.3.0)•Includes sample downlink / uplink scheduler
2. RLC - Radio Link Control
•Compatible to standard: 3GPP 36.322 (RLC) (V.8.3.0)
3. L2/L1 interface •Implements an efficient L2/L1 interface designed for seamless integration with Freescale L1 solution (available today)•Easy L2/L1 interface, out-of-the-box experience through validated test cases.(over sRIO)
4. Framework •Example integrated processing chain running under Linux (available today):o Demonstrates integration of L2 moduleso Provides known development/test environment
5. PDCP -Packet Data Convergence Protocol
►Header •Full header implementation (including HO) available now
►ROHC & encryption
•RoHC - Available through third party (available today)• Provided with specific optimisations for Freescale architectures
•Air interface encryption (available today)• Algorithm implemented on SEC Engine
6.IPSEC Freescale Software (FastpathUTM), formerly Intoto
7.RRC •3rd party or customer development
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LTE Layer 2 Software Components
- Harness & Operating System: System level test harness utilizing operating system timers and ethernet stack- Scheduler: Priority based round-robin scheduler- Control: API to facilitate configuration and execution of core modules- PDCP: Packet Data Convergence Protocol as specified by 3GPP 36.323 - utilises 3rd party ROHC implementation- RLC: Radio Link Control as specified by 3GPP 36.322- MAC: Medium Access Control as specified by 3GPP 36.321- Common: Generic functionality utilised by multiple modules e.g. linked list implementation, TTI event Timers etc.- IF1 interface: Covers the protocol and LTE specific aspects of the DSP L1 interface
Control
PDCP Com
mon
Scheduler
Harness / Operating System
MAC
IF1
RLC
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LTE L2 Development Environment
KDBG Insight DDD
GDB
Standard CCodebase
GCCBinutilsMetrowerks
Linux
UBOOT
Linux
BIOS
Cygwin
BIOS
Development Tools
Run-Time Environment85xx x86 x86
Target Platforms
•Controller AMCs•8548/8572/P2x/P4xAMCs
•DSP AMCs•8144/8156AMCs
•Industry Standard Carriers•Pico/Micro TCA
•Proprietary Systems
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Freescale LTE Layer 2 QorIQ™
Solution OverviewSoftware Support
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►Multicore CPU's can permit a number of processing scenarios
LTE QorIQ OS Implementation
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Services
Light Weight Executive
Forwarding/ Data Plane Control Plane
Linux®
AMP SMPAMP
Linux® Linux®
We are benchmarking our LTE Layer 2 implementation to determine the optimal mix and fit for QorIQ architectures
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SMP/AMP Operating System
Hypervisor
Optimized High Speed Drivers
Freescale Multicore Silicon
Applications
Freescale
Cycle-Accurate
SMP/AMP Operating System
Hypervisor
Optimized High-Speed Drivers
Multicore Simulation Environment
IDE (com
piler / debugger / build tools)
Simulation to HardwareSame Software
Freescale-supplied SDK items
FunctionalAPI
Applications
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SRIOMessage
UnitDMA
PCIe
18-Lane 5GHz SERDES
PCIe SRIOPCIe
CoreNet™
1024-KbyteFrontsideL3 Cache
64-bitDDR-2 / 3
Memory ControllerP4080 Power Architecture™e500-mc Core
D-Cache I-Cache
128-KbyteBacksideL2 Cache
SRIO
WatchpointCrossTrigger
PerfMonitor
CoreNetTrace
Aurora
Real Time DebugSecurity
4.0
PatternMatchEngine
2.0
Queue Mgr.
Buffer Mgr.
eLBIU
M2SB
TestPort/SAP
Frame Manager
1GE 1GE
1GE 1GE10GE
Parse, Classify,Distribute
Buffer
32-Kbyte 32-Kbyte 1024-KbyteFrontsideL3 Cache
P4080 Datapath infrastructure blocks: Queue and Buffer managers
64-bitDDR-2 / 3
Memory Controller
PAMU
Coherency FabricPAMUPAMUPAMU PAMU
1GE 1GE
1GE 1GE10GE
Parse, Classify,Distribute
Buffer
Frame Manager
Peripheral Access Mgmt Unit
eOpenPIC
Power Mgmt
2x USB 2.0/ULPI
SD/MMC
Clocks/Reset
DUART
2x I 2C
SPI
GPIO
PreBoot Loader
Security MonitorInternal BootROM
CCSR
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DPAA Pool Channel Implementation
Frame Queues
Power Architecture™Core
D-Cache I-Cache
L2 Cache
portal
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
portal portal
channel
WQ
0
channel channel
WQ
1
WQ
2
WQ
3
WQ
4
WQ
5
WQ
6
WQ
7
WQ
0
WQ
1
WQ
2
WQ
3
WQ
4
WQ
5
WQ
6
WQ
7
WQ
0
WQ
1
WQ
2
WQ
3
WQ
4
WQ
5
WQ
6
WQ
7
QMAN Dedicated Channel
Linux Control Partition Control Path
DoorbellsShared MemoryINBAND – Via FQ’s
Classify
QMANPool Channel
PDCP/RLC/MAC/SchLightweight Executive
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MAC
Multicore Software Partitioning
Fixed Partitioning Dynamic Load Balancing
MAC/RLCPDCP
Scheduler
IPSEC
SchedulerScheduler
SMP LinuxSMP LinuxSMP Linux
SMP Linux
PHY
eNodeB
RRC
PDCP
RLC
Small fixed function LWE kernel with high icache hit ratio
Large Multifunction kernel with lower icache hit ratio but with
dynamic load balancing
LinuxLWE
IPSEC
L2/L1
GTP SCTP
UDP TCP
IPSingle LWEApp
SMP LinuxIPSEC
SMP Linux
Sch
MACRLC
PDCP
Core #1
Core #8
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Traditional LTE L2 Downlink vs. DPAA solution
PDCP
RLC
MAC
IF1
L1
SCHEDULER
ROHC
DE/CIPHER
INTEGRITY
UE
DE/COMPRESSIONReduces Payload &
increases throughput
DE/CIPHERING Provides security
INTEGRITYEnsures data is
relevant & non-corrupt
GTP
IPSEC
Traditional Implementation (Linux SMP)•Potential Buffer Copy•Synchronization/lock Point
DPAA LWE run to completion implementation (objective: offload e500mc cores)• Buffer copies are replaced by DPAA enqueue / dequeue operations• Locking/synchronization is handled in hardware.
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System Partitioning / Initialization
►DPAA partitioning and initialization is driven by the Linux device tree which is passed to both the hypervisor and guest OS’s on startup.
►The device tree is Power.org ePAPR compliant with extensions to support the new DPAA features.
►The device tree details• Partitioning of cores i.e., Linux/LWE. • Physical Memory Areas.• Allocation of all Phyiscal resources – eg. Network ports, serial ports etc• Portals• BMan Pools• FQ Allocation• etc …
►The Hypervisor parses the device tree and allocates resources as required.
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
P3 is held until P2 is processed through the ORP
P2 processing time is greater than P1 or P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2 P1P3
In order arrival of 3 packets Packet order is preserved
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2 P1P3
In order arrival of 3 packets Packet order is preserved
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2P1
P3
In order arrival of 3 packets Packet order is preserved
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2
P1
P3
In order arrival of 3 packets Packet order is preserved
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
P3 is held until P2 is processed through the ORP
P2 processing time is greater than P1 or P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2
P1
P3
In order arrival of 3 packets Packet order is preserved
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ODP/ORP PDCP Example
P3
P2
P3 P1
ODP ORP
Parallel Processing ElementsCores
P2
P3
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P1
Power Architecture™Core
D-Cache I-Cache
L2 Cache
Power Architecture™Core
D-Cache I-Cache
L2 Cache
P2P1P3
In order arrival of 3 packets Packet order is preserved
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QMan Software Portal components
Software portals have 4 components Dequeue: Command registers + DQRR Enqueue: EQCR Messages: MR
Asynchronous error messages (e.g. enqueue rejections) Management commands: command/response registers
Interrupts can be used to signal availability of data or space (in EQCR)
Rings provide finite size FIFOs Up to 16 entries for DQRR, 8 entries for EQCR and MR
Portal components are implemented inside QMan to reduce access latency Unlike traditional BD rings which are in “memory” and “registers”
QMan can “push” (stash) DQRR entries across Corenet into the appropriate core’s cache
PI and CI are the basic mechanisms used with rings but other forms of notification of data availability and data consumption are supported
When these other mechanisms are used QMan maintains PI/CI
Dequeue Response Ring (DQRR)
Enqueue Command Ring
(EQCR)
… …
Dequeue Commands
N Cores
QMan
PI
CI
PI
CI Management Command/Response
Registers
Message Ring(MR)
…
PI
CI
Dequeue Interface
Interrupts
Enqueue Interface
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PDCP QMan Stashing Example QMan can stash DQRR entries
across Corenet into the appropriate core’s cache. The stash size 0 -> 3 Cache lines ( 64 bytes) can be set for the following components on FQ creation.
Frame Data Actual Packet Data
FQ Context Per Queue Context Data ie PDCP user
context, Sequence Numbers, ROHC context, Cipher keys etc ….
Frame Annotation Per Packet Context Data ie Mapping of
PDCP Bearer ID to internal structures.
Dequeue Interface
Dequeue Response Ring (DQRR)
…
Dequeue Commands
PI
CI
Interrupts
Core
QMan
Power Architecture™Core
D-Cache I-Cache
L2 Cache
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Example DPAA main() for FQ Creation and Dequeue
Main(){
..
.. Init .. fq = qm_new_fq(g_qm_portal,
fq, channel, priority, pdcp_dl_context, 0, 0, 0, MT_SHARED, 0);
..
while (1) {if (entry = qm_dq_dqrr_entry(g_qm_portal)) {
context = (struct lte_context *)(entry->contextB); context->handler(context, entry); qm_dqrr_cci_consume(g_qm_portal->p, 1);
} else {idle_loop();
}}
}
Frame Queue Creation sets the system connectivity. FQ’s have a number of attributes whichdetermine run time behaviour ie HELD ACTIVE, ORP/ODP
Processing is “data” driven - By the time data arrives at the core we do not need to parse channel, priority, FQ as data processing is driven by context
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Comparison of example LTE Data handler()
void pdcp_dl(struct pdcp_dl_context_t *context, struct qm_dqrr_entry *entry) { SBL2_BUFFER_T buffer; struct qm_fd fd;
buffer.length = fd.length20 - ETH_HLEN; buffer.data = (uint8_t *) ptov_dpa(fd.addr_lo); buffer.offset = fd.offset + ETH_HLEN; if (SBL2_PDCP_DL_DataTransfer(&(context->bearer), &buffer)) {
fd.length20 = buffer.length; fd.offset = buffer.offset; qman_enqueue_performance(g_qm_portal, RLC_CHANNEL, &fd, 0, 0);
} else { printf("PDCP DL Drop Packet.\n");
}
void pdcp_dl(UINT16 bearer_id, UINT8 *sdu, UINT16 sdu_length){SBL2_PDCP_RADIO_BEARER_T *bearer = &SBL2_PDCP->raidio_bearer[bearer_id]);
pdu = SBL2_GetBuffer();LOCK(&(bearer->mutex);MEMCPY(sdu,pdu, sdu_length);SBL2_PDCP_DL_DataTransfer(bearer, &pdu, sdu_length); UNLOCK(&(bearer->mutex);
}
P4080 DPAA based PDCP Handler
Abstraction of the bman buffer to SBL2_BUFFER_T type allows the same SBL2_PDCP_DL_DataTransfer code to be reused for Linux/SMPLinux/LWE/RTOS
Linux SMP based PDCP HandlerAlthough simpler the original code has a buffer allocation/copy and mutex lock around the data processing
Linu
x SM
Pap
proa
chLW
E R
un to
Com
plet
ion
appr
oach
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LTE Layer 2 Summary
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LTE Layer 2 Code Summary
►Evolving multicore code set derived from “mature” single core base.►Code developed to date has the benefit of deployment “feedback”.►Robust software development and management process
established.►Simulation environment facilitating early code development.►Multicore code generation is underway.
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Q&A
►Thank you for attending this presentation. We’ll now take a few moments for the audience’s questions and then we’ll begin the question and answer session.
TM