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160 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO 1,
FEBRUARY 1988v~,JAS5
fzii-g MloS3 S3
Mll Mlz
L-JAS4 S5Fig
bv~*1. The dynamic latch
The transconductance isTherefore
(gm, + gin,) =
given by gm = {21LC4(W/L. ).
Thus(gin, +gm2)2= G:. (5)
Equation (5) shows that if the total power and area areheld
constant, the total transconductance is also constant.B. Comparator
Architecture
The dynamic latch (Fig. 1), often used as a sense ampli-fier in
dynamic RAMs, is a fast CMOS comparator.However, its large offset
voltage limits its resolution toabout 5 bits. A linear amplifier
may precede the dynamiclatch so that the voltage applied to the,
latch is largeenough to overcome this offset. Since a linear
amplifiercan be offset-cancelled, medium-resolution ( = 8-bit)
con-verters are possible.
Fig. 2 shows the comparator block diagram, which con-sists of a
dynamic latch preceded by an offset-cancelledamplifier [5]. The
Qfset-cancellation cycle begins bythrowing the switch SI to ground
and closing the switchS1. The offset-cancellation amplifier (g~2)
forces its offset(V0,2) and the offset (VO~l) from the high-gain
amplifier(g~l) onto the offset-cancellation capacitors COCIand
COC2.This voltage VOff is given by
R L ( grnl%l + b%%Voff = )1+%2RL
(6)
The input-referred offset voltage VO, is reduced by the
9ml(vln-vref) Fv DIn -0 ?L Q:: YLUL OAVref - s, RO A ~; RT QCw
AC
Fe / EEIH :H
R c
*w, Vpass9m2v0f fco:, -Voffs, tr +coc~ ~Fig. 2. The comparator
block diagram,
Fig. 3. A one-stage single-pole amplifier
voltage gain of the high-gain amplifier and is given byRL(%lvml
+ gm2vos2Vo,f = )
%lRL(I+ gW2RL) (7)
The amplify cycle begins by throwing the switch ~ tosample the
input voltage and opening the switch S1. Now,the amplifier output
voltage VP=, is a rising exponentialwhose final value is the
product of V,n V,,~ and thevoltage gain gnlR L.
Once the voltage VP=, is large enough (about 50 mV),the dynamic
latch is enabled. Since it has positive feed-back, it is able to
amplify the pass voltage to near logiclevels in a short period of
time. Then the storage latch isturned on to hold the result until
the encode logic isenabled.C. Motivation for Offset
Cancellation
The initial motivation for offset cancellation is clear:without
it, an MOS comparator could not resolve smallenough voltages so
that it could be used in a medium-reso-lution ADC. Since it takes a
finite amount of time tocomplete the offset-cancellation cycle
before the compara-tor can be enabled, it seems that the comparator
responsetime must be increased. However, if the
offset-cancellationcycle is pipelined with the dynamic latch cycle,
it does notdegrade the response time.
Consider the simple one-stage, single-pole amplifiershown in
Fig. 3. The step response for the amplifier isgiven byVOUt(t) =
[g~R~V,n(O+ )(1 e-/c))
1(4)-VOU,0) e-t/RLc u t)
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0.2 I , I t T I I 1 1 I 1 , Thresho ld =50mV /
0,15 A .20 /----- A. ,50 / .---?z - AV =80 ./:.. --
.,0 >. ,,--?-0,05
/o : ,/ I I , 1,11)11,,1-0 I 2 3 4 5T ime (nsec )
(a)0.20.15 Threshold =50mV Av =20o. I0,05
0-0.05-0.1-0.150.2 0 I 2 3 4 5T ime (nsec)
(b)Fig. 4. (a) One-stage amplifier step response for I&(0)=
O. (b) One-stage amplifier step response for J&t (0) = 0.15
V.
The first term is a rising exponential with the
magnitudedetermined by the voltage gain g~R~ times the input
stepVi~(O+ ). The second term is just the exponential decay ofthe
residual voltage from the last comparison V(QUt(0).Consider the
one-stage amplifier for two cases. First,
assume that the initial output voltage VOUt(0) is zero andthat
,the following conditions hold: g~ = 0.001 S, CL= 100fF, F,.(o + )
= 5 mV, and that the voltage gain is variedfrom 20 to 80 by
adjusting R ~. The result is shown in Fig.4(a). For any time t, the
highest-gain configuration hasamplified the 5-mV input voltage into
the largest outputvoltage. For small t, the slope of the step
response for eachconfiguration is given by g~ /C~ so that the
response timecan be improved by increasing g~ or decreasing CL and
isindependent of R L (only for t
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162 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1,
FEBRUARY 1988
The optimum comparator response time can now be de-termined for
a given power and area constraint.2. Single-Stage Amplifier Plus
Source Follower: By add-
ing a source follower, the latch capacitance is bufferedfrom the
high-gain amplifier at the expense of adding somegroup delay. Also,
the source follower has the addedbenefit of buffering the high-gain
amplifier from thekickback charge of the dynamic latch.The step
response for the single-stage amplifier plus
source follower is approximated by()mgml ~ _ cLatchv=~ u(t)
(15)pass pl gm3
determined in terms of G,.. Thusml%=izig,,ll =
l+l%zi+G
(21)g,,,2 = +ti+lzz
(22)where gm3 is the source-follower transconductance. Thetime
delay is thus
v Cp, c~atc~pass+d= Vi. g~~ (16)gm3
and the comparator response time is given by
v C,l cLatc~ CP1+ Coc~r=2!s-+ +Min gml
(17)gm3 gm2
Since the total transconductance G~ must be held con-stant, then
g~3 = Gm g~l g~z. Therefore, (17) becomes
/cGn, LatchM(CP1 + Coc)
3=1+%zrz+L5(23)Once the optimum transconductances are known,
theycan be substituted back into (17) to determine the opti-mum
comparator response time for the single-stage plussource-follower
configuration.3. Two-Stage Amplifier Plus Source Follower:
Taking
this a step further, consider two single-pole amplifier
stagescascaded together and buffered by a source follower.
Thetransconductance for the two gain stages must be dividedby two
in order to keep the total transconductance con-stant. If the
parasitic capacitance CPI is domiriated by gatecapacitance, it must
also be divided by two. The resultingpass voltage can be
approximated by
By taking separate partial derivatives of (18) with respectto
g~l and g~ z and setting them equal to zero, the
vp=,=:(~)2(t-R)2u(t). (24,following relationship results:
The time delay isp11=gm2Ez3=1)In order to determine the
relationship between g~~ andLa. substitute g-, = G,,, f!~j %, into
07). Then takeseparate partial derivatives of t,with respect to g~3
andg,,,z and set them both equal to zero. Solving this
resultgives
{c Latchgm3 = gm2 M(CP1 + co. )
(20)
By taking (19), (20), and remembering that g~l + gw,~+gm,q=
G,,,v the three individual transconductances can be
The comparator response time is given by
=FEla+%+Mc2Note that (26) is the same as (17) with VPa,,/ V,.
re-
placed by ~=. Therefore, the optimum transcon-ductances ~an be
determined by making the above sub-stitution into (21)(23). Then,
these transconductances canbe substituted into (26) to determine
the optimum com-parator response time for the two-stage plus
source-fol-lower configuration.
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4 : I I I I J2 E ----- I Stoge+ SourceFollower-2 Stoges t Source
Followero864
:~o 0.02 0.04 006 0.08 0. [Vpo$s (volts)Fig. 6. Optimized
comparator response time for three high-gain amph-fier
configurations for CPI = 200 fF, C~l,ch = 300 fF, COC= 200 fF,V,n =
10 mV, and G~ = 1 mS.
4. Amplifier Optimization Results: Fig. 6 shows the opti-mized
time delay td versus pass voltage Vp,,, for the threeamplifier
configurations considered above. It is interestingto note that the
fastest amplifier configuration depends onthe desired pass voltage.
For pass voltages between O and45 mV, the single-stage amplifier is
fastest; for pass volt-ages between 45 and 80 mV, the single-stage
amplifiersource follower is fastest; for pass voltages greater than
80mV, the two-stage amplifier is fastest; etc. If a large
passvoltage were desired or if the input voltage were smaller (itis
10 mV in this example) higher order amplifiers becomeoptimum. For
an 8-bit ADC with a dynamic range of2.5 V, 10 mV corresponds to 1
LSB and, as will be shownin the next subsection, 50 mV is the
optimum pass voltage.Therefore, the one-stage amplifier plus source
follower isthe optimum amplif ier conf iguration.E. Dynamic Latch
OptimizationIt was previously mentioned that the dynamic latch hasa
large offset voltage. Unlike the offset of the high-gain
amplifier, it is difficult to cancel the dynamic latch
offset.Therefore, it is important to understand the origin of
thisoffset so that its effects can be minimized.Consider the
dynamic latch shown in Fig. 1. Assume
that the initial voltage VP.,, has been applied by closingand
then opening S3. The switches S5 are initially openedand switch S4
is thrown to the right. Since no current canflow through them,
transistors 114gand J410 are initiallyoff. Either or both
transistors Mll and Nllz are on and thesmall-signal voltage across
their gates is given by
~out = ( ~pa~, ~o,) 6? gmLatch/c
where the offset voltage VO~is assumed to opposevoltage VPa~.
The dynamic latch response timegiven by
CL () in outt Latch= g. v pass Vo, Latch
20 I I I I r18 ,~16 1 toc: 14 1 . - ---- fLatchc-=[2 ,;10-~ 8 ,
~.v ..~6 ..>> . . . .-: 4 .- -----2 - -- -- -- - . .. -.
--~~
o I I , I , , , I Io 0.02 0.04 0.06 0,08 0.1VP9SS (volts)
Fig. 7. Latch and offset-cancellation amplifier response times
versuspass voltage for C ~ = 200 fF, C~a,Ch= 300 fF, CO, = 200 fF,
P&= 10mV, Gm=l mS, #=10 pm, L=2 pm, and AL= 0,1 pm.
voltage is given byIAK AKVO, = Au + = AK + C (29)&hL.t&K
4K2 -
By taking the partial derivative of t~a,chith respect
tog??!=.,=,and setting it equal to zero, the optimum responsetime
for a dynamic latch with a worst-case opposing offsetvoltage can be
determined:at Latch c Latch 1 a Vo,dgmLa,ch= gm=atc, VP,., Vo,
I?gmL,,ch
c()
v= in out = o. (30)d vLatch pass V*,Since from (29)
dVO, AK~gm.a,ch= 4K 2 (31)
and sinceAK AL= K L (32)
(30) becomesatLatch AL=0=~fkatch
(gm,atc,AL4KL VPa,, AK 4KL )
1 \1
1
vin outI
AL (33)(27) mLatch Vp=, _ Afi _ mL.lch _4KL
the pass Equation (33) can be solved iteratively for the
optimumt Latch 1s gm ~ which can be substituted into (28) to obtain
theop~~um tL,,ch.ince the dynamic latch-response time
t~,tchmust fit into the offset-cancellation time t.C,the(28)
optimum pass voltage VPa~~can be found by plotting theoptimum
tLatchand t.Cwith respect to VP.,, and noting
where they intersect. This is done in Fig. 7 for VOUt= 1 V.Using
the square law approximation for an MOS transistor An optimum pass
voltage of 50 mV has been chosen in ourId= K(V~, ~)2 where K =
(pCOx/2)( W,/L) the offset design.
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.,-. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1,
FEBRUARY 198804After a few nanoseconds, the switches S5 are
closed
(Fig. 1) and the differential output of the dynamic latchquickly
approaches logic levels. Then, the storage latch isenabled to hold
the result.
III. CIRCUIT DESCRIPTIONFor an 8-bit flash ADC it has been shown
that the
optimum topology consists of a single-stage amplifier plussource
follower, an offset-cancellation amplifier, a dy-namic latch, and a
storage latch as shown in Fig. 2. Adetailed discussion of the
circuit implementation of theseblocks in now given.Fig. 8 shows the
high-gain amplifier plus source follower
and the offset-cancellation amplifier. The differential
pairconsisting of transistors Ml and Mz constitutes the high-gain
amplifier. Transistors M5 and M6 make up theoffset-cancellation
amplifier. Since the drains of Ml andMz connect to the drains of M5
and M6, both the high-gainamplifier and the offset-cancellation
amplifier are cascodedby transistors M3 and Md. This increases the
outputresistance of the amplifiers, thus increasing the
voltagegain. It also reduces the Miller effect, thus improving
thecomparator response time. Transistors MT and M8 are thesource
followers.To insure that transistors Ml throug~ ~~ in the high
gain and offset-cancellation amplifiers are all operating inthe
saturation region, a simple common~mode feedbackcircuit is
employed. The high impedance nodes of eachdifferential amplifier
are tied to the gates of source fol-lowers. The output current of
these two source followers issummed into a diode-connected
transistor producing avoltage CMFB. This voltage is tied to the
gate of thecurrent source transistor for the differential pair. The
sumof the currents from these source followers remains con-stant
with a small signal differential voltage at the highimpedance
nodes. If a common mode voltage appears atthe high impedance nodes,
the sum of the source followercurrents causes a change in voltage
CMFB to return thecommon mode voltage near O. This common mode
feed-back circuit has only one pole and therefore is unity
gainstable without compensation. A more complete explana-tion of
this circuit is discussed in [6].The dynamic and storage latches
are shown in Fig. 9.
Transistors Mg through Mlz are the dynamic latch andtransistors
ML3 through M16 make up the storage latch.The dynamic latch is
first turned on slowly by throwingswitch Sa to the right. The
current source 1 is chosen toestablish the optimum g~,,,C~.After a
few nanoseconds, theS5 switches are closed to quickly bring the
dynamic latchoutput near logic levels.A tri-state inverter
separates the two latches. It is en-
abled one-half of a cycle after the dynamic latch is en-abled.
Then, switches designated by Se are closed and thestorage latch
holds the result until the encode logic isenabled.
~dd
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Fig. 11. Comparator response to a 1.44-MHz sine wave while
beingclocked at 23 MHz.
Fig. 12. Comparator noise and hysteresis while being clocked
at23 MHz.
Fig. 12 shows the comparator noise and hysteresis byapplying a
triangle wave to both the comparator input andthe X axis of the
oscilloscope. The 10-mV noise window isdue mostly to clock
feedthrough in a track and hold thatprecedes the comparator. Two
complementary strobes areneeded to control the track and hold.
Since one is bufferedon chip and the other is not, truly
complementary strobesare not being applied internally.
A 2-pm CMOS flash ADC using the comparator archi-tecture
discussed here is being fabricated. The clockfeedthrough in the
track and hold is reduced by the use ofon-chip clock generation.
The 2-~m comparator used inthe flash ADC has the dimensions 130 pm
by 500 pm.
V. CONCLUSIONSA CMOS comparator design and optimization
proce-
dure has been developed for use in an ADC. A dynamiclatch
preceded by an offset-cancelled amplifier has beenused to build a
fast and precise comparator. The use ofpipelining within the
comparator enabled the offset-cancel-lation and latch functions to
be accomplished simulta-neously. In addition, an optimal
distribution of power andarea within the amplifier was developed so
that the com-parator response time was minimized.
Using a 3-pm CMOS process, a single comparator hasbeen built and
tested. It operated at a minimum responsetime of 43.5 ns with a
noise and hysteresis window of10 mV that is limited by clock
feedthrough in the inputtrack and hold.
[1]
[2]
[3]
[4]
[5]
[6]
165
ACKNOWLEDGMENT
Special thanks to L. Weaver for his initial work.
REFERENCESA. Matsuzawa, A. Kanda, M. Kagawa, and H. Yamada, A
200Msps 8-bit A/D converter with duplex gray coding, in Proc.
Symp.VLSI Circuits, May 1987, pp. 109-110.Y. Yoshii, M. Nakamura,
K. Hirasawa, A. Kayanuma, and K.Asano, An 8b 350-MHz flash ADC~ in
ISSCC Dig. Tech. Papers,Feb. 1987, pp. 96-97,Y. Akazawa, A. Iwata,
T. Wakimoto, T. Kamato, H. Nakamura, andH. Ikawa, A 400 MSPS 8b
flash AD conversion LSI, in LSSCCDig. Tech. Papers, Feb. 1987, pp.
98-99.T. Tsukada, Y. Nakatani, E. Imaizmni, Y. Toba, and S.
Ueda,CMOS 8b 25 MHz flash ADC, in ZSSCC Dig. Tech. Papers,
Feb.1985, pp . 34-35.M. Degrauwe, E. Vittoz, and L Verbauwhede, A
micropowerCMOS-instrumentation amplifier; IEEE J. Solid-State
Circuits, vol.SC-20. rm. 805-807. June 1985.. . .J. W. Scott, W. L.
Lee? C. H. Giancarlo, and C. G. Sodiui, CMOSimplementation of an
Immediately adaptive delta modulator, IEEEJ. Solid-State Circuits,
vol. SC-21, pp. 1088-1095, Dec. 1986.
Benjamin J. McCarroll was born in Ontario, OR,on November 10,
1960. He received the B.S.degree from the University of Idaho,
Moscow, in1983. In 1985 he began attending the Massachu-setts
Institute of Technology, Cambridge, wherehe received the S.M.
degree in 1987.
For two years beginning in 1983, he workeddesigning spectrum
analyzers for Tektronix,Beaverton, OR. He is currently working in
theLab Instruments Division of Tektronix where hedes igns
high-speed integrated c ircuits.
Charles G. Sodini (S80-M82) was born in Pitts-burgh, PA, in
1952. He received the B. S.E.E.degree from Purdue University,
Lafayette, IN, in1974, and the M. S.E.E. and Ph.D. degrees fromthe
University of California, Berkeley, in 1981and 1982, respect
ively.He was a member of the technicrd staff atHewlett-Packard
Laboratories from 1974 to 1982,where he worked on the design of MOS
memoryand later on the development of MOS deviceswith very thin
faculty of the Massachusetts Institute ofgate dielectrics. He
joined theTechnology, Cambridge , in 1983,
where he is currently an Associate Professor in the Department
ofElectrical Engineering and Computer Sciences. His research
interests arefocused on IC fabrication, device modeling and
device-level circuit de-sign, with emphasis on analog and memory
circuits.
Dr. Sodini has served on a variety of IEEE Conference
Committeesincluding the International Electron Device Meeting of
which he is the1987 Techn ica l Program Vice Chairman.
Hae-Seung Lee (M85) was born in Seoul, Korea,in 1955. He
received the B.S. and M.S. degrees inelectrical engineering from
Seoul National Uni-versity, Seoul, Korea, in 1978 and 1980,
respec-tively. He received the Ph.D. degree in 1984 fromthe
University o f Califo rnia, Berkeley.
In 1980, he was a Member of the TechnicafStaff in the Department
of Mechanical Engineer-ing , Korean Institute of Science and
Technology,where he was involved in the development
ofelectro-mechanical systems. In 1984. he ioined
the faculty of the Massachusetts Institute of Technology,
Cam&idge,where he is now an Assistant Professor. Since 1985, he
has acted asConsultant to Analog Devices Semiconductor and Lincoln
Laboratory.His research interests include CMOS and BiCMOS
integrated circuits, ICfabrication technologies, and so lid-state
sensors.
