pspice model for flicker noise.pdf

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2000 1293

SPICE Models for Flicker Noise inn-MOSFETsfrom Subthreshold to Strong Inversion

Dingming Xie, Mengzhang Cheng, and Leonard Forbes

Abstract—The two main sources of low-frequency flickernoise are mobility fluctuations and number fluctuations. Ourexperiments on NMOS noise measurements were done from sub-threshold to saturation region of operation for both long-channel(5 m) and short-channel (as small as 0.6 m) NMOS transistors.The results suggest that for both types that in the saturationregion, the flicker noise is due to the surface state effect andthe noise equations, NLEV= 2 and 3, in SPICE, HSPICE, andPSPICE are most appropriate. For short-channel devices, dueto the effects of velocity saturation and the resulting nonlineartransconductance ( ) variation with gate bias voltage, theinput-referred voltage noise increases as the gate-source voltageincreases instead of staying constant as it does for long-channeldevices. In the subthreshold region, the input-referred voltagenoise decreases drastically as the gate-source voltage increases forboth long-channel and short-channel NMOS devices. Simulationshave been done using PSPICE and HSPICE, with noise level(NLEV) = 3 and device model level 3 and BSIM 3.2 and 3.3. Theresults from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICElevel 3 compare favorably with the measured noise phenomena forthe short-channel and long-channel NMOS devices, respectively.

Index Terms—BSIM 3.3, drain current noise, HSPICE, input-re-ferred noise, measurement, NMOSFET, 1/ noise, PSPICE, satu-ration, simulation, subthreshold.

I. INTRODUCTION

F LICKER noise is also known as 1/ noise, becausethe noise spectral density is inversely proportional to

frequency. It is a major noise source in silicon MOSFETs,especially in the low-frequency range, so in order to improvethe MOS circuit’s dynamic range and get better circuit per-formance, a circuit designer must be able to understand thephysical origin and model the behavior of the flicker noise.

Unfortunately, there is no universally accepted theory for thesource of the flicker noise although a lot of work has been donesince 1957 [1]–[4] including that of our previous companionpaper [42]. The carrier density fluctuation model, also calledMcWhorter number fluctuation model, attributes that the flickernoise to the tunnelling of free-charge carriers into oxide trapsclose to the Si-SiOinterface. The input referred voltage noiseis independent of the gate bias voltage and the magnitude ofthe noise spectra is proportional to the interface trap density.This assumes and is of course only true if the density of inter-

Manuscript received March 15, 2000; revised May 18, 2000. This paper wasrecommended by Associate Editor W. Schoenmaker.

The authors are with the Electrical and Computer Engineering, Oregon StateUniversity, Corvallis, OR 97331-3211 USA.

Publisher Item Identifier S 0278-0070(00)09152-1.

face/oxide traps is constant with the Fermi level position. Ex-perimental data reveals that the slopeof the 1/ noise spectravaries from 0.7 to 1.2, instead of being exactly one.

The mobility fluctuation model, also called Hooge mobilityfluctuation model, postulates that the stochastic nature of carrierscattering events cause the low-frequency noise. It has a gatebias voltage dependence of the input-referred voltage noise.

Inconsistent experiment results have been published for bothNMOS and PMOS devices. Different models have thus beenintroduced into different versions of SPICE (SPICE, HSPICE,and PSPICE) for the 1/noise of MOSFETs. There is also nosuggestion as to which equation is more appropriate for eitherNMOS or PMOS devices, nor under what kind of condition it isappropriate to use, the long-channel or short-channel models.

Our previous paper has simply showed that in saturation re-gion, the flicker noise in the short-channel (0.6m) NMOS tran-sistors is due to the McWhorter number fluctuation model, and agood match between the SPICE simulations with the NLEV2and 3 noise equation and the measurements had been achieved.

In this work we try to more carefully ascertain which modelis most appropriate for both long-channel (5m) and short-channel (1.2-m and 0.6 m) NMOS transistors under bothsubthreshold and saturation operating conditions. Section II ex-plains how we experimentally measure the flicker noise. Sec-tion III shows the PSPICE simulation for the flicker noise byusing a model based on the experimental results. Sections IVand V give the results and conclusions, respectively.

II. -MOSFETNOISE MEASUREMENT

The work was initially addressed at large micrometer sizeNMOS devices (5-m channel length) experimentally and bysimulation in saturation region, then moved on to the more dif-ficult problems of sub-micrometer devices (0.6-m and 1.2- mchannel length) and subthreshold models.

The experimental measurement setup has been described inour previous paper. The flicker noise at 1 Hz measured usingan automated system and the noise measured at 1 kHz by ananalog system have been compared to check the accuracy ofthe measurements. Please refer to [42] for details. The NMOStransistors to be measured are: 1) long-channel transistors with

120 m, 5 m, VTO 1.4 V and 1050 Å;2) short-channel transistors, including 1.2m ones with30.8 m, 1.2 m, VTO 0.7 V and 100 Å, and 0.6

m ones with 30.8 m, 0.6 m, VTO 0.7 V and100 Å.

0278–0070/00$10.00 © 2000 IEEE

1294 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2000

Fig. 1. Measured and simulated dc characteristics of the 5-�m NMOS transistors. SPICE level 3 to simulate whenT = 1050 Å andKP = 22�A/V .

Fig. 2. Measured and simulated dc characteristics of the 0.6-�m NMOS transistors. PSPICE level 7 (BSIM 3.3) to simulate whenT = 95 Å andKP = 50�A/V .

III. -MOSFETNOISE SIMULATION

Device model levels, level 3, BSIM3.2 (i.e., level 6 in PSPICEand level 47 in HSPICE) and BSIM 3.3 (i.e., level 7 in PSPICE)are tried for long-channel and short-channel devices, respec-tively, to fit their experimental dc characteristics, including thedrain current, , and the transconductance, . The parame-ters in the models, such as the oxide thickness, , and theintrinsic transconductance parameter, , are adjusted for thebest match. Once the appropriate model is found for each in-dividual device, the noise characteristics can be simulated ac-cording to the noise experimental results using the appropriatenoise equation selector (NLEV, or NOIMOD), flicker noise ex-ponent (AF) and coefficient (KF) in SPICE (see Appendix fordetails about the device models and noise models).

IV. RESULTS AND DISCUSSIONS

Both long-channel ( 5.0 m) and short-channel devices( 1.2 m and 0.6 m) have been measured in both the satu-ration and the subthreshold regions of operation.

Part of the results and explanation can be referred to Figs. 2,3 in [42]. The SPICE simulations show that the device modellevel 3 is more appropriate for the long-channel transistors (seeFig. 1), while level 7 in PSPICE version 8.0, i.e., BSIM 3.3 ismost appropriate to model the dc characteristics of the short-channel devices (shown in Fig. 2 for 0.6-m NMOS only). Theparameters used are: 1050 Å and 22 A/V for5- m NMOS devices; and 95 Å and 50 A/Vfor both 1.2- m and 0.6- m NMOS devices. As we will seelater, the measured input-referred noise results shows that the

XIE et al.: SPICE MODELS FOR FLICKER NOISE IN -MOSFETs FROM SUBTHRESHOLD TO STRONG INVERSION 1295

Fig. 3. Simulated and measured NMOS drain current noise versus absolute gate-source voltage in the saturation region.L = 5.0, 1.2, and 0.6�m, respectively.f = 1 Hz.

Fig. 4. Simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage in the saturation region.L = 5.0, 1.2, and 0.6�m,respectively.f = 1 Hz.

noise model, NLEV 3 with AF 1 in SPICE simulation ismost appropriate.

Thus, the measured noise results have been compared to thesurface state model for noise in SPICE, NLEV3 with AF1, using the device model level 3 for the long-channel, 5-mdevices, and the BSIM 3.3 (level 7 in PSPICE version 8.0) forthe short-channel, 1.2-m and 0.6- m devices. The KF valueis 1.05 -23 V F for the 5- m NMOS devices, and 1.0-24V F for the 1.2- m and 0.6- m NMOS devices. Within thesame process and technology, in our case for the 0.6 and 1.2 mi-crometer devices the average noise increases for smaller devicelengths.

Fig. 3 shows the simulated and measured NMOS drain cur-rent noise versus absolute gate-source voltage in the saturationregion for 5.0, 1.2, and 0.6m, respectively, at frequency of1.0 Hz. It shows that the shorter the NMOS transistor channel,the larger the drain current noise. Fig. 4 shows the correspondingsimulated and measured NMOS input-referred voltage noise inthe saturation region. For the simple case of long-channel de-vices, the transconductance is a linear function of gate voltageand so the input referred noise stays constant.

For short-channel devices, however, due to the velocity satu-ration of carriers in the channel, the transconductance does notincrease linearly with gate voltage bias.


Fig. 5. Short-channel effect on 0.6�m-NMOSFET transconductance.

Fig. 6. Different SPICE models used to simulated the drain current noise for the 0.6-�m short-channel NMOS transistors in the saturation region.f = 1 Hz.

Considering the presence of velocity saturation effects, thedrain current of MOSFET working in situation region is

(1)

where , ( , electric field) and has the dimension. It can be shown that the transconductance under short-

channel effects is

(2)

So, the transconductance,, is no longer linear with the gatevoltage, .

Fig. 5 shows the transconductance values obtained by simula-tion, measurement and analytical calculation for 0.6m-NMOSdevices over a range of gate bias, which demonstrates that thetransconductances increase more slowly with increasing gatebias. This nonlinearity of the transconductance causes the inputreferred voltage noise at the gate to increase with increasing gatebias in the saturation region. Note that HSPICE level 49 does notuse the BSIM 3.3 noise model, for input referred noise voltage. Itappears to be calculated using a transconductance which changeslinearly with gate voltage even for submicrometer devices.

Figs. 6 and 7 show that the HSPICE BSIM 3.2 (level 47)and PSPICE BSIM 3.2 (level 6) give almost the same resultsas that of HSPICE (level 49). Although they can approximately


Fig. 7. Different SPICE models used to simulated the input-referred voltage noise for the 0.6-�m short-channel NMOS transistors in the saturation region.f =1 Hz.

Fig. 8. Analog measured 1.2-�m NMOS noise to determine channel width effect.W =30.8�m andW = 2 � 30.8�m, at 1 KHz in saturation region.

simulate the measured drain current noises shown in Fig. 6, theycan not show that the input referred gate voltage noise increasesproportionally with increasing gate bias as shown in Fig. 7.

Fig. 8 shows some analog measurements of the input-referredvoltage noise of NMOS transistors ( 1.2 m) at 1 kHz inthe saturation region to determine the-channel width effect. Thetendency of noise to decrease with width,, is consistent withthe NLEV 2 and 3 or surface state model.

So, in conclusion, for NMOS devices in saturation region,the flicker noise is due to the number fluctuation model, andthe NLEV 2 and 3 equation seems to be the most appropriatenoise model to simulate the flicker noise for both long-channeland short-channel devices.

When in the subthreshold region (also called weak inversion),the gate potential applied in MOSFET ( ) is less than thethreshold voltage ( ), the channel charge and the depletion re-gion charge in the MOSFET device are both affected by the ap-plied gate voltage [17]. The MOSFET transistor can thus worksimilar to a bipolar transistor because the electrons in thesource region of an NMOS transistor can surmount the potentialbarrier to the -type substrate and get into the channel region.Its characteristics can be defined as

(3)


Fig. 9. Simulated and measured NMOS drain current noise versus absolute gate-source voltage in the subthreshold region.L = 5.0, 1.2, and 0.6�m, respectively.f = 1 Hz.

Fig. 10. Simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage in the subthreshold region.L = 5.0, 1.2, and 0.6�m,respectively.f = 1 Hz.

So, the transconductance, , is an exponential function ofgate voltage, , in subthreshold region, this will be reflectedin the input referred voltage noise.

Fig. 9 shows the simulated and measured NMOS draincurrent noise versus absolute gate-source voltage in the sub-threshold region for 5.0, 1.2, and 0.6 m, respectively.Fig. 10 shows the corresponding simulated and measuredNMOS input-referred voltage noise in the subthreshold region.The input referred voltage noise at the gate increases sharply asthe gate voltage decreases since the transconductance,, isan exponential function of gate voltage in subthreshold region.The level-3 model does not have an appropriate subthreshold

model for long-channel transistors, and the BSIM 3.3 modelalso does not work for long-channel devices, so no simulationcan be done for 5-m-long-channel devices.

In conclusion, for NMOS devices in subthreshold region, theinput referredvoltagenoise is larger thanthatofsaturationregion,and it decreasesdrasticallywhen increasing the gate bias voltage.It seems that the NLEV 2 and 3 equation can still predict thenoise tendencywell for the short-channel NMOSdevices.

Figs. 11 and 12 give a summary of the results for both theinput referred mean square noise voltage at the gate and themean square drain current noise for both regions of operationand both types of devices.


Fig. 11. Summary of simulated and measured NMOS drain current noise versus absolute gate-source voltage from subthreshold to saturation region.L = 5.0,1.2, and 0.6�m, respectively.f = 1 Hz.

Fig. 12. Summary of simulated and measured NMOS input-referred voltage noise versus absolute gate-source voltage from subthreshold to saturation region.L = 5.0, 1.2, and 0.6�m, respectively.f = 1 Hz.

V. CONCLUSION

For long-channel NMOS ( 5 m), the input-referred gate-voltage noise ( ) is independent of gate bias ( ), whichshows the surface state model and the noise model (NLEV2 and 3) in SPICE is more appropriate. SPICE (level3) canpredict the long-channel NMOS noise performance very wellin saturation region, but not in subthreshold region, and alsocannot be used to simulated the short-channel NMOS noise per-formance.

For short-channel NMOS devices ( 0.6 and 1.2 m), theinput-referred gate-voltage noise ( ) is dependent on gate-

source voltage ( ), increasing proportionally as increase,which is due to the nonlinearity of the transconductance ()variation with gate bias. These devices can be modeled with theBSIM 3.3 model (level 7 in PSPICE version 8.0) and the samenoise model (noimod 1 which is approximately the same asNLEV 2 and 3 in SPICE) is also appropriate. BSIM 3.3 inPSPICE version 8.0 can predict the short-channel NMOS noiseperformance in both the saturation and the subthreshold region,but does not work for long-channel NMOS devices.

HSPICE level 49 does not use the BSIM 3.3 noise equations.Note that PSPICE ver 8.0 and ver 9.1 have completely differentequations for noimod 1, only the one in PSPICE ver 8.0


TABLE ISPICE EXPRESSIONS FORMOSFET FLICKER NOISE SIMULATION

which is similar to NLEV 2 or 3 is relevant to NMOS de-vices. NMOS devices are best described by the NLEV2 or 3models. These models are applicable only to NMOS and not toPMOS devices, the latter appear to be described by a differentmodel which will be described in another manuscript.

APPENDIX

A. Detailed Explanation for Table I

1) The HSPICE Manual Problem for the Default NoiseModel in Level 49 (BIM 3.3):The HSPICE manual indicates

that the default noise model in level 49 (BSIM 3.3) is NLEV2. We think it should be NLEV 0 according to the simulationresults as follows:

For example, using the same dc and noise parametersin HSPICE level 49 for the NMOS flicker noise simula-tion, 95 m, VTO 0.7 V, 50 ,

, 0.6 m, 30.8 m, if in settingthe gate bias, , to be 3.0 V, when we define NLEV 2, thesimulated mean square current noise () is

- A Hz


when we define NLEV 0, the simulated mean square currentnoise ( ) is

- A Hz

when we do not define NLEV, the simulated mean square cur-rent noise ( ) is

- A Hz

Here, we can see that the current noise obtained from thedefault noise model is the same as the current noise obtainedfrom the noise model, NLEV 0. The default noise model isNLEV 0 for HSPICE level 49 (BSIM 3.3).

2) The BSIM 3.3 Manual Problem for the Expression inPSPICE ver 8.0 Level 7:The BSIM 3.3 manual refers thenoise equation selector, NOIMOD 1, to the noise equation,NLEV 0. We think the NOIMOD 1 should refer to thenoise equation, NLEV 2 and 3. The detailed explanation isas following:

For example, if the parameters for the 0.6-m NMOS tran-sistor used in the PSPICE version 8.0 level 7 simulation are:

m, , 0.6 m, 30.8m. When 2.0 V, the simulated dc characteristics are

- A - Siemens

At frequency of 1.0 Hz, the simulated drain current noise,upon setting the noise equation selector, NOIMOD1, is:

A /Hz.Now let us assume that the effective channel width () and

the effective channel length ( ) are about same as the channelwidth ( ) and the channel length (), respectively, and approx-imately calculate the mean square drain current noise using thenoise equations provided in SPICE, NELV0 and NELV 2and 3:

For NLEV 0

- -- -

AHz

AHz

For NLEV 2 and 3

- -- - -

AHz

AHz

So, by comparing with these three drain current noise values,we find that the drain current noise simulated by PSPICE ver-sion 8.0 level 7 (BSIM 3.3) with NOIMOD 1 is closest to theone calculated by using the NLEV 2 and 3 noise equation,and they are both much smaller than that one calculated fromthe noise equation, NLEV 0.

In other words, NOIMOD 1 in PSPICE ver 8.0 (BSIM 3.3)more likely refers to the noise equation, NLEV2 and 3, not

NLEV 0. PSPICE ver 9.1 level 7 (BSIM 3.3) does in fact usethe NLEV 0 equation for NOIMOD 1.

3) Confirmation of the Default Expression in the StandardNoise Model in SPICE:The HSPICE level 3 and level 47(BSIM 3.2), and PSPICE level 3 and level 6 (BSIM 3.2) all usethe standard noise model for flicker noise simulations, and allthe default expressions in them are referred to NLEV2.

The following gives confirmation of the NELV 2 defaultmodel in PSPICE level 6.

The parameters for the 0.6-m NMOS transistor used inthe PSPICE level 6 simulation are: 95 -10 m,1.0 -24, 0.6 m, 30.8 m. We also assume that theeffective channel width ( ) and the effective channel length( ) are about same to the channel width () and the channellength ( ), respectively.

a) When 1.0 V, the simulated dc characteristics are asfollows:

- A - Siemens

At frequency of 1.0 Hz, the simulated drain currentnoise is: 7.96 -17 A /Hz. For NLEV 2 and 3

- -- - -

AHz

AHz

b) When 2.0 V, the simulated dc characteristics are asfollows:

- A - Siemens

At frequency of 1.0 Hz, the simulated drain current noiseis: 2.55 -16 A /Hz. For NLEV 2 and 3

- -- - -

AHz

AHz

c) When 4.0 V, the simulated dc characteristics are asfollows:

- A - Siemens

At frequency of 1.0 Hz, the simulated drain current noiseis: 4.02 -16 A /Hz. For NLEV 2 and 3

- -- - -

AHz

AHz


TABLE IICOMPARISON OFPSPICE LEVEL 6 WITH NLEV = 2 SIMULATIONS OF FLICKER NOISE(NMOS:T = 95e-10 m,KF = 1.0e-24,L= 0.6�m,W = 30.8�m)

All the above flicker noise results are included in Table IIfor convenience. From it, we can see clearly that the defaultexpression in the standard noise model in PSPICE level 6 isNLEV 2. The same conclusion applies to HSPICE level 3and level 47, and PSPICE level 3.

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Dingming Xie was born in Gao’an, China, in 1971.He received the B.S. degree in chemical engineeringfrom Nanjing Forestry University, China, in 1992 andtwo M.S. degrees in electrical engineering and forestproducts from Oregon State University, Corvallis, in1999 and 1998, respectively.

He is now an Analog Design Engineer with Qual-comm, Inc., San Diego, CA.

Mengzhang Chengwas born in JiangSu, China, in 1956. He received the B.S.degree in automatic control engineering from Northeast Engineering University,China, in 1982 and M.S. degree in computer science in 1987. Since 1999, he hasbeen working on the M.S. degree in electrical engineering from Oregon StateUniversity, Corvallis.

Leonard Forbes was born in Grande Prairie, AB,Canada, in 1940. He received the B.Sc. degree withdistinction in engineering physics from the Univer-sity of Alberta, Edmonton, AB, Canada, and receivedthe Ph.D. degree in electrical engineering from theUniversity of Illinois, Urbana, in 1970.

He has 30 years of experience in the semicon-ductor industry working as an engineer, teachingand/or doing research. He is currently a Professor atOregon State University, Corvallis, and an AdjunctResearch Fellow of the Micron Advanced Research

Institute, Boise, ID. He has previously taught at the University of California atDavis, the University of Arkansas, Fayetteville, and was an IBM Professor atHoward University, Washington, DC.

Documents

pspice model for flicker noise.pdf