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1:1 1 1 10-02-2012_14:43
C3
PSEC4-Digital
C.Harabedian
PSEC4-DIGITAL LAPPD
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
Clocks
2-3
JC_S
PI[3
:0]
FPG
A_TO
_JC[
6:0]
JC_MClk[0:4]
CLK4
0+
CLK4
0-
JC_SMA
CLK4
0_TO
_FPG
A
Board2Board_240pin
PSEC_TokDECODE[0:14]
PSEC_TRIG[0:29]
PSEC_ChanDECODE[0:14]
PSEC_Rd_Clk[0:4]
gnd
+3.0V +1.2V
JC_MClk[0:4]
PSEC_DATA[0:59]
PSEC_from_FPGA[0:46]
PSEC_to_FPGA[0:14]
PSEC_DAC_SPI[0:9]
Power
4
FPGA
5-10
JC_S
PI[3
:0]
FPG
A_TO
_JC[
6:0]
FD[0:15]
PA[0:7]
USB_AUX[0:7]
PSEC
_Rd_
Clk[
0:4]
PSEC
_Cha
nDEC
ODE
[0:1
4]
PSEC
_Tok
DECO
DE[0
:14]
PSEC
_fro
m_F
PGA[
0:46
]
PSEC
_DAC
_SPI
[0:9
]
PSEC
_to_
FPG
A[0:
14]
PSEC
_DAT
A[0:
59]
PSEC
_TRI
G[0
:29]
GPI
O_1
v2[0
:23]
GPI
O_2
V5[0
:29]
GPI
O_3
V3[0
:12]
CLK_OUT_1V2[0:3]
CLK_OUT_2V5[0:5]
CLK_
IN_R
EF[0
:8]
SMA_TRIG
FPGA_CLKOUT
CC_COMM[0:13]
CLK4
0_TO
_FPG
A
15
USB
USB_AUX[0:7]
PA[0:7]
FD[0:15]
+3.3V +1.2V_PSEC
DGND
CONNECTORS
16-18
CLK40+
CLK40-
JC_SMA
GPIO_1v2[0:23]
GPIO_2V5[0:29]
GPIO_3V3[0:12]
CLK_OUT_1V2[0:3]
CLK_OUT_2V5[0:5]
CLK_IN_REF[0:8]
SMA_TRIG
FPGA_CLKOUT
CC_COMM[0:13]
TOP LEVEL BLOCKS
1 2 23-01-2012_15:18
C2
Clocks
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
JC_SPI[3:0]
FPGA_TO_JC[6:0]
CLKOUT0
CLKOUT4
U3
CDCE62005
37
13
2
3
46
45
43
14
12
31
33
23
24
25
22
4140 4838
4
30 493644147353442395
15
32
29
26
21
6
18
11
8
7
10
9
17
16
20
19
28
27U0P
U0N
U1P
U1N
U2P
U2N
U3P
U3N
U4N
VCC_OUT_0
VCC_OUT_1
VCC_OUT_2
U4P
VCC_OUT_3
VCC_OUT_4
VCC_OUT_5
VCC_OUT_6
VCC_AUXOUT
VCC1
_PLL
VCC2
_PLL
VCC3
_PLL
VCC_
VCO
_0
VCC_
VCO
_1
VCC_
IN_P
RI
VCC_
IN_S
EC
VCC_
AUXI
NG
ND_V
CO
GND
_PAD
TEST
OUT
A
REG
_CAP
1
REG
_CAP
2
VBB
EXT_
LFP
EXT_
LFN
SPI_MISO
SPI_LE
SPI_CLK
SPI_MOSI
TEST_MODE
REF_SEL
POWER_DOWN
SYNC
AUX_IN
PRI_REF+
PRI_REF-
SEC_REF+
SEC_REF-
AUX_OUT
PLL_LOCK
+3.3V
2 1
FB1BLM15HD102SN1D
BLM15HD102SN1D
FB2
2 1
BLM15HD102SN1D
FB3
2 1
C58
10uF
2
1+
C75
1uF
2
1
C1
0.1u
F
2
1
C131
0.01
uF
2
1
0.01
uF
C132
2
1
0.01
uF
C133
2
1
DGND
CLKOUT3
CLKOUT2
CLKOUT1
CLK40+
CLK40-
C59
10uF
10uF
C60
C76
1uF
1
DGND
DO N
OT
INST
ALL=
DO N
OT
INST
ALL=
C38DO N
OT
INST
ALL= R2
4
FPGA_TO_JC[2]
FPGA_TO_JC[1]
JC_SMA
R3
50oh
ms
50oh
ms
R4
50oh
ms
R5
DGND
DGND
0.01
uF
C136
0.01
uF
C134
0.01
uF
C135
0.1u
F
C2
1uF
C79
10uF
C61
+
CLK40_ONBOARD
R29100ohms
0.01
uF
C137
0.1u
F
C3
1uF
C80
10uF
C62
+
DGND
DGND
VCC_VCO
VCC_IN
VCC_IN
VCC_VCOVCC_IN
+3.3V
0.01
uF
C138
10uF
C65
+
0.01
uF
C139
0.01
uF
C140
0.01
uF
C141
0.01
uF
C142
0.01
uF
C143 C4
0.1u
F
0.1u
F
C50.
1uF
C60.
1uF
C70.
1uF
C8
0.01
uF
C144
C81
1uF
1uF
C82
1uF
C83
+3.3V
DGND
R44
25ohms
25ohms
R45
25ohms
R46
25ohms
R47
25ohms
R48
25ohms
R49
VCC_PLL
JC_SPI[3]
JC_SPI[2]
JC_SPI[1]
JC_SPI[0]
FPGA_TO_JC[6]
FPGA_TO_JC[5]
FPGA_TO_JC[4]
FPGA_TO_JC[3]
FPGA_TO_JC[0]
JITTER CLEANER
C.Harabedian
C2
10-02-2012_14:482 2
ClocksREV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
U4
SN74AVC1T45
5
43
6
2
1VCCA
GND
VCCB
A B
DIR
+3.3V
DGND
+1.2V_PSEC
C145
0.01uF
C11
0.1uF
C881uF
1uF
C89
0.1u
FC12
0.01
uFC146
2
1
0.01uFC147
0.1uF
C13
1uF
C901uF
C910.1uF
C14
0.01uF
C148
SN74AVC1T45
U5
5
43
6
2
1VCCA
GND
VCCB
A B
DIR
+3.3V+1.2V_PSEC
DGND
0.01uFC149
0.1uF
C15
1uF
C921uF
C93
0.1uF
C16
0.01uF
C150
SN74AVC1T45
U6
5
43
6
2
1VCCA
GND
VCCB
A B
DIR
+3.3V
+1.2V_PSEC
DGND
0.01uF
C151
0.1uF
C17
1uF
C941uF
C95
0.1uF
C180.01uF
C152
SN74AVC1T45
U7
5
43
6
2
1VCCA
GND
VCCB
A B
DIR
+3.3V
+1.2V_PSEC
DGND
0.01uF
C153
0.1uF
C19 C961uF 1uF
C970.1uF
C20
0.01uF
C154
SN74AVC1T45
U8
5
43
6
2
1VCCA
GND
VCCB
A B
DIR
+3.3V
+1.2V_PSEC
DGND
CLK_E_1v2
CLK_D_1v2
CLK_C_1v2
CLK_B_1v2
CLK_A_1v2
R400ohm
s
U13
CDCLVC1102PWR
6
4
8
3
2
1CLKIN
1G
Y0
Y1
GND
VDD
CLK40_TO_FPGA
+3.3V
DGND
R35
1Kohms
JP1
1
2
3
DGND
+3.3V
25ohms
R87
Y1
FXO-HC536R-40
40Mhz Osc.
31
2
4 VCC
GND
ENOUT
25ohms
R88
DGND
+3.3V
CLK40_ONBOARD
0.01
uF
C36
2
1 0.01
uF
C37
2
1
0.1u
F
C21
2
1
DGND
+3.3V
1uF
C99
2
1 0.01
uF
C156
2
1
0.1u
F
C22
2
1
R6
25ohms
25ohms
R725ohms
R825ohms
R925ohms
R10
0.00
47uF
C190
2
1R43
25ohms
CLKOUT0
CLK_A_1v2
CLK_A_1v2
CLKOUT1
CLK_B_1v2
CLK_B_1v2
CLKOUT2
CLK_C_1v2
CLK_C_1v2
CLKOUT3
CLK_D_1v2
CLK_D_1v2
CLKOUT4
CLK_E_1v2
CLK_E_1v2
MClk_A
MClk_B
MClk_C
MClk_D
MClk_E
JC_MClk[0:4]
SIZE RESISTORS FOR CORRECT TERMINATION
JITT
ER C
LEAN
ER O
UTPU
T TR
ANSL
ATED
TO
1.2
V
OSC
ILLA
TORS
TO B2B CONNECTOR
B2B_240pin $16I7SAMTEC_QSH-120-01-L-D-A_PINS.11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+1.2V : OUT ... +
+3.0V : OUT ...
gnd : OUT ... + + +
JC_MClk[0:4] : OUT (*)
JC_MClk[0:4] : OUT 21 : BI# +
JC_MClk[0:4] : OUT 75 : BI#
JC_MClk[0:4] : OUT 119 : B...
JC_MClk[0:4] : OUT 171 : B...
JC_MClk[0:4] : OUT 215 : B...
PSEC_ChanDECODE[0:14] : OUT (*)
PSEC_ChanDECODE[0:14] : OUT 41 : BI#
PSEC_ChanDECODE[0:14] : OUT 95 : BI#
PSEC_ChanDECODE[0:14] : OUT 139 : B...
PSEC_ChanDECODE[0:14] : OUT 191 : B...
PSEC_ChanDECODE[0:14] : OUT 237 : B...
PSEC_ChanDECODE[0:14] : OUT 42 : BI#
PSEC_ChanDECODE[0:14] : OUT 96 : BI#
PSEC_ChanDECODE[0:14] : OUT 140 : B...
PSEC_ChanDECODE[0:14] : OUT 192 : B...
PSEC_ChanDECODE[0:14] : OUT 238 : B...
PSEC_ChanDECODE[0:14] : OUT 43 : BI#
PSEC_ChanDECODE[0:14] : OUT 97 : BI#
PSEC_ChanDECODE[0:14] : OUT 141 : B...
PSEC_ChanDECODE[0:14] : OUT 193 : B...
PSEC_ChanDECODE[0:14] : OUT 239 : B...
PSEC_DAC_SPI[0:9] : BI (*)
PSEC_DAC_SPI[0:9] : BI 49 : BI#
PSEC_DAC_SPI[0:9] : BI 50 : BI#
PSEC_DAC_SPI[0:9] : BI 52 : BI#
PSEC_DAC_SPI[0:9] : BI 53 : BI#
PSEC_DAC_SPI[0:9] : BI 54 : BI#
PSEC_DAC_SPI[0:9] : BI 145 : B...
PSEC_DAC_SPI[0:9] : BI 146 : B...
PSEC_DAC_SPI[0:9] : BI 148 : B...
PSEC_DAC_SPI[0:9] : BI 149 : B...
PSEC_DAC_SPI[0:9] : BI 150 : B...
PSEC_DATA[0:59] : IN (*)
PSEC_DATA[0:59] : IN 31 : BI# +
PSEC_DATA[0:59] : IN 85 : BI#
PSEC_DATA[0:59] : IN 129 : B...
PSEC_DATA[0:59] : IN 181 : B...
PSEC_DATA[0:59] : IN 225 : B...
PSEC_DATA[0:59] : IN 10 : BI#
PSEC_DATA[0:59] : IN 64 : BI#
PSEC_DATA[0:59] : IN 108 : B...
PSEC_DATA[0:59] : IN 160 : B...
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+
+
+ + + +
+
+
+
+
+
+
93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+ +
+
+
+
+
+
141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+
+
+ + + +
+
+
+
+
+
187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+ + +
+
+
+
+
233 235 237 239 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+
+
+
+
+
50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+
+
+
+
+
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+
+
+
+
+
+
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+
184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
+ +
+
+
230 232 234 236 238 240$16I8
SAMTEC_QSH-120-01-L-D-A_GROUND.1G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
+1.2V / B2B_240pin
+3.0V / B2B_240pin
gnd / B2B_240pin
JC_MClk[0:4] / B2B_240pin
MClk_A / B2B_240pin
MClk_B / B2B_240pin
MClk_C / B2B_240pin
MClk_D / B2B_240pin
MClk_E / B2B_240pin
PSEC_ChanDECODE[0:14] / B2B_240pin
ChanDECODE0_A / B2B_240pin
ChanDECODE0_B / B2B_240pin
ChanDECODE0_C / B2B_240pin
ChanDECODE0_D / B2B_240pin
ChanDECODE0_E / B2B_240pin
ChanDECODE1_A / B2B_240pin
ChanDECODE1_B / B2B_240pin
ChanDECODE1_C / B2B_240pin
ChanDECODE1_D / B2B_240pin
ChanDECODE1_E / B2B_240pin
ChanDECODE2_A / B2B_240pin
ChanDECODE2_B / B2B_240pin
ChanDECODE2_C / B2B_240pin
ChanDECODE2_D / B2B_240pin
ChanDECODE2_E / B2B_240pin
PSEC_DAC_SPI[0:9] / B2B_240pin
DAC_10 / B2B_240pin
DAC_11 / B2B_240pin
DAC_12 / B2B_240pin
DAC_13 / B2B_240pin
DAC_14 / B2B_240pin
DAC_20 / B2B_240pin
DAC_21 / B2B_240pin
DAC_22 / B2B_240pin
DAC_23 / B2B_240pin
DAC_24 / B2B_240pin
PSEC_DATA[0:59] / B2B_240pin
DATA0_A / B2B_240pin
DATA0_B / B2B_240pin
DATA0_C / B2B_240pin
DATA0_D / B2B_240pin
DATA0_E / B2B_240pin
DATA10_A / B2B_240pin
DATA10_B / B2B_240pin
DATA10_C / B2B_240pin
DATA10_D / B2B_240pin
... + + + + + + + + + + + + + + + +
+
B2B_240pin $16I7SAMTEC_QSH-120-01-L-D-A_PINS.11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
PSEC_DATA[0:59] : IN 206 : B...
PSEC_DATA[0:59] : IN 9 : BI# +
PSEC_DATA[0:59] : IN 63 : BI#
PSEC_DATA[0:59] : IN 107 : B...
PSEC_DATA[0:59] : IN 159 : B...
PSEC_DATA[0:59] : IN 203 : B...
PSEC_DATA[0:59] : IN 30 : BI#
PSEC_DATA[0:59] : IN 84 : BI#
PSEC_DATA[0:59] : IN 128 : B...
PSEC_DATA[0:59] : IN 180 : B...
PSEC_DATA[0:59] : IN 226 : B...
PSEC_DATA[0:59] : IN 29 : BI# +
PSEC_DATA[0:59] : IN 83 : BI#
PSEC_DATA[0:59] : IN 127 : B...
PSEC_DATA[0:59] : IN 179 : B...
PSEC_DATA[0:59] : IN 223 : B...
PSEC_DATA[0:59] : IN 27 : BI# +
PSEC_DATA[0:59] : IN 81 : BI#
PSEC_DATA[0:59] : IN 125 : B...
PSEC_DATA[0:59] : IN 177 : B...
PSEC_DATA[0:59] : IN 221 : B...
PSEC_DATA[0:59] : IN 26 : BI#
PSEC_DATA[0:59] : IN 80 : BI#
PSEC_DATA[0:59] : IN 124 : B...
PSEC_DATA[0:59] : IN 176 : B...
PSEC_DATA[0:59] : IN 222 : B...
PSEC_DATA[0:59] : IN 24 : BI#
PSEC_DATA[0:59] : IN 78 : BI#
PSEC_DATA[0:59] : IN 122 : B...
PSEC_DATA[0:59] : IN 174 : B...
PSEC_DATA[0:59] : IN 220 : B...
PSEC_DATA[0:59] : IN 16 : BI#
PSEC_DATA[0:59] : IN 70 : BI#
PSEC_DATA[0:59] : IN 114 : B...
PSEC_DATA[0:59] : IN 166 : B...
PSEC_DATA[0:59] : IN 212 : B...
PSEC_DATA[0:59] : IN 15 : BI# +
PSEC_DATA[0:59] : IN 69 : BI#
PSEC_DATA[0:59] : IN 113 : B...
PSEC_DATA[0:59] : IN 165 : B...
PSEC_DATA[0:59] : IN 209 : B...
PSEC_DATA[0:59] : IN 13 : BI# +
PSEC_DATA[0:59] : IN 67 : BI#
PSEC_DATA[0:59] : IN 111 : B...
PSEC_DATA[0:59] : IN 163 : B...
PSEC_DATA[0:59] : IN 207 : B...
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
+
93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
+
141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
+
187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
+
233 235 237 239 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
+
+
+
+
+
230 232 234 236 238 240$16I8
SAMTEC_QSH-120-01-L-D-A_GROUND.1G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
DATA10_E / B2B_240pin
DATA11_A / B2B_240pin
DATA11_B / B2B_240pin
DATA11_C / B2B_240pin
DATA11_D / B2B_240pin
DATA11_E / B2B_240pin
DATA1_A / B2B_240pin
DATA1_B / B2B_240pin
DATA1_C / B2B_240pin
DATA1_D / B2B_240pin
DATA1_E / B2B_240pin
DATA2_A / B2B_240pin
DATA2_B / B2B_240pin
DATA2_C / B2B_240pin
DATA2_D / B2B_240pin
DATA2_E / B2B_240pin
DATA3_A / B2B_240pin
DATA3_B / B2B_240pin
DATA3_C / B2B_240pin
DATA3_D / B2B_240pin
DATA3_E / B2B_240pin
DATA4_A / B2B_240pin
DATA4_B / B2B_240pin
DATA4_C / B2B_240pin
DATA4_D / B2B_240pin
DATA4_E / B2B_240pin
DATA5_A / B2B_240pin
DATA5_B / B2B_240pin
DATA5_C / B2B_240pin
DATA5_D / B2B_240pin
DATA5_E / B2B_240pin
DATA6_A / B2B_240pin
DATA6_B / B2B_240pin
DATA6_C / B2B_240pin
DATA6_D / B2B_240pin
DATA6_E / B2B_240pin
DATA7_A / B2B_240pin
DATA7_B / B2B_240pin
DATA7_C / B2B_240pin
DATA7_D / B2B_240pin
DATA7_E / B2B_240pin
DATA8_A / B2B_240pin
DATA8_B / B2B_240pin
DATA8_C / B2B_240pin
DATA8_D / B2B_240pin
DATA8_E / B2B_240pin
B2B_240pin $16I7SAMTEC_QSH-120-01-L-D-A_PINS.11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
PSEC_DATA[0:59] : IN 11 : BI# +
PSEC_DATA[0:59] : IN 65 : BI#
PSEC_DATA[0:59] : IN 109 : B...
PSEC_DATA[0:59] : IN 161 : B...
PSEC_DATA[0:59] : IN 205 : B...
PSEC_from_FPGA[0:46] : OUT (*)
PSEC_from_FPGA[0:46] : OUT 36 : BI#
PSEC_from_FPGA[0:46] : OUT 90 : BI#
PSEC_from_FPGA[0:46] : OUT 134 : B...
PSEC_from_FPGA[0:46] : OUT 186 : B...
PSEC_from_FPGA[0:46] : OUT 232 : B...
PSEC_from_FPGA[0:46] : OUT 34 : BI#
PSEC_from_FPGA[0:46] : OUT 88 : BI#
PSEC_from_FPGA[0:46] : OUT 132 : B...
PSEC_from_FPGA[0:46] : OUT 184 : B...
PSEC_from_FPGA[0:46] : OUT 230 : B...
PSEC_from_FPGA[0:46] : OUT 7 : BI# +
PSEC_from_FPGA[0:46] : OUT 61 : BI#
PSEC_from_FPGA[0:46] : OUT 105 : B...
PSEC_from_FPGA[0:46] : OUT 157 : B...
PSEC_from_FPGA[0:46] : OUT 201 : B...
PSEC_from_FPGA[0:46] : OUT 33 : BI# +
PSEC_from_FPGA[0:46] : OUT 87 : BI#
PSEC_from_FPGA[0:46] : OUT 131 : B...
PSEC_from_FPGA[0:46] : OUT 183 : B...
PSEC_from_FPGA[0:46] : OUT 227 : B...
PSEC_from_FPGA[0:46] : OUT 45 : BI#
PSEC_from_FPGA[0:46] : OUT 6 : BI#
PSEC_from_FPGA[0:46] : OUT 60 : BI#
PSEC_from_FPGA[0:46] : OUT 104 : B...
PSEC_from_FPGA[0:46] : OUT 156 : B...
PSEC_from_FPGA[0:46] : OUT 202 : B...
PSEC_from_FPGA[0:46] : OUT 35 : BI#
PSEC_from_FPGA[0:46] : OUT 89 : BI#
PSEC_from_FPGA[0:46] : OUT 133 : B...
PSEC_from_FPGA[0:46] : OUT 185 : B...
PSEC_from_FPGA[0:46] : OUT 231 : B...
PSEC_from_FPGA[0:46] : OUT 40 : BI#
PSEC_from_FPGA[0:46] : OUT 94 : BI#
PSEC_from_FPGA[0:46] : OUT 138 : B...
PSEC_from_FPGA[0:46] : OUT 190 : B...
PSEC_from_FPGA[0:46] : OUT 236 : B...
PSEC_from_FPGA[0:46] : OUT 2 : BI#
PSEC_from_FPGA[0:46] : OUT 56 : BI#
PSEC_from_FPGA[0:46] : OUT 100 : B...
PSEC_from_FPGA[0:46] : OUT 152 : B...
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
+
+
93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
233 235 237 239 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
+
50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
+
+
+
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
+
230 232 234 236 238 240$16I8
SAMTEC_QSH-120-01-L-D-A_GROUND.1G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
DATA9_A / B2B_240pin
DATA9_B / B2B_240pin
DATA9_C / B2B_240pin
DATA9_D / B2B_240pin
DATA9_E / B2B_240pin
PSEC_from_FPGA[0:46] / B2B_240pin
ADClatch_A / B2B_240pin
ADClatch_B / B2B_240pin
ADClatch_C / B2B_240pin
ADClatch_D / B2B_240pin
ADClatch_E / B2B_240pin
clearADC_A / B2B_240pin
clearADC_B / B2B_240pin
clearADC_C / B2B_240pin
clearADC_D / B2B_240pin
clearADC_E / B2B_240pin
DLLreset_A / B2B_240pin
DLLreset_B / B2B_240pin
DLLreset_C / B2B_240pin
DLLreset_D / B2B_240pin
DLLreset_E / B2B_240pin
EXT_trig_A / B2B_240pin
EXT_trig_B / B2B_240pin
EXT_trig_C / B2B_240pin
EXT_trig_D / B2B_240pin
EXT_trig_E / B2B_240pin
FREQsel_global / B2B_240pin
rampSTART_A / B2B_240pin
rampSTART_B / B2B_240pin
rampSTART_C / B2B_240pin
rampSTART_D / B2B_240pin
rampSTART_E / B2B_240pin
RO_enable_A / B2B_240pin
RO_enable_B / B2B_240pin
RO_enable_C / B2B_240pin
RO_enable_D / B2B_240pin
RO_enable_E / B2B_240pin
TOKin1_A / B2B_240pin
TOKin1_B / B2B_240pin
TOKin1_C / B2B_240pin
TOKin1_D / B2B_240pin
TOKin1_E / B2B_240pin
TOKin2_A / B2B_240pin
TOKin2_B / B2B_240pin
TOKin2_C / B2B_240pin
TOKin2_D / B2B_240pin
+
+
+
B2B_240pin $16I7SAMTEC_QSH-120-01-L-D-A_PINS.11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
PSEC_from_FPGA[0:46] : OUT 198 : B...
PSEC_from_FPGA[0:46] : OUT 4 : BI#
PSEC_from_FPGA[0:46] : OUT 58 : BI#
PSEC_from_FPGA[0:46] : OUT 102 : B...
PSEC_from_FPGA[0:46] : OUT 154 : B...
PSEC_from_FPGA[0:46] : OUT 200 : B...
PSEC_from_FPGA[0:46] : OUT 44 : BI#
PSEC_Rd_Clk[0:4] : OUT (*)
PSEC_Rd_Clk[0:4] : OUT 3 : BI# +
PSEC_Rd_Clk[0:4] : OUT 57 : BI#
PSEC_Rd_Clk[0:4] : OUT 101 : B...
PSEC_Rd_Clk[0:4] : OUT 153 : B...
PSEC_Rd_Clk[0:4] : OUT 197 : B...
PSEC_TokDECODE[0:14] : OUT (*)
PSEC_TokDECODE[0:14] : OUT 37 : BI#
PSEC_TokDECODE[0:14] : OUT 91 : BI#
PSEC_TokDECODE[0:14] : OUT 135 : B...
PSEC_TokDECODE[0:14] : OUT 187 : B...
PSEC_TokDECODE[0:14] : OUT 233 : B...
PSEC_TokDECODE[0:14] : OUT 38 : BI#
PSEC_TokDECODE[0:14] : OUT 92 : BI#
PSEC_TokDECODE[0:14] : OUT 136 : B...
PSEC_TokDECODE[0:14] : OUT 188 : B...
PSEC_TokDECODE[0:14] : OUT 234 : B...
PSEC_TokDECODE[0:14] : OUT 39 : BI#
PSEC_TokDECODE[0:14] : OUT 93 : BI#
PSEC_TokDECODE[0:14] : OUT 137 : B...
PSEC_TokDECODE[0:14] : OUT 189 : B...
PSEC_TokDECODE[0:14] : OUT 235 : B...
PSEC_to_FPGA[0:14] : IN (*)
PSEC_to_FPGA[0:14] : IN 8 : BI#
PSEC_to_FPGA[0:14] : IN 62 : BI#
PSEC_to_FPGA[0:14] : IN 106 : B...
PSEC_to_FPGA[0:14] : IN 158 : B...
PSEC_to_FPGA[0:14] : IN 204 : B...
PSEC_to_FPGA[0:14] : IN 17 : BI# +
PSEC_to_FPGA[0:14] : IN 71 : BI#
PSEC_to_FPGA[0:14] : IN 115 : B...
PSEC_to_FPGA[0:14] : IN 167 : B...
PSEC_to_FPGA[0:14] : IN 211 : B...
PSEC_to_FPGA[0:14] : IN 46 : BI#
PSEC_to_FPGA[0:14] : IN 98 : BI#
PSEC_to_FPGA[0:14] : IN 142 : B...
PSEC_to_FPGA[0:14] : IN 194 : B...
PSEC_to_FPGA[0:14] : IN 240 : B...
PSEC_TRIG[0:29] : IN (*)
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
+
93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
+
141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
233 235 237 239 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
+
+
+
50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
+
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
+
+
+
230 232 234 236 238 240$16I8
SAMTEC_QSH-120-01-L-D-A_GROUND.1G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
TOKin2_E / B2B_240pin
trigCLEAR_A / B2B_240pin
trigCLEAR_B / B2B_240pin
trigCLEAR_C / B2B_240pin
trigCLEAR_D / B2B_240pin
trigCLEAR_E / B2B_240pin
trigSIGN_global / B2B_240pin
PSEC_Rd_Clk[0:4] / B2B_240pin
Rd_CLk_A / B2B_240pin
Rd_CLk_B / B2B_240pin
Rd_CLk_C / B2B_240pin
Rd_CLk_D / B2B_240pin
Rd_CLk_E / B2B_240pin
PSEC_TokDECODE[0:14] / B2B_240pin
TokDECODE0_A / B2B_240pin
TokDECODE0_B / B2B_240pin
TokDECODE0_C / B2B_240pin
TokDECODE0_D / B2B_240pin
TokDECODE0_E / B2B_240pin
TokDECODE1_A / B2B_240pin
TokDECODE1_B / B2B_240pin
TokDECODE1_C / B2B_240pin
TokDECODE1_D / B2B_240pin
TokDECODE1_E / B2B_240pin
TokDECODE2_A / B2B_240pin
TokDECODE2_B / B2B_240pin
TokDECODE2_C / B2B_240pin
TokDECODE2_D / B2B_240pin
TokDECODE2_E / B2B_240pin
PSEC_to_FPGA[0:14] / B2B_240pin
DATA_ovflw_A / B2B_240pin
DATA_ovflw_B / B2B_240pin
DATA_ovflw_C / B2B_240pin
DATA_ovflw_D / B2B_240pin
DATA_ovflw_E / B2B_240pin
Dlout_A / B2B_240pin
Dlout_B / B2B_240pin
Dlout_C / B2B_240pin
Dlout_D / B2B_240pin
Dlout_E / B2B_240pin
RO_mon_A / B2B_240pin
RO_mon_B / B2B_240pin
RO_mon_C / B2B_240pin
RO_mon_D / B2B_240pin
RO_mon_E / B2B_240pin
PSEC_TRIG[0:29] / B2B_240pin
+
+
B2B_240pin $16I7SAMTEC_QSH-120-01-L-D-A_PINS.11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
PSEC_TRIG[0:29] : IN 28 : BI#
PSEC_TRIG[0:29] : IN 82 : BI#
PSEC_TRIG[0:29] : IN 126 : B...
PSEC_TRIG[0:29] : IN 178 : B...
PSEC_TRIG[0:29] : IN 224 : B...
PSEC_TRIG[0:29] : IN 25 : BI# +
PSEC_TRIG[0:29] : IN 79 : BI#
PSEC_TRIG[0:29] : IN 123 : B...
PSEC_TRIG[0:29] : IN 175 : B...
PSEC_TRIG[0:29] : IN 219 : B...
PSEC_TRIG[0:29] : IN 22 : BI#
PSEC_TRIG[0:29] : IN 76 : BI#
PSEC_TRIG[0:29] : IN 120 : B...
PSEC_TRIG[0:29] : IN 172 : B...
PSEC_TRIG[0:29] : IN 218 : B...
PSEC_TRIG[0:29] : IN 20 : BI#
PSEC_TRIG[0:29] : IN 74 : BI#
PSEC_TRIG[0:29] : IN 118 : B...
PSEC_TRIG[0:29] : IN 170 : B...
PSEC_TRIG[0:29] : IN 216 : B...
PSEC_TRIG[0:29] : IN 18 : BI#
PSEC_TRIG[0:29] : IN 72 : BI#
PSEC_TRIG[0:29] : IN 116 : B...
PSEC_TRIG[0:29] : IN 168 : B...
PSEC_TRIG[0:29] : IN 214 : B...
PSEC_TRIG[0:29] : IN 14 : BI#
PSEC_TRIG[0:29] : IN 68 : BI#
PSEC_TRIG[0:29] : IN 112 : B...
PSEC_TRIG[0:29] : IN 164 : B...
PSEC_TRIG[0:29] : IN 210 : B...
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
233 235 237 239 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
+
+
+
+
50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
+
+
+
+
106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
+
+
+
+
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
+
+
+
+
184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
+
+
+
+
+
230 232 234 236 238 240$16I8
SAMTEC_QSH-120-01-L-D-A_GROUND.1G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
TRIG1_A / B2B_240pin
TRIG1_B / B2B_240pin
TRIG1_C / B2B_240pin
TRIG1_D / B2B_240pin
TRIG1_E / B2B_240pin
TRIG2_A / B2B_240pin
TRIG2_B / B2B_240pin
TRIG2_C / B2B_240pin
TRIG2_D / B2B_240pin
TRIG2_E / B2B_240pin
TRIG3_A / B2B_240pin
TRIG3_B / B2B_240pin
TRIG3_C / B2B_240pin
TRIG3_D / B2B_240pin
TRIG3_E / B2B_240pin
TRIG4_A / B2B_240pin
TRIG4_B / B2B_240pin
TRIG4_C / B2B_240pin
TRIG4_D / B2B_240pin
TRIG4_E / B2B_240pin
TRIG5_A / B2B_240pin
TRIG5_B / B2B_240pin
TRIG5_C / B2B_240pin
TRIG5_D / B2B_240pin
TRIG5_E / B2B_240pin
TRIG6_A / B2B_240pin
TRIG6_B / B2B_240pin
TRIG6_C / B2B_240pin
TRIG6_D / B2B_240pin
TRIG6_E / B2B_240pin
1 1
C2
20-01-2012_17:28
Power
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
U1
LM1084
2
1
3VIN
ADJ
VOUT
R2390ohms
R1240ohms
+5.0V_IN
C25810uF
+
10uF
C259+
DGND
DGND
10uF
C260+
10uFC261+
+5.0V_IN
100ohms
100ohms
LM317_T
U2
2
1
3VIN
ADJ
VOUT
+3.3V
+2.5V
C55
0.1uF
0.1uF
C56
+3.3V
LT3083
U11
3
42
5IN
SET
VCONTROL
VOUT
+1.2V
DGND
24Kohms
10uF
2
1+
10uF2
1+
0.1uF
2
1
4.7uF
2
1
U12
LT3083_TO-220
3
42
5IN
SET
VCONTROL
VOUT
R7424Kohms
C263
10uF
2
1+
10uFC264
2
1+
C570.1uF
2
1
+3.3V
C266
4.7uF
2
1
DGND
+1.2V_PSEC
10uF2
1+
1A
FUSE_AXIAL
2
1
1
2
3A
FUSE_AXIAL
2
1
1
2
FUSE_AXIAL
1A1
1 2
2
0026605040
J15
1 2 3 4
+5.0V_IN +5.0V_IN
DGND DGND
C91uF
+2.5V
+1.2V
+3.3V
+1.2V_PSEC
1 6 13-02-2012_10:45
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
JC_SPI[3:0]
PSEC_ChanDECODE[0:14]
PSEC_to_FPGA[0:14]
PSEC_DATA[0:59]
CLK4
0_TO
_FPG
A
SMA_TRIG
FPGA_CLKOUT
U9
EP4CGX110DF27
W5T5N5K5AC3
AC1
V5R5M5J5Y5U5AA4
AA3P5L5H5G5
AD2
N1
N2
M3
M4
L1
L2
K3
K4
J1
J2
H3
H4
G1
G2
F3
F4
AA1
AA2
Y3
Y4
W1
W2
V3
V4
U1
U2
T3
T4
R1
R2
P3
P4GXB_TX3p
GXB_TX3n
GXB_RX3p
GXB_RX3n
GXB_TX2p
GXB_TX2n
GXB_RX2p
GXB_RX2n
GXB_TX1p
GXB_TX1n
GXB_RX1p
GXB_RX1n
GXB_TX0p
GXB_TX0n
GXB_RX0p
GXB_RX0n
GXB_TX7p
GXB_TX7n
GXB_RX7p
GXB_RX7n
GXB_TX6p
GXB_TX6n
GXB_RX6p
GXB_RX6n
GXB_TX5p
GXB_TX5n
GXB_RX5p
GXB_RX5n
GXB_TX4p
GXB_TX4n
GXB_RX4p
GXB_RX4n
VCCL
_GXB
_0
VCCL
_GXB
_1
VCCL
_GXB
_2
VCCL
_GXB
_3
VCCL
_GXB
_4
VCCL
_GXB
_5
VCCL
_GXB
_6
VCCL
_GXB
_7
VCCL
_GXB
_8
VCCH
_GXB
_0
VCCH
_GXB
_1
VCCH
_GXB
_2
VCCH
_GXB
_3
RREF
0
VCCA
_GXB
_0
VCCA
_GXB
_1
VCCA
_GXB
_2
VCCA
_GXB
_3
VCCA
_GXB
_4
BANK-GXB
U9
EP4CGX110DF27
H8
F5
G8
G6
H7
E5
F6
D5
E6
D6
G7VCCIO9
DATA0
DATA1-ASDO
NCSO
DCLK
nCONFIG
nCE
TDI
TCK
TMS
TDO
BANK9
R9810Kohms
DGND
+1.2V +2.5V
RES102_0.1W1%16081Kohms
R25
DGND
+3.3V
U10
EPCS64
1
2
8
11
12
13
14
15
10
9 7
16DCLK
nCSVCC3
GND
ASDI
NC8
NC7
NC6
NC5
DATA
VCC2
VCC1R68
25ohms
DGND
R20
10Kohms
DGND
+3.3V J11
CONN_10PIN1 2
3 4
5 6
7 8
9 10109
87
65
43
21
DGNDR261Kohms
1KohmsR27
1KohmsR28
+2.5V+2.5V
DGND
+2.5V
DO NOT INSTALL
R420ohms
FD[0:15]
PA[0:7]
USB_AUX[0:7]
JC_SPI[0:3]
PSEC_Rd_Clk[0:4]
PSEC_TokDECODE[0:14]
PSEC_from_FPGA[0:46]
PSEC_TRIG[0:29]
PSEC_DAC_SPI[0:9]
TCK
TDO
TMS
TDI
CLK_IN_REF2+
CLK_IN_REF2-
CLK_IN_REF3+
CLK4
0_TO
_FPG
A
CLK_IN_REF[8]
CLK_IN_REF0+
CLK_IN_REF1-
CLK_IN_REF1+
CLK_IN_REF0-
CLK_IN_REF3-
JC_SPI[0:3]
FPGA_TO_JC[6:0]
FD[0:15]
PA[0:7]
USB_AUX[0:7]
GPIO_1v2[0:23]
GPIO_2V5[0:29]
GPIO_3V3[0:12]
CLK_OUT_1V2[0:3]
CLK_OUT_2V5[0:5]
CLK_IN_REF[0:8]
GXB
BAN
KCO
NFIG
BAN
KPO
RTS
TO T
OP
LEVE
L
2 6 10-02-2012_14:43
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
U9
EP4CGX110DF27
M21
M17
M15
M13
M11
L8L18
L16
L12
K25
K17
K15
K11
J8J22
H19
G13
F7F25
F22
F19
F17
F12
F10
B8B3B24
B20
B16
B12
AE8
AE4
AE24
AE20
AE16
AE12
AB25
AB22
AB19
AB16
AB13
AB10
M7
G20
W20
V7U6P6N6K6J7
T8V8V10
U17
U15
U13
U11
T18
T16
T12R9R7R17
R15
R13
R11P8P18
P16
P14
P12
P10N9N17
N15
N13
N11
M8
M18
M16
M14
M12
M10L17
L13
L11K8K18
K16
J10L7
Y2
Y1
W4
W3
V2
V1
U4
U3
T2
T1
R4
R3
P2
P1
N4
N3
M2
M1
L4
L3
K2
K1
J4
J3
H2
H1
G4
G3
F2
F1
E4
E3
AD1
AC2
AB2
AB1
R8
Y8
Y18
Y16
V25
U8
U21
T7
T17
T13
T11
R18
R16
R14
R12
R10
P9
P25
P22
P17
P15
P13
P11
N8
N18
N16
N14
N12
N10
M9
H20
W21
W6
U7
P7
N7
K7
H6
G21
Y20
V6
T6
R6
M6
L6
J6VCCD_PLL0
VCCD_PLL1
VCCD_PLL2
VCCD_PLL3
VCCD_PLL4
VCCD_PLL5
VCCD_PLL6
VCCD_PLL7
VCCA0
VCCA1
VCCA2
VCCA3
VCCA4
VCCA5
VCCA6
VCCA7
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
VCCI
NT0
VCCI
NT1
VCCI
NT2
VCCI
NT3
VCCI
NT4
VCCI
NT5
VCCI
NT6
VCCI
NT7
VCCI
NT8
VCCI
NT9
VCCI
NT10
VCCI
NT11
VCCI
NT12
VCCI
NT13
VCCI
NT14
VCCI
NT15
VCCI
NT16
VCCI
NT17
VCCI
NT18
VCCI
NT19
VCCI
NT20
VCCI
NT21
VCCI
NT22
VCCI
NT23
VCCI
NT24
VCCI
NT25
VCCI
NT26
VCCI
NT27
VCCI
NT28
VCCI
NT29
VCCI
NT30
VCCI
NT31
VCCI
NT32
VCCI
NT33
VCCI
NT34
VCCI
NT35
VCCI
NT36
VCCI
NT37
VCCI
NT38
VCCI
NT39
VCCI
NT40
GND
0
GND
1
GND
2
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
GND
9
GND
10
GND
11
GND
12
GND
13
GND
14
GND
15
GND
16
GND
17
GND
18
GND
19
GND
20
GND
21
GND
22
GND
23
GND
24
GND
25
GND
26
GND
27
GND
28
GND
29
GND
30
GND
31
GND
32
GND
33
GND
34
GND
35
GND
36
GND
37
GND
38
GND
39
GND
40
GND
41
GND
42
GND
43
GND
44
GND
45
GND
46
GND
47
GND
48
GND
49
GND
50
CORE POWER
DGND
DGND
+1.2VVCCD_PLL
VCCA
FPGA CORE POWER
3 6 13-02-2012_10:45
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
U9
EP4CGX110DF27
AF12
AF11
AF10
AE10
AF9
AE9
Y14
W14
AE13
AD13
AC13
Y13
W13
AE11
AD12
AF8
AF7
V14
V13
AF6
AE7
AC12
AB12
AD10
AC10
Y12
W12
AC11
AB11
AD11
V12
U12
Y11
W11
AA9
Y10
W10
V11
AF5
AF4
AE6
AE5
AD6
AD5
AD8
AD7
Y9
W9
AD9
AC9
AB9
AC8
AB8
AA8
AA7
AF3
AF2
AE2
AE1
AE3
AD3
AD4
AC4
AC5
AB5
AC7
AC6
AB7
AA5
AB6
AA6
Y7
Y6
W7
W8
AA14
AA13
AA12
AA11
AA10VCCIO3_0
VCCIO3_1
VCCIO3_2
VCCIO3_3
VCCIO3_4
VCCIO3_5
MSEL3
MSEL2
MSEL1
MSEL0
CONF_DONE
nSTATUS
INIT_DONE
CRC_ERROR
NCEO
PLL1_CLKOUTp
PLL1_CLKOUTn
PLL5_CLKOUTp
PLL5_CLKOUTn
PLL6_CLKOUTp
PLL6_CLKOUTn
DIFFIO_B2p
DIFFIO_B2n
DIFFIO_B3p
DIFFIO_B3n
DIFFIO_B4p
DIFFIO_B4n
DIFFIO_B5p
DIFFIO_B5n
VREFB3N2
DIFFIO_B7p
DIFFIO_B7n
DIFFIO_B8p
DIFFIO_B8n
DIFFIO_B9p
DIFFIO_B9n
DIFFIO_B10p
DIFFIO_B10n
DIFFIO_B11p
DIFFIO_B11n
DIFFIO_B12p
DIFFIO_B12n
DIFFIO_B14p
DIFFIO_B14n
DIFFIO_B15p
DIFFIO_B15n
DIFFIO_B16p
DIFFIO_B16n
DIFFIO_B17p
DIFFIO_B17n
VREFB3N1
DIFFIO_B19p
DIFFIO_B19n
DIFFIO_B20p
DIFFIO_B20n
DIFFIO_B21p
DIFFIO_B21n
DIFFIO_B23p
DIFFIO_B23n
DIFFIO_B25p
DIFFIO_B25n
DIFFIO_B26p
DIFFIO_B26n
DIFFIO_B27p
DIFFIO_B27n
DIFFIO_B28p
DIFFIO_B28n
DIFFIO_B30p
DIFFIO_B30n
DIFFIO_B32p
DIFFIO_B32n
VREFB3N0
DIFFIO_B33p
DIFFIO_B33n
DIFFIO_B34p
DIFFIO_B34n
DIFFIO_B35p
DIFFIO_B35n
DIFFIO_B36p
DIFFIO_B36n
BANK3
U9
EP4CGX110DF27
T15
T14
U14
VCC_CLKIN3A
DIFFCLK_7p-REFCLK2p
DIFFCLK_7n-REFCLK2n
BANK3A
U9
EP4CGX110DF27
U10
T10
U9
T9
V9VCC_CLKIN3B
DIFFCLK_0p-CLKIO20
DIFFCLK_0n
DIFFCLK_1p-CLKIO22
DIFFCLK_1n
BANK3B
R9910Kohms
DGND
+2.5V
R21
10Ko
hms
10Ko
hms
R22
DGND
+2.5V
CLK_OUT_2V5[0:5]
OUT_P
OUT_N
IN_P
IN_N
OUT_P
OUT_N
IN_P
IN_N
OUT_P
OUT_N
IN_P
IN_N
OUT_P
OUT_N
IN_P
IN_N
R30100ohms
100ohms
100ohms
+3.3V
100ohms
100ohmsR34
TP1
GPIO_2V5[1]
LVDS_RX_N[2]
LVDS_RX_N[2]
LVDS_RX_P[2]
LVDS_RX_P[2]
GPIO_2V5[13]
GPIO_2V5[28]
GPIO_2V5[21]
GPIO_2V5[26]
GPIO_2V5[3]
GPIO_2V5[7]
GPIO_2V5[2]
GPIO_2V5[0]
GPIO_2V5[20]
GPIO_2V5[19]
GPIO_2V5[6]
GPIO_2V5[11]
GPIO_2V5[11]
GPIO_2V5[27]
GPIO_2V5[23]
GPIO_2V5[29]
GPIO_2V5[25]
GPIO_2V5[24]
GPIO_2V5[14]
GPIO_2V5[18]
GPIO_2V5[17]
LVDS_RX_N[0]
LVDS_RX_N[0]
LVDS_RX_P[0]
LVDS_RX_P[0]
GPIO_2V5[12]
GPIO_2V5[16]
GPIO_2V5[15]
GPIO_2V5[5]
GPIO_2V5[10]
GPIO_2V5[9]
GPIO_2V5[4]
CLK_OUT_2V5[5]
CLK_OUT_2V5[4]
CLK_OUT_2V5[3]
CLK_OUT_2V5[2]
CLK_OUT_2V5[1]
CLK_OUT_2V5[0]
INIT_DONE
GPIO_2V5[8]
GPIO_2V5[22]
LVDS_TX_P[2]
LVDS_TX_P[2]
LVDS_TX_N[2]
LVDS_TX_N[2]
LVDS_TX_P[0]
LVDS_TX_P[0]
LVDS_TX_N[0]
LVDS_TX_N[0]
LVDS_TX_N[1]
LVDS_TX_N[1]
LVDS_TX_P[3]
LVDS_TX_P[3]
LVDS_TX_N[3]
LVDS_TX_N[3] LVDS_RX_P[1]
LVDS_RX_P[1]
LVDS_RX_N[1]
LVDS_RX_N[1]
CLK_IN_REF2+
CLK_IN_REF2-
CLK_IN_REF3+
FPGA_TO_JC[0]
LVDS_TX_P[1]
LVDS_TX_P[1]
CLK_IN_REF3-
GPIO_2V5[0:29]
GPIO_2V5[0:29]
CC_COMM[0:13]
BANK
3
4 6 10-02-2012_15:17
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
FPGA_BANKS4-5-6-7
GPIO_1v2[0:23]
PSEC_ChanDECODE[0:14]
PSEC_Rd_Clk[0:4]
PSEC_TokDECODE[0:14]
PSEC_from_FPGA[0:46]PSEC_to_FPGA[0:14]
CLK_OUT_1V2[0:3]CLK_IN_REF[8]
PSEC_TRIG[0:29]
PSEC_DATA[0:59]
FPGA_ACARD_PWR
DGND
JP2
1
2
3
+1.2V +2.5V
DGND
DGND
BANK
S 4,
5,6,
7
0ohms
5 6 13-02-2012_10:46
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
U9
EP4CGX110DF27
F8
D4
E2
E1
D1
C1
E7
D7
C9
C8
D2
C2
D3
C3
C7
C6
E9
E8
D8
H9
G9
H10
G10
D10
D9
B2
B1
C5
C4
A3
A2
C10
B9
B4
A4
B7
B6
D11
H11
G11
E11
D12
K12
J11
J12
H12
B5
A5
C12
C11
E12
D13
J13
H13
E14
E13
K13
J14
A7
A6
A9
A8
D14
B10
A10
B11
A11
A13
A12
C13
B13
G12
F9
F14
F13
F11
E10VCCIO8_0
VCCIO8_1
VCCIO8_2
VCCIO8_3
VCCIO8_4
VCCIO8_5
DIFFIO_T35n
DIFFIO_T35p
DIFFIO_T34n
DIFFIO_T34p
DIFFIO_T32n
DIFFIO_T32p
DIFFIO_T31n
DIFFIO_T31p
VREFB8N0
DIFFIO_T30n
DIFFIO_T30p
DIFFIO_T29n
DIFFIO_T29p
DIFFIO_T28n
DIFFIO_T28p
DIFFIO_T26n
DIFFIO_T26p
DIFFIO_T24n
DIFFIO_T24p
DIFFIO_T23n
DIFFIO_T23p
DIFFIO_T22n
DIFFIO_T22p
DIFFIO_T21n
DIFFIO_T21p
DIFFIO_T20n
DIFFIO_T20p
DIFFIO_T19n
DIFFIO_T19p
DIFFIO_T18n
DIFFIO_T18p
DIFFIO_T17n
DIFFIO_T17p
VREFB8N1
DIFFIO_T16n
DIFFIO_T16p
DIFFIO_T15n
DIFFIO_T15p
DIFFIO_T14n
DIFFIO_T14p
DIFFIO_T13n
DIFFIO_T13p
DIFFIO_T11n
DIFFIO_T11p
DIFFIO_T10n
DIFFIO_T10p
DIFFIO_T9n
DIFFIO_T9p
DIFFIO_T8n
DIFFIO_T8p
DIFFIO_T7n
DIFFIO_T7p
DIFFIO_T6n
DIFFIO_T6p
VREFB8N2
DIFFIO_T4n
DIFFIO_T4p
DIFFIO_T3n
DIFFIO_T3p
DIFFIO_T2n
DIFFIO_T2p
DIFFIO_T1n
DIFFIO_T1p
PLL2_CLKOUTn
PLL2_CLKOUTp
PLL7_CLKOUTn
PLL7_CLKOUTp
PLL8_CLKOUTn
PLL8_CLKOUTp
IO_8
IO
BANK8
U9
EP4CGX110DF27
L15
L14
K14
VCC_CLKIN8A
DIFFCLK_4n-REFCLK3n
DIFFCLK_4p-REFCLK3p
BANK8A
U9
EP4CGX110DF27
L9
K9
L10
K10
J9VCC_CLKIN8B
DIFFCLK_8n
DIFFCLK_8p-CLKIO17
DIFFCLK_9n
DIFFCLK_9p-CLKIO19
BANK8B
0ohms
0ohms
0ohms
0ohms
0ohms
0ohms
0ohms
R100
10Kohms
DGND
+3.3V
+2.5V
100o
hms
R36
100o
hms
R37
+3.3V
GPIO_3V3[0:12]
TP2
FD[0
:15]
PA[0
:7]
R17
0ohms
DGND
DGND
DGND
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
FD[5]
FD[6]
FD[7]
FD[8]
FD[9]
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
USB_CLKOUT
USB_IFCLK
USB_CTL0
USB_CTL1
USB_CTL2
USB_RDY0
USB_RDY1
USB_WAKEUP DAC_11
GPIO_3V3[7]
GPIO_3V3[3]
GPIO_3V3[2]
DAC_22
DAC_21
FPGA_TO_JC[5]
JC_SPI[2]
JC_SPI[2]
DAC_14
GPIO_3V3[4]
SMA_TRIG
DAC_23
FPGA_TO_JC[2]
DAC_13
FPGA_TO_JC[1]
GPIO_3V3[5]
GPIO_3V3[8]
GPIO_3V3[6]
FPGA_TO_JC[4]
FPGA_TO_JC[3]
DAC_24
GPIO_3V3[0]
JC_SPI[0]
JC_SPI[0]
GPIO_3V3[11]
GPIO_3V3[10]
GPIO_3V3[9]
JC_SPI[3]
JC_SPI[3]
GPIO_3V3[1]
GPIO_3V3[12]
DAC_10
FPGA_CLKOUT
CLK40_TO_FPGA
FPGA_TO_JC[6]
DAC_20
DAC_12
JC_SPI[1]
JC_SPI[1]
CLK_IN_REF0+
CLK_IN_REF1-
CLK_IN_REF1+
CLK_IN_REF0-
GPIO_3V3[0:12]
FD[0:15]
PA[0:7]
PSEC_DAC_SPI[0:9]
FPGA_TO_JC[6:0]
USB_
AUX[
0:7]
JC_SPI[0:3]
BANK8
6 6 10-02-2012_14:42
C3
FPGA
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
0.00
47u
F
C191
2
1
0.00
47u
F
C192
2
1
0.00
47u
F
C193
2
1
0.00
47u
F
C194
2
1
0.00
47u
F
C195
2
1
0.00
47u
F
C196
2
1
0.00
47u
F
C197
2
1
0.00
47u
F
C198
2
1
0.00
47u
F
C199
2
1
10u
F
2
1
10u
F
2
1
10u
F
2
1
1uFC32
2
1
1uF
2
1
0.01
uF
2
1
0.01
uF
2
1
0.01
uF
2
1
10u
F
C255
2
1+
10u
F
C66
2
1
10u
F
C67
2
1
0.01
uF
2
1
0.1u
F
C23
2
1
0.01
uF
C166
2
1
1uF
C108
2
1
10u
F
C68
2
1
0.00
1uF
C232
2
1
0.00
47u
F
C200
2
1
0.00
47u
F
C201
2
10.
001u
FC233
2
1
10u
F
C69
2
1
1uF
C111
2
1
0.01
uF
C167
2
1
0.1u
F
C33
2
1
10u
F
C71
2
1
10u
F
C256
2
1+
0.00
47u
F
C202
2
1
0.00
47u
F
C21
1
2
1
0.00
47u
F
C21
2
2
1
0.00
47u
F
C21
3
2
1
0.00
47u
F
C21
4
2
1
0.00
47u
F
C21
5
2
1
0.00
47u
F
C21
6
2
1
0.00
47u
F
C21
7
2
1
0.00
47u
F
C21
8
2
1
0.00
47u
F
C21
9
2
1
10u
F
2
1
10u
F
2
1
10u
F
2
1
0.00
1uF
2
1
10u
F
2
1
10u
FC28
2
1
10u
FC
257
2
1+
10u
FC
72
2
1
10u
FC
73
2
1
0.1u
FC
43
2
1
0.01
uF
C18
6
2
1
1uF
C12
9
2
1
10u
FC
74
2
1
0.00
47u
F
C22
0
2
1
+1.2V
DGND
DGND
DGND
+2.5V
+3.3V
FB4
BLM15HD102SN1D
0.00
47u
F
C221
2
1
0.00
1uF
C253
2
1
0.1u
F
C53
2
1
0.01
uF
C187
2
1
DGND
DGND
0.00
47u
F
C222
2
1
0.01
uF
C188
2
1
0.1u
F
C54
2
1
0.00
1uF
C254
2
1
BLM15HD102SN1D
FB5
+1.2V
+2.5V
VCCD_PLL
VCCA
DECO
UPLI
NG N
ETW
ORK
1 1 15-11-2011_17:13
0
USB
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
2_U1
pn-CY7C6803_56
52
55
56
54
2
3
1
34
37
33 4835
40
17
26
25
21
47
32
296
28
14
46
44
15
2474
5018
19
3812 11
5
4939
13
42
10
45
41
43
22
51
20
30
27
31
16
23
9
36
8
53FD9
RDY0
CTL0
RDY1
SDA
Dn
FD6
FD2
FD5
IFCLK
_WAKEUP
SCL
PA3
PA1
PA5
AVCC
1
PA2
AGND
1
VCC5
_RESET
CLKOUT
XTAL
OUT
XTAL
INCTL2
GND
3
VCC2
VCC6
GND
1
GND
2VC
C3
Dp
PA4
PA6
AVCC
2
FD3VC
C1FD4
FD7
PA7
Reserved
FD0
FD1
AGND
2
PA0
GND
5
GND
6
GND
4
CTL1
VCC4
FD13
FD15
FD14
FD10
FD12
FD11
FD8
2_U2
pn-TPS3828_33
2
5
4
1
3
_MR
_RST
WDI
VDD
GND
2_U3
pn-24LC65_SM
8
7
4
6
5
3
2
1A0
A1
A2
SDA
SCL
VSS
NC
VCC
2_U4
LM317_T 2
1
3VIN
ADJ
VOUT
2_C17
0.1uF
FD[0:15]
PA[0:7]
2_F
B1
BLM
15H
D10
2SN
1D
+3.3V_USB
+3.3V_USB
+3.3V_USB
2_R1240ohms
2_R2390ohms
2_C1
10uF
+
2_C2
10uF21
+
2_R3
0ohms
2_R4 10Ko
hms
10Ko
hms
2_R5
+3.3v_USBUSB_AUX[0:7]2_Y1
24MHZ_CRYSTAL
12
2_C4
22pF 2
22pF
2_C5
2
1
2_C6
0.1uF 0.1uF
2_C7
0.1uF
2_C8
0.1uF
2_C9
0.1uF
2_C10
0.1uF
2_C11
0.1uF
2_C12
0.1uF
2_C13
0.1uF
2_C14
0.1uF
2_C15 2_C3
10uF
+2_C16
1uF
+3.3V_USB
2_R6
10Ko
hms
2_R8
1Koh
ms
2_JP
1
12
2_R9
1Koh
ms
10Ko
hms
2_R7
2_J1
61729-1010BLF
5
6
4
1
23 D+
D-
+5VDC
GND
SHD1
SHD2
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
USB_CLKOUT
USB_IFCLK
USB_CTL0
USB_CTL1
USB_CTL2
USB_RDY0
USB_RDY1
USB_WAKEUP
1 3 23-01-2012_11:48
C2
CONNECTORS
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
CLK40+
CLK40-
JC_SMA
J2
A00-216-262-450
109
87
54
21 1
23
45
6
78
SHD1SHD2
910
11
1213
14
1516
SHD3
J3
142-0711-201
GND
PIN
R11
0ohms
DGND
142-0711-201
J4 GND
PIN 0ohms
R12
R1810Kohms
10Kohms
DGND
+3.3V
SMA_TRIG
0ohms
R13
142-0711-201
J5
GND
PIN
DGND
DGND
J9
A00-108-262-450
SHD1
3
12
3
45
6
78
SHD1
SHD2
CLK_IN_REF[0:8]
DGND
DGND
0ohms
R14
142-0711-201
J6
GND
PIN
142-0711-201
GND
PIN0ohms
R15
DGND
DGND
0ohms
R16
142-0711-201
GND
PIN
GPIO_2V5[0:29]
DGND
J10
CONN_10PIN
1010
99
88
77
66
55
44
33
22
11
GPIO_3V3[0:12]
GPIO_1V2[0:23]
FPGA_CLKOUT
CLK_IN_REF0+CLK_IN_REF0-
CLK_IN_REF2+CLK_IN_REF2-
CLK_IN_REF3+CLK_IN_REF3-
CLK_IN_REF1+
CLK_IN_REF1-
CLK_OUT_2v5[0]
CLK_OUT_1v2[0]
CLK_OUT_1v2[0]
CLK_IN_REF[8]
CLK_OUT_1v2[1]
CLK_OUT_1v2[2]
CLK_OUT_1v2[3]
CLK_OUT_2v5[1]
CLK_OUT_2v5[2]
CLK_OUT_2v5[3]
CLK_OUT_2v5[4]
CLK_OUT_2v5[5]
LVDS_RX_P[1]
LVDS_RX_P[1]
LVDS_RX_N[0]
LVDS_RX_N[0]LVDS_RX_P[0]
LVDS_RX_P[0]
LVDS_TX_P[0]
LVDS_TX_P[0]
LVDS_TX_N[0]
LVDS_TX_N[0]
LVDS_TX_P[1]
LVDS_TX_P[1]
LVDS_TX_P[3]
LVDS_TX_P[3]
LVDS_TX_N[3]
LVDS_TX_N[3]
LVDS_RX_P[2]
LVDS_RX_P[2]
LVDS_RX_N[2]
LVDS_RX_N[2]
LVDS_TX_N[2]
LVDS_TX_N[2]
LVDS_TX_P[2]
LVDS_TX_P[2]
LVDS_RX_N[1]
LVDS_RX_N[1]
LVDS_TX_N[1]
LVDS_TX_N[1]
CLK_IN_REF[0:8]
CLK_OUT_1v2[0:3]
CLK_OUT_2v5[0:5]
CC_COMM[0:13]
CONN
ECTO
RS
C2
13-02-2012_13:32C.Harabedian
CONNECTORS
32
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
J12
CONN_14PIN
11
33
55
77
99
1111
1313
22
44
66
88
1010
1212
1414
DGND
J13
CONN_30PIN
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
11
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
DGND
+1.2V
DGND
CONN_30PIN
J14
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
11
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
R41
0ohms
CLK_OUT_1v2[1]
CLK_OUT_1v2[2]
CLK_OUT_1v2[3]
GPIO_3V3[0]
GPIO_3V3[1]
GPIO_3V3[2]
GPIO_3V3[3]
GPIO_3V3[4]
GPIO_3V3[5]
GPIO_3V3[6]
GPIO_3V3[7]
GPIO_3V3[8]
GPIO_3V3[9]
GPIO_3V3[10]
GPIO_3V3[11]
GPIO_3V3[12]
GPIO_2V5[0]
GPIO_2V5[1]
GPIO_2V5[2]
GPIO_2V5[3]
GPIO_2V5[4]
GPIO_2V5[5]
GPIO_2V5[6]
GPIO_2V5[7]
GPIO_2V5[8]
GPIO_2V5[9]
GPIO_2V5[10]
GPIO_2V5[11]
GPIO_2V5[12]
GPIO_2V5[13]
GPIO_2V5[14] GPIO_2V5[15]
GPIO_2V5[16]
GPIO_2V5[17]
GPIO_2V5[18]
GPIO_2V5[19]
GPIO_2V5[20]
GPIO_2V5[21]
GPIO_2V5[22]
GPIO_2V5[23]
GPIO_2V5[24]
GPIO_2V5[25]
GPIO_2V5[26]
GPIO_2V5[27]
GPIO_2V5[28]
GPIO_2V5[29]
GPIO_1V2[0]
GPIO_1V2[1]
GPIO_1V2[2]
GPIO_1V2[3]
GPIO_1V2[4]
GPIO_1V2[5]
GPIO_1V2[6]
GPIO_1V2[7]
GPIO_1V2[8]
GPIO_1V2[9]
GPIO_1V2[10]
GPIO_1V2[11]
GPIO_1V2[12]
GPIO_1V2[13]
GPIO_1V2[14]
GPIO_1V2[15]
GPIO_1V2[16]
GPIO_1V2[17]
GPIO_1V2[18]
GPIO_1V2[19]
GPIO_1V2[20]
GPIO_1V2[21]
GPIO_3V3[0:12]
GPIO_1V2[0:23]
GPIO_2V5[0:29]
14pin Header
DEBU
G H
EADE
RS
25oh
ms
R50
25oh
ms
R51
25oh
ms
R52
25oh
ms
R53
WP1
503E
B_2S
RD
D1
A0
C0 CA
WP1
503E
B_2S
RD
D2
A1
C1 CA
WP1
503E
B_2S
RD
D3
A1
C1 CA
WP1
503E
B_2S
RD
D4
A0
C0 CA
WP1
503E
B_2S
RD
D5
A1
C1 CA
25oh
ms
R54
25oh
ms
R55
25oh
ms
R56
25oh
ms
R57
25oh
ms
R58
WP1
503E
B_2S
RD
D1
A1
C1 CA
WP1
503E
B_2S
RD
D6
A1
C1 CA
WP1
503E
B_2S
RD
D3
A0
C0 CA
WP1
503E
B_2S
RD
D7
A0
C0 CA
WP1
503E
B_2S
RD
D2
A0
C0 CA
25oh
ms
R59
3 3 09-01-2012_16:15
C2
CONNECTORS
C.Harabedian
REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
25oh
ms
R60
WP1
503E
B_2S
RD
D7
A1
C1 CA
WP1
503E
B_2S
RD
D8
A1
C1 CA
WP1
503E
B_2S
RD
D9
A0
C0 CA
25oh
ms
R61
25oh
ms
R62
25oh
ms
R63
WP1
503E
B_2S
RD
D8
A0
C0 CA
WP1
503E
B_2S
RD
D6
A0
C0 CA
WP1
503E
B_2S
RD
D9
A1
C1 CA
WP1
503E
B_2S
RD
D5
A0
C0 CA
WP1
503E
B_2S
RD
D4
A1
C1 CA
25oh
ms
R64
25oh
ms
R65
25oh
ms
R66
25oh
ms
R67
+2.5V
GPIO_2V5[0:29]
GPI
O_2
V5[1
2]
GPI
O_2
V5[1
3]
GPI
O_2
V5[1
4]
GPI
O_2
V5[1
5]
GPI
O_2
V5[1
6]
GPI
O_2
V5[1
7]
GPI
O_2
V5[1
8]
GPI
O_2
V5[1
9]
GPI
O_2
V5[2
0]
GPI
O_2
V5[2
1]
GPI
O_2
V5[2
2]
GPI
O_2
V5[2
3]
GPI
O_2
V5[2
4]
GPI
O_2
V5[2
5]
GPI
O_2
V5[2
6]
GPI
O_2
V5[2
7]
GPI
O_2
V5[2
8]
GPI
O_2
V5[2
9]
GPIO_2V5[0:29]
REMOVE LEDS TO USE GPIO_2V5[12:29] ON 30PIN HEADER
FPG
A LE
Ds
C.Harabedian 19-12-2011_08:43
LVDS_TX_RESISTORS
11
0REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
R75
120ohms
R83170ohms
120ohms
R76
OUT_N
OUT_PIN_P
IN_N
C.Harabedian 19-12-2011_08:43
LVDS_TX_RESISTORS
11
0REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
R77
120ohms
R84170ohms
120ohms
R78
OUT_N
OUT_PIN_P
IN_N
C.Harabedian 19-12-2011_08:43
LVDS_TX_RESISTORS
11
0REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
R79
120ohms
R85170ohms
120ohms
R80
OUT_N
OUT_PIN_P
IN_N
C.Harabedian 19-12-2011_08:43
LVDS_TX_RESISTORS
11
0REV
2 134
4 3 2 1
TITLE
SCALE
SIZE Board
A
B B
A
SHEET
BofDRAWN BY
University of ChicagoEnrico Fermi Institute
Electronics Design Group
Project
R81
120ohms
R86170ohms
120ohms
R82
OUT_N
OUT_PIN_P
IN_N
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
GPIO_1v2[0:23] : OUT (*)
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT DIFFIO_B53n : BI#
GPIO_1v2[0:23] : OUT DIFFIO_B72p : BI#
GPIO_1v2[0:23] : OUT DIFFIO_B63p : BI#
GPIO_1v2[0:23] : OUT DIFFIO_B63n : BI#
GPIO_1v2[0:23] : OUT DIFFIO_B51n : BI#
GPIO_1v2[0:23] : OUT DIFFIO_B51p : BI#
GPIO_1v2[0:23] : OUT
GPIO_1v2[0:23] : OUT
CLK_OUT_1V2[0:3] : OUT (*)
CLK_OUT_1V2[0:3] : OUT
CLK_OUT_1V2[0:3] : OUT
CLK_OUT_1V2[0:3] : OUT PLL3_CLKOUTp : BI#
CLK_OUT_1V2[0:3] : OUT PLL3_CLKOUTn : BI#
PSEC_ChanDECODE[0:14] : OUT (*)
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B62p : BI#
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B57p : BI#
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B72n : BI#
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B64p : BI#
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B57n : BI#
PSEC_ChanDECODE[0:14] : OUT DIFFIO_B62n : BI#
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
PSEC_ChanDECODE[0:14] : OUT
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
+
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
+
+
+
+
+
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
+
+
+
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
(*)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
(*)
...
...
+
(*) (*) (*)
...
...
...
...
...
...
...
...
...
$912I1Resistor.1
GPIO_1v2[0:23] / FPGA_BANKS4-5-6-7
GPIO_1v2[0] / FPGA_BANKS4-5-6-7
GPIO_1v2[1] / FPGA_BANKS4-5-6-7
GPIO_1v2[2] / FPGA_BANKS4-5-6-7
GPIO_1v2[3] / FPGA_BANKS4-5-6-7
GPIO_1v2[4] / FPGA_BANKS4-5-6-7
GPIO_1v2[5] / FPGA_BANKS4-5-6-7
GPIO_1v2[6] / FPGA_BANKS4-5-6-7
GPIO_1v2[7] / FPGA_BANKS4-5-6-7
GPIO_1v2[8] / FPGA_BANKS4-5-6-7
GPIO_1v2[9] / FPGA_BANKS4-5-6-7
GPIO_1v2[10] / FPGA_BANKS4-5-6-7
GPIO_1v2[11] / FPGA_BANKS4-5-6-7
GPIO_1v2[12] / FPGA_BANKS4-5-6-7
GPIO_1v2[13] / FPGA_BANKS4-5-6-7
GPIO_1v2[14] / FPGA_BANKS4-5-6-7
GPIO_1v2[15] / FPGA_BANKS4-5-6-7
GPIO_1v2[16] / FPGA_BANKS4-5-6-7
GPIO_1v2[17] / FPGA_BANKS4-5-6-7
GPIO_1v2[18] / FPGA_BANKS4-5-6-7
GPIO_1v2[19] / FPGA_BANKS4-5-6-7
GPIO_1v2[20] / FPGA_BANKS4-5-6-7
GPIO_1v2[21] / FPGA_BANKS4-5-6-7
GPIO_1v2[22] / FPGA_BANKS4-5-6-7
GPIO_1v2[23] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0:3] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[0] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[1] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[2] / FPGA_BANKS4-5-6-7
CLK_OUT_1V2[3] / FPGA_BANKS4-5-6-7
PSEC_ChanDECODE[0:14] / FPGA_BANKS4-5-6-7
ChanDECODE0_A / FPGA_BANKS4-5-6-7
ChanDECODE0_B / FPGA_BANKS4-5-6-7
ChanDECODE0_C / FPGA_BANKS4-5-6-7
ChanDECODE0_D / FPGA_BANKS4-5-6-7
ChanDECODE0_E / FPGA_BANKS4-5-6-7
ChanDECODE2_E / FPGA_BANKS4-5-6-7
ChanDECODE2_D / FPGA_BANKS4-5-6-7
ChanDECODE2_C / FPGA_BANKS4-5-6-7
ChanDECODE2_B / FPGA_BANKS4-5-6-7
ChanDECODE2_A / FPGA_BANKS4-5-6-7
ChanDECODE1_E / FPGA_BANKS4-5-6-7
ChanDECODE1_D / FPGA_BANKS4-5-6-7
ChanDECODE1_C / FPGA_BANKS4-5-6-7
ChanDECODE1_B / FPGA_BANKS4-5-6-7
ChanDECODE1_A / FPGA_BANKS4-5-6-7
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
PSEC_DATA[0:59] : OUT (*)
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B45n : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B58n : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B58p : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B45p : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B42n : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B43n : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B43p : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B48p : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B53p : BI#
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
+
+
+
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
+
+
+
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7 +
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
(*) (*) (*)
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$912I1Resistor.1
PSEC_DATA[0:59] / FPGA_BANKS4-5-6-7
DATA0_A / FPGA_BANKS4-5-6-7
DATA0_B / FPGA_BANKS4-5-6-7
DATA0_C / FPGA_BANKS4-5-6-7
DATA0_D / FPGA_BANKS4-5-6-7
DATA0_E / FPGA_BANKS4-5-6-7
DATA10_A / FPGA_BANKS4-5-6-7
DATA10_B / FPGA_BANKS4-5-6-7
DATA10_C / FPGA_BANKS4-5-6-7
DATA10_D / FPGA_BANKS4-5-6-7
DATA10_E / FPGA_BANKS4-5-6-7
DATA11_A / FPGA_BANKS4-5-6-7
DATA11_B / FPGA_BANKS4-5-6-7
DATA11_C / FPGA_BANKS4-5-6-7
DATA11_E / FPGA_BANKS4-5-6-7
DATA1_A / FPGA_BANKS4-5-6-7
DATA11_D / FPGA_BANKS4-5-6-7
DATA1_C / FPGA_BANKS4-5-6-7
DATA1_D / FPGA_BANKS4-5-6-7
DATA1_B / FPGA_BANKS4-5-6-7
DATA1_E / FPGA_BANKS4-5-6-7
DATA2_B / FPGA_BANKS4-5-6-7
DATA2_C / FPGA_BANKS4-5-6-7
DATA2_A / FPGA_BANKS4-5-6-7
DATA2_D / FPGA_BANKS4-5-6-7
DATA2_E / FPGA_BANKS4-5-6-7
DATA3_A / FPGA_BANKS4-5-6-7
DATA3_B / FPGA_BANKS4-5-6-7
DATA3_C / FPGA_BANKS4-5-6-7
DATA3_D / FPGA_BANKS4-5-6-7
DATA3_E / FPGA_BANKS4-5-6-7
DATA4_B / FPGA_BANKS4-5-6-7
DATA4_D / FPGA_BANKS4-5-6-7
DATA4_A / FPGA_BANKS4-5-6-7
DATA4_C / FPGA_BANKS4-5-6-7
DATA4_E / FPGA_BANKS4-5-6-7
DATA5_A / FPGA_BANKS4-5-6-7
DATA5_B / FPGA_BANKS4-5-6-7
DATA5_C / FPGA_BANKS4-5-6-7
DATA5_D / FPGA_BANKS4-5-6-7
DATA5_E / FPGA_BANKS4-5-6-7
DATA6_A / FPGA_BANKS4-5-6-7
DATA6_B / FPGA_BANKS4-5-6-7
DATA6_C / FPGA_BANKS4-5-6-7
DATA6_D / FPGA_BANKS4-5-6-7
DATA6_E / FPGA_BANKS4-5-6-7
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B54p : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B55n : BI#
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT
PSEC_DATA[0:59] : OUT DIFFIO_B55p : BI#
PSEC_TRIG[0:29] : OUT (*)
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B48n : BI#
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B47n : BI#
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B47p : BI#
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B52n : BI#
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B52p : BI#
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT
PSEC_TRIG[0:29] : OUT DIFFIO_B54n : BI#
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
+
+
+
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
+
+
+
+
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
...
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RDN3 : B...
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(*) (*) (*)
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$912I1Resistor.1
DATA7_A / FPGA_BANKS4-5-6-7
DATA7_B / FPGA_BANKS4-5-6-7
DATA7_D / FPGA_BANKS4-5-6-7
DATA7_E / FPGA_BANKS4-5-6-7
DATA8_A / FPGA_BANKS4-5-6-7
DATA7_C / FPGA_BANKS4-5-6-7
DATA8_C / FPGA_BANKS4-5-6-7
DATA8_B / FPGA_BANKS4-5-6-7
DATA8_D / FPGA_BANKS4-5-6-7
DATA8_E / FPGA_BANKS4-5-6-7
DATA9_A / FPGA_BANKS4-5-6-7
DATA9_B / FPGA_BANKS4-5-6-7
DATA9_C / FPGA_BANKS4-5-6-7
DATA9_D / FPGA_BANKS4-5-6-7
DATA9_E / FPGA_BANKS4-5-6-7
PSEC_TRIG[0:29] / FPGA_BANKS4-5-6-7
TRIG1_A / FPGA_BANKS4-5-6-7
TRIG1_B / FPGA_BANKS4-5-6-7
TRIG1_C / FPGA_BANKS4-5-6-7
TRIG1_D / FPGA_BANKS4-5-6-7
TRIG1_E / FPGA_BANKS4-5-6-7
TRIG2_A / FPGA_BANKS4-5-6-7
TRIG2_B / FPGA_BANKS4-5-6-7
TRIG2_C / FPGA_BANKS4-5-6-7
TRIG2_D / FPGA_BANKS4-5-6-7
TRIG2_E / FPGA_BANKS4-5-6-7
TRIG3_A / FPGA_BANKS4-5-6-7
TRIG3_C / FPGA_BANKS4-5-6-7
TRIG3_D / FPGA_BANKS4-5-6-7
TRIG3_B / FPGA_BANKS4-5-6-7
TRIG3_E / FPGA_BANKS4-5-6-7
TRIG4_A / FPGA_BANKS4-5-6-7
TRIG4_C / FPGA_BANKS4-5-6-7
TRIG4_B / FPGA_BANKS4-5-6-7
TRIG4_D / FPGA_BANKS4-5-6-7
TRIG4_E / FPGA_BANKS4-5-6-7
TRIG5_A / FPGA_BANKS4-5-6-7
TRIG5_B / FPGA_BANKS4-5-6-7
TRIG5_C / FPGA_BANKS4-5-6-7
TRIG5_D / FPGA_BANKS4-5-6-7
TRIG5_E / FPGA_BANKS4-5-6-7
TRIG6_A / FPGA_BANKS4-5-6-7
TRIG6_B / FPGA_BANKS4-5-6-7
TRIG6_C / FPGA_BANKS4-5-6-7
TRIG6_D / FPGA_BANKS4-5-6-7
TRIG6_E / FPGA_BANKS4-5-6-7
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
PSEC_Rd_Clk[0:4] : OUT
PSEC_Rd_Clk[0:4] : OUT
PSEC_Rd_Clk[0:4] : OUT
PSEC_Rd_Clk[0:4] : OUT
PSEC_Rd_Clk[0:4] : OUT
PSEC_Rd_Clk[0:4] : OUT
PSEC_to_FPGA[0:14] : IN (*)
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN DIFFIO_B59p : BI#
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN DIFFCLK_6p : BI#
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN
PSEC_to_FPGA[0:14] : IN DIFFIO_B64n : BI#
PSEC_to_FPGA[0:14] : IN DIFFIO_B50n : BI#
PSEC_from_FPGA[0:46] : OUT (*)
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B61p : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B70p : BI#
PSEC_from_FPGA[0:46] : OUT DIFFIO_B39n : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B68n : BI#
PSEC_from_FPGA[0:46] : OUT DIFFIO_B41p : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B68p : BI#
PSEC_from_FPGA[0:46] : OUT DIFFIO_B50p : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
+
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
+
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
(*) (*) (*) (*) (*)
2 : A... +
... +
... +
...
...
(*) (*) (*)
...
...
...
...
...
...
...
...
...
...
...
(*) (*) (*)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
IO : BI#
...
$912I1Resistor.1
PSEC_Rd_Clk[0:4] / FPGA_BANKS4-5-6-7
Rd_CLk_A / FPGA_BANKS4-5-6-7
Rd_CLk_B / FPGA_BANKS4-5-6-7
Rd_CLk_C / FPGA_BANKS4-5-6-7
Rd_CLk_D / FPGA_BANKS4-5-6-7
Rd_CLk_E / FPGA_BANKS4-5-6-7
PSEC_to_FPGA[0:14] / FPGA_BANKS4-5-6-7
DATA_ovflw_A / FPGA_BANKS4-5-6-7
DATA_ovflw_B / FPGA_BANKS4-5-6-7
DATA_ovflw_C / FPGA_BANKS4-5-6-7
DATA_ovflw_D / FPGA_BANKS4-5-6-7
DATA_ovflw_E / FPGA_BANKS4-5-6-7
Dlout_A / FPGA_BANKS4-5-6-7
Dlout_B / FPGA_BANKS4-5-6-7
Dlout_C / FPGA_BANKS4-5-6-7
Dlout_D / FPGA_BANKS4-5-6-7
Dlout_E / FPGA_BANKS4-5-6-7
RO_mon_A / FPGA_BANKS4-5-6-7
RO_mon_B / FPGA_BANKS4-5-6-7
RO_mon_C / FPGA_BANKS4-5-6-7
RO_mon_D / FPGA_BANKS4-5-6-7
RO_mon_E / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] / FPGA_BANKS4-5-6-7
DLLreset_A / FPGA_BANKS4-5-6-7
DLLreset_B / FPGA_BANKS4-5-6-7
DLLreset_C / FPGA_BANKS4-5-6-7
DLLreset_D / FPGA_BANKS4-5-6-7
DLLreset_E / FPGA_BANKS4-5-6-7
ADClatch_A / FPGA_BANKS4-5-6-7
ADClatch_B / FPGA_BANKS4-5-6-7
ADClatch_C / FPGA_BANKS4-5-6-7
ADClatch_D / FPGA_BANKS4-5-6-7
ADClatch_E / FPGA_BANKS4-5-6-7
EXT_trig_A / FPGA_BANKS4-5-6-7
EXT_trig_B / FPGA_BANKS4-5-6-7
EXT_trig_C / FPGA_BANKS4-5-6-7
EXT_trig_D / FPGA_BANKS4-5-6-7
EXT_trig_E / FPGA_BANKS4-5-6-7
FREQsel_global / FPGA_BANKS4-5-6-7
RO_enable_A / FPGA_BANKS4-5-6-7
RO_enable_B / FPGA_BANKS4-5-6-7
RO_enable_C / FPGA_BANKS4-5-6-7
RO_enable_D / FPGA_BANKS4-5-6-7
RO_enable_E / FPGA_BANKS4-5-6-7
TOKin1_A / FPGA_BANKS4-5-6-7
TOKin1_B / FPGA_BANKS4-5-6-7
(*)
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B69n : BI#
PSEC_from_FPGA[0:46] : OUT DIFFIO_B42p : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B67p : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B61n : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B70n : BI#
PSEC_from_FPGA[0:46] : OUT DIFFIO_B41n : BI#
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT
PSEC_from_FPGA[0:46] : OUT DIFFIO_B59n : BI#
PSEC_TokDECODE[0:14] : OUT (*)
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT DIFFIO_B65p : BI#
PSEC_TokDECODE[0:14] : OUT DIFFIO_B37p : BI#
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT DIFFIO_B65n : BI#
PSEC_TokDECODE[0:14] : OUT DIFFIO_B37n : BI#
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT
PSEC_TokDECODE[0:14] : OUT DIFFIO_B69p : BI#
PSEC_TokDECODE[0:14] : OUT DIFFIO_B39p : BI#
DIFFIO_B67n : BI#
CLK_IN_REF[8] : OUT
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
+
+
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
+
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
+
+
+
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
+
+
+
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
(*) (*) (*)
...
...
...
...
...
...
...
...
...
... ... +
... ... +
... ...
...
...
... 1 : A... +
$912I1Resistor.1
TOKin1_C / FPGA_BANKS4-5-6-7
TOKin1_D / FPGA_BANKS4-5-6-7
TOKin1_E / FPGA_BANKS4-5-6-7
TOKin2_A / FPGA_BANKS4-5-6-7
TOKin2_B / FPGA_BANKS4-5-6-7
TOKin2_C / FPGA_BANKS4-5-6-7
TOKin2_D / FPGA_BANKS4-5-6-7
TOKin2_E / FPGA_BANKS4-5-6-7
trigCLEAR_A / FPGA_BANKS4-5-6-7
trigCLEAR_B / FPGA_BANKS4-5-6-7
trigCLEAR_C / FPGA_BANKS4-5-6-7
trigCLEAR_D / FPGA_BANKS4-5-6-7
trigCLEAR_E / FPGA_BANKS4-5-6-7
trigSIGN_global / FPGA_BANKS4-5-6-7
clearADC_A / FPGA_BANKS4-5-6-7
clearADC_B / FPGA_BANKS4-5-6-7
clearADC_C / FPGA_BANKS4-5-6-7
clearADC_D / FPGA_BANKS4-5-6-7
clearADC_E / FPGA_BANKS4-5-6-7
rampSTART_A / FPGA_BANKS4-5-6-7
rampSTART_B / FPGA_BANKS4-5-6-7
rampSTART_C / FPGA_BANKS4-5-6-7
rampSTART_D / FPGA_BANKS4-5-6-7
rampSTART_E / FPGA_BANKS4-5-6-7
PSEC_TokDECODE[0:14] / FPGA_BANKS4-5-6-7
TokDECODE0_A / FPGA_BANKS4-5-6-7
TokDECODE0_B / FPGA_BANKS4-5-6-7
TokDECODE0_C / FPGA_BANKS4-5-6-7
TokDECODE0_D / FPGA_BANKS4-5-6-7
TokDECODE0_E / FPGA_BANKS4-5-6-7
TokDECODE1_A / FPGA_BANKS4-5-6-7
TokDECODE1_B / FPGA_BANKS4-5-6-7
TokDECODE1_C / FPGA_BANKS4-5-6-7
TokDECODE1_D / FPGA_BANKS4-5-6-7
TokDECODE1_E / FPGA_BANKS4-5-6-7
TokDECODE2_A / FPGA_BANKS4-5-6-7
TokDECODE2_B / FPGA_BANKS4-5-6-7
TokDECODE2_C / FPGA_BANKS4-5-6-7
TokDECODE2_D / FPGA_BANKS4-5-6-7
TokDECODE2_E / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_B / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_C / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_D / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_E / FPGA_BANKS4-5-6-7
CLK_IN_REF[8] / FPGA_BANKS4-5-6-7
RES_TO_RD_CLK_A / FPGA_BANKS4-5-6-7
1 : A...
FPGA_BANKS4-5-6-7 $75I1EP4CGX110DF27_Bank4.1 VCCIO4_0 VCCIO4_1 VCCIO4_2 VCCIO4_3
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
DGND : BI ...
FPGA_ACARD_PWR : IN ... + + + +
VCCIO4_4 VCCIO4_5 DIFFCLK_6p DIFFCLK_6n DIFFIO_B37p DIFFIO_B37n DIFFIO_B39p DIFFIO_B39n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
+ +
VREFB4N2 DIFFIO_B41p DIFFIO_B41n DIFFIO_B42p DIFFIO_B42n DIFFIO_B43p DIFFIO_B43n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
DIFFIO_B45p DIFFIO_B45n DIFFIO_B47p DIFFIO_B47n DIFFIO_B48p DIFFIO_B48n DIFFIO_B49p
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
DIFFIO_B49n DIFFIO_B50p DIFFIO_B50n DIFFIO_B51p DIFFIO_B51n DIFFIO_B52p DIFFIO_B52n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
DIFFIO_B53p DIFFIO_B53n VREFB4N1 DIFFIO_B54p DIFFIO_B54n DIFFIO_B55p DIFFIO_B55n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
DIFFIO_B57p DIFFIO_B57n DIFFIO_B58p DIFFIO_B58n DIFFIO_B59p DIFFIO_B59n DIFFIO_B61p
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
DIFFIO_B61n DIFFIO_B62p DIFFIO_B62n DIFFIO_B63p DIFFIO_B63n DIFFIO_B64p DIFFIO_B64n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
DIFFIO_B65p DIFFIO_B65n VREFB4N0 DIFFIO_B67p DIFFIO_B67n DIFFIO_B68p DIFFIO_B68n
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+
DIFFIO_B69p DIFFIO_B69n DIFFIO_B70p DIFFIO_B70n DIFFIO_B72p DIFFIO_B72n PLL3_CLKOUTp
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
PLL3_CLKOUTn RUP2 RDN2$75I2
EP4CGX110DF27_Bank5.1$75I3
EP4CGX110DF27_Bank6.1$75I4
EP4CGX110DF27_Bank7.1$75I8
Resistor.1$77I2
Resistor.1$77I6
Resistor.1 1 2$77I9
Resistor.1 1 2$77I12
Resistor.1 1 2
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
+ + ... ... ...
...
... ... ...
$912I1Resistor.1
DGND / FPGA_BANKS4-5-6-7
+1.2V / FPGA_BANKS4-5-6-7
TERM_R_TRIG_SIGN / FPGA_BANKS4-5-6-7
+2.5v / FPGA_BANKS4-5-6-7
FPGA_ACARD_PWR / FPGA_BANKS4-5-6-7
2 : A...
