PSB beam control mezzanine boards Time-table

4 Channel DAC (Petri): 3 boards available for testing (version 1) -> nowTransition board -> 22/12/2010End of Hardware tests -> 28/01/2011 Attached DDC firmware -> 28/03/2011

Clock distribution (Petri): 3 boards available for testing (version 1) -> nowTransition board -> 22/12/2010

4 Channel ADC (Jorge): prototype (version 1) -> 01/03/2011End of hardware tests -> 07/04/2011

Master DDS (Jorge): prototype (or version 1) -> 7/02/2011End of hardware tests -> 15/03/2011Attached firmware -> 30/03/2011

Add 1 month for each board for tests with the motherboard when available Add 2 months for each unit in case another version is necessary

PSB beam control mezzanine boardsTime-table

Alfred BLAS Working group meeting 25/11/2010 1

http://upload.wikimedia.org/wikipedia/sh/4/42/CERN_logo_400x400.gif

Jorge’s time requirements:

MDDS: 2 weeks design time (present work)ADC transition board design (from Petri’s transition board): 2 days

Both should be finished end of December

Extra work in 2011 (total 11 weeks)

ADC test firmware: 1 weekMDDS test firmware: 1 week(these 2 before Mid February)

ADC tests: 1.5 weeks (after mid-February)MDDS tests : 1.5 weeks (after last week of February)DDC firmware + tests: 6 weeks

Key dates:ADC transition board assembled: Mid-FebruaryMDDS boards ready for tests: Last week of February

Most convenient periods for Jorge’s DC work:All February + 1st week of March.

Then 6 weeks to be decided according t the MB design advancement

PSB beam control mezzanine boardsTime-table



MDDS details (Option 1)


This version provides 2 DDS fully autonomous channels, meaning a maximum potential for future applications. To be realized only if it means no special difficulty.

Else go to option 2


MDDS details (Option 2)


This simpler version fulfills all needs in LEIR and PSB


MDDS clock signals


Note that I took John’s idea to use a 50% duty cycle tag signal instead of the pulses proposed in earlier presentations.This choice has practical advantages in case of AC coupling, level translation, use of fiber links…


Some remarks concerning the MDDS design


Clock signals: the electrical standard is differential LVPECL. For comparison, LVDS has a 2-times lower voltage swing - 0.4 V instead of 0.8 V - and a slower rise time – 260 ps instead of 170 ps). A higher dV/dT is favorable for clock jitter but this high speed switching induces more coupled signals on analogue chains. The overall effect still seems to be in favor of LVPECL (cf. John and Julien who made a whole set of measurements).

Thermal aspects: at a first glance, the silicon temperature would mainly be a worry for the DDS chip itself, in case version 1 of the FMC board is chosen with the two DDS chips being along the same cooling air flow. Even in this context the temperature can be estimated with enough precision.A non-refrigerated closed rf shielding increases by a great amount this thermal problem that should be evaluated at the design stage.A worrying noise source (see next slide) would be external. A good VME front and back panel shielding is likely to be good starting point in case of a problem, without thermal issues associated with a local shielding.


Some remarks concerning the ADC design


Crosstalk: crosstalk between 50 Ohm traces (analog and digital) can be simulated with tools like Microwave Studio.

Any residual sampling clock signal on the analogue lines is not likely to present any effect as the sampling process naturally filters out the corresponding harmonics.

Effects between clock lines are likely to be null as the clock is unique, although split in 4 channels, but travelling the along the same direction (See also John’s results about his VME back plane tests).

A parasitic clock edge (and reaching the threshold level) caused by a crosstalk from ADC digital data to clock would mean a very poor ground layout.

An interference likely to affect the signal integrity would come from a digital converted signal to analogue input coupling or from external sources. The good news is that all evaluation boards allow for full spec results, meaning it can be achieved without sophisticated means. (for external noise see previous slide)


Some remarks concerning the MB design


RF Clock input: On the MB front panel there is only one clock input (not two) receiving the clock from the “clock distribution Unit” or “Clock fanout”. This clock is distributed to the FMC mezzanines (except DDS).

Nevertheless there are - at most - 4 clock signals routed from the DDC mezzanine to the MB.

The 2 main clock signals (non divided clocks) created by the DDS mezzanine are routed to the MB FPGA in order to create the revolution signal. These two clock signals could use data tracks as long as they can handle 250 MHz.

The 2 divided clocks from the DDS are also received on the MB in order to create the tag and double tag with the proper length. This two clocks being below 125 MHz can easily be kept on a data track.

Note that with the DDS version using two independent sets of DDS , one can create 2 different “revolution” and tag signals. This is of no use yet, and is only kept like this in order not to limit the potentiality of the 2 channel DDS version. In all cases the MB will remain with a single rf clock.


Some remarks concerning the MB design


MDDS low-pass filter: the 250 MHz value that appears on the block diagram comes from a classical division by 4 of the sampling frequency. With a typically available filter with a 52 dB per octave attenuation, this means a filtering of the aliases down to -84 dB(14 bit equivalent S/N)

It would be interesting to increase this 250 MHz value in order to increase the dynamic range of the system. This requires a little simulation to evaluate the effect of the aliases on the final jitter. But this study should not take design time as this extension of the dynamic range is not required for CERN synchrotrons.


RF Interlocks


• The operation may ask the rf to achieve a real time “interlock” process1. Asynchronous rf interlock for all rings (real time interlock from BIS)2. Synchronous Ring specific interlock due to external conditions3. Asynchronous Real time ring specific interlock (due to measurements along the

ramp)

• The operation needs to be informed of any malfunctioning of the rf system in order to create an interlockInformation for each of the rings

Questions:

What process needs to be achieved in order to respond to a beam interlock?

What information can be used to determine a Beam Control malfunction?


RF Interlock Inputs


There are 3 different types of interlocks inputs

As we want to have the freedom to envisage different responses to these interlocks, it is a good approach to have 3 different inputs.

1 input from BIS will consist of 2 rf TTL signals (leading to beam permit A and B) that need to be daisy chained to all the 4 beam controls.

The 2 other inputs should be sensitive to a signal level (+V = not OK with a pull up on the rf side)The timing input is not a safe for an interlock input


RF Interlock input


From B. Puccio

RFInput

All rings


RF Interlock Outputs


2 cases will be taken into account for the interlock output:

1) The RF is in such a bad shape that it cannot output any interlock

2) The RF Beam Control works fine, but some external conditions are not met

For case 1) assuming the BC outputs a “rf OK” value when it is in fault, one suggestion is to create an external interlock box (it can for instance measure the phase difference between injection reference and rf)

For Case 2) an interlock will be output by the Beam Control itself down to the external interlock box.

The final rf interlock will be the OR of the 2 latter interlocks.

The final interlock from the external box, will also present different outputs. One for each ring and a 5th corresponding to all 4 rings being Out of Order.


RF Interlock Output


From B. Puccio

RFOutput

Each ring


RF Interlock


FromRF


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PSB beam control mezzanine boards Time-table