Providing Infrastructure for Optical Communication Networks

Prof. Michael GreenDept. of EECSHenry Samueli School of Engineeringmgreen@uci.edu

EECS 294 Colloquium4 October 2006

This presentation can be found at:http://www.eng.uci.edu/faculty/green/public/courses/294

Friday, March 7 2003

Advantages of Optical Fibers over Copper Cable

• Very high bandwidth (bandwidth of optical transmission network determined primarily by electronics)• Low loss• Interference Immunity (no antenna-like behavior)• Lower maintenance costs (no corrosion, squirrels don’t like the taste)• Small & light: 1000 feet of copper weighs approx. 300 lb.

1000 feet of fiber weighs approx. 10 lb.• Different light wavelengths can be multiplexed onto a single fiber: Dense Wavelength Division Multiplexing (DWM)• 10Gb/s transmission networks now being deployed; 40Gb/s will be here soon.

Protocols for High-Speed Optical Networks

Synchronous Optical Network (SONET):• Provides a protocol for long-haul (50-100km) wide-area netework (WAN) fiber transmission• Basic OC-1 rate is 51.84Mb/s OC-48 (2.5Gb/s) & OC-192 (10Gb/s) are commonGigabit/10 Gigabit Ethernet (IEEE Standard 802.3):• Ethernet was invented in 1973 at Xerox PARC

(“ether” is the name of the medium through which E/M waves were thought to travel)

• Provides a protocol for local-area network (LAN) copper or fiber transmission

• 1 Gb/s links can be transmitted over twisted-pair copper• 10 Gb/s links can be transmitter over copper (short lengths) or fiber.

Fiber Channel:• Often used for Storage Area Networks (SAN); allows fast transmission of large amounts of data across many different servers.• Currently 1-4 Gb/s is deployed; 8Gb/s will arrive soon.

Some SAN Terminology

JBOD: Just a Bunch Of DisksRefers to a set of hard disks that are

not configured together.

RAID: Redundant Array of Independent (or Inexpensive?) Disks

Multiple disk drives that are combined for fault tolerance

and performance. Looks like a single disk to the rest of

the system. If one disk fails, the systems will continue

working properly.

Blade Servers vs. Regular Servers

See: http://www.spectrum.ieee.org/WEBONLY/publicfeature/apr05/1106for full article.

Barcelona, Spain:MareNostrum supercomputer cluster (2282 Blade servers)

Housed in Chapel Torre Girona (Technical Univ. of Catalonia)

Characteristics of Broadband Signals & Circuits

• Standard analog circuit applications: Continuous-time operation Precision required in signal domain (i.e., voltage or current) Dynamic range determined by noise & distortion

• Broadband communication circuits: Discrete-time (clocked) operation Precision required in time domain (low jitter) Bilevel signals processed

t

V

t0

V

t

V

t

Vh

Vt

Vl

Primarily digital (i.e., bilevel) operation but high bit rate (multi-Gb/s) dictates analog behavior & design techniques.

Typical broadband data waveform:

Length of single bit = 1 Unit Interval (1 UI)

Eye diagram

An eye diagram maps a random bit sequence to a regular structure that can be used to analyze jitter.

Close-up of eye diagram:

voltage swing

1 UI

Zero crossings

trise = tfall

What is Jitter?

Jitter is the short-term variation of the significant instants of a digital signal from their ideal positions in time.Jitter normally characterizes variations above 10Hz; variations below 10Hz are called wander.

1. Phase noise (frequency domain)2. Jitter (time domain)3. Bit Error-Rate (end result of phase

noise & jitter)

The effects of these variations are measured in 3 ways:

Types of Jitter

1. Random Jitter (RJ)• Originates from external and

internal random noise sources• Stochastic in nature (probability-

based)• Measured in rms units• Observed as Gaussian histogram

around zero-crossing• Grows without bound over time

Histogram measurement at zero crossing exhibiting Gaussian probability distribution

Types of Jitter (cont.)

2. Deterministic Jitter (DJ)• Originates from circuit non-idealities (e.g., finite bandwidth, offset, etc.)• Amount of DJ at any given transition is predictable• Measured in peak-to-peak units• Bounded and observed in various eye diagram “signatures”

• Different types of DJ:a) Intersymbol interference (ISI)b) Duty-cycle distortion (DCD)c) Periodic jitter (PJ)

Consider a 1UI output pulse from a buffer:

If rise/fall time << 1 UI, then the output pulse is attenuated and the pulse width decreases.

a) Intersymbol interference (ISI)

€

τ <<UI

€

τ ≈UI

€

τ >UI

1UI

< 1UI

0 0 1

1 0 1

ISI (cont.)

Consider 2 different bit sequences:

t = ISISteady-state not reachedat end of 2nd bit

2 output sequencessuperimposed

ISI is characterized by a double edge in the eye diagram. It is measured in units of ps peak-to-peak.

Double-edge

Effect of ISI on eye diagram:

Occurs when rising and falling edges exhibit different delaysCaused by circuit mismatches

Nominal data sequence

Data sequence with early falling edges& late rising edges

t = DCD

Eye diagram with DCD

b) Duty cycle distortion (DCD)

Crossing offset fromnominal threshold

c) Periodic Jitter (PJ)

Timing variation caused by periodic sources unrelated to the data pattern.Can be correlated or uncorrelated with data rate.

Clock source withduty cycle

€

≠50%

Synchronized dataexhibiting correlated PJ

t1 t0

€

PJ =t1 − Δt0

Uncorrelated jitter (e.g., sub-rate PJ due to supply ripple) affects the eye diagram in a similar way as RJ.

R

€

2σ

€

2σ

0 T

€

T

2

€

t0

€

T − t0

€

PL =1

σ 2π⋅ exp −

x 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

t0

∞

∫ dx

€

PR =1

σ 2π⋅ exp −

T − x( )2

2σ 2

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥t0

∞

∫ dx

€

pL (t) =1

σ 2π⋅exp −

t 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

€

pR (t) =1

σ 2π⋅exp −

T − t( )2

2σ 2

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥

Probability of sample at t > t0 from left-hand transition:Probability of sample at t < t0 from right-hand transition:

Jitter and Bit Error Rate

Total Bit Error Rate (BER) given by:

€

BER = PL + PU =1

σ 2π⋅ exp −

x 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

t0

∞

∫ dx +1

σ 2π⋅ exp −

x 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

T −t0

∞

∫ dx

€

=1

2erfc

t0

2σ

⎛

⎝ ⎜

⎞

⎠ ⎟+ erfc

T − t0

2σ

⎛

⎝ ⎜

⎞

⎠ ⎟

⎡

⎣ ⎢

⎤

⎦ ⎥

€

where erfc(t) ≡2

π⋅ exp

t

∞

∫ −x 2( )dx

€

PL =1

σ 2π⋅ exp −

x 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

t0

∞

∫ dx

€

PR =1

σ 2π⋅ exp −

T − x( )2

2σ 2

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥t0

∞

∫ dx =1

σ 2π⋅ exp −

x 2

2σ 2

⎡

⎣ ⎢

⎤

⎦ ⎥

T −t0

∞

∫

€

•

€

•

€

•

€

•

t0 (ps)

log BER

€

σ =5ps

€

σ =2.5ps

€

σ =2.5ps :

€

BER ≤10−12 for t0 ∈ 18ps, 82ps[ ]

€

σ =5ps :

€

BER ≤10−12 for t0 ∈ 36ps, 74ps[ ]

Example: T = 100ps

(64ps eye opening)

(38ps eye opening)

log(0.5)

Bathtub CurvesThe bit error-rate vs. sampling time can be measured directly using a bit error-rate tester (BERT) at various sampling points.

Note: The inherent jitter of the analyzer trigger should be considered.

€

JrmsRJ

( )measured

2= Jrms

RJ( )

actual

2+ Jrms

RJ( )

trigger

2

Benefits of Using Bathtub Curve Measurements

1. Curves can easily be numerically extrapolated to very low BERs (corresponding to random jitter), allowing much lower measurement times.

Example: 10-12 BER with T = 100ps is equivalent to an average of 1 error per 100s. To verify this over a sample of 100 errors would require almost 3 hours!

€

•

€

•

€

•

€

•

t0 (ps)

2. Deterministic jitter and random jitter can be distinguished and measured by observing the bathtub curve.

Advantages of Using CMOS Fabrication Process

• Compact (shared diffusion regions)

• Very low static power dissipation

• High noise margins (nearly ideal inverter voltage transfer characteristic)

• Very well modeled and characterized

• Inexpensive (?)

• Mechanically robust

• Lends itself very well to high integration levels

• SiGe BiCMOS has many advantages but is a generation behind currently available standard CMOS

CMOS gates generate and are sensitive to supply/ground bounce.

Series R & L cause supply/ground bounce.Resulting modulation of transistor Vt’s results in jitter.

data in clock in

Rs = 0Ls = 0

clock out

clock out

Rs = 5Ls = 5nH

clock out

data out

DDV ′

SSV ′

DDV ′

SSV ′

data out

Rs = 5 Ls = 5nH

Inverter based on differential pair:

• Differential operation• Inherent common-mode rejection• Very robust in the presence of common-mode disturbances (e.g., VDD/VSS bounce)

“Current-mode logic (CML)”

data in clock in

Rs = 0Ls = 0

clock out

clock out

Rs = 5Ls = 5nH

clock out

data out

DDV ′

SSV ′

DDV ′

SSV ′

data out

Rs = 5 Ls = 5nH

Research Topics

BiCMOS 10Gb/s Adaptive Equalizer

A Novel CDR with Adjustable Phase Detector Characteristics

A Distributed Approach to Broadband Circuit Design

Research Topics

BiCMOS 10Gb/s Adaptive EqualizerEvelina Zhang, Graduate Student

Researcher

A Novel CDR with Adjustable Phase Detector Characteristics

A Distributed Approach to Broadband Circuit Design

Cable Model

Copper Cable

Where: L is the cable length a is a cable-dependent

characteristic

shorter cable

longer cable

longer cable

shorter cable

1G 10Gf

+10

0

-10-20

-30

magnitude (dB)

100M

1G 10G

f

100M

0

-100

-200

-300

phase (deg)

€

F (s) =e−aL s

Motivation

Reduce ISI Improve receiver sensitivity

40 41 42 43

t (ns)

40 41 42 43

t (ns)

0.5

0

-0.5

input waveform (V)

39

0.3

0

-0.339

output waveform (V)

100 200 300

t (ps)

0

100 200 300

t (ps)

0

0.5

0

-0.5

0.3

0

-0.3

input eye

output eye

Adaptive Equalizer

Implemented in Jazz Semiconductor SiGe process:• 120GHz fT npn • 0.35 CMOS

Equalizer Block Diagram

Feedforward Path

f (Hz)

€

Veq

Vin

(dB)

Vcontrol

FFE Frequency Response

teq = 75psPW = 86ps

teq = 60psPW = 100ps

2.4 2.5 2.6 2.7 2.8

t (ns)

-0.3

0

0.3

VFFE

ISI & Transition Time

• Simulations indicate that ISI correlates strongly with FFE transition time teq.

• Optimum teq is observed to be 60ps.

teq = 45psPW = 108ps

Slicer

Feedback Path

∫

Transition Time Detector

DC characteristic:

−+ −VV

SV

Transient Characteristic:

t

−+ −VV

SV

• Rectification & filtering done in a single stage.

(a)

(b)

(a)

(b)

Integrator

( )2110 oom rrgA ||=

1m

Lint g

C=τ

intint sAs

AsH

ττ1

1 0

0 ≈+

=)(

Detector + Integrator

∫

slopedetector

slopedetector

FromSlicer

tslicer=60ps

FromFFEtFFE

Vcontrol

+ _0 10 20 30 40 50

60

40

0

-40

20

-20

-60

t (ns)

Vcontrol (mV)

60ps

45ps

15ps

75ps

90ps

FFE transitionTime tFFE

€

∑+

_Kd

Kd

Keq

tslicer teqdetector

detector

feedforwardequalizer

integrator

H(s)

Vcontrol

)(

)(

sHKK

sHKK

t

t

eqd

eqd

slicer

eq

+=1

eqd

slicer

eq

KKst

t

intτ+=1

1

intssH

τ1

≈)(

Keq = 1.5 ps/mV

Kd = 2.5 mV/ps

τint = 75ns

€

τadapt=τint

KdKeq

=20ns

System Analysis

Measurement Setup

Die under test

231 PRBS signalapplied to cable

EQ inputs

EQ outputs

Eye Diagrams

4-footRU256 cable

15-footRU256 cable

EQ input EQ output

4.0ps rms jitter

3.9ps rms jitter

Supply voltage 3.3V

Power Dissipation 350mW(155mW not including output driver)

Die Size 0.81mm X 0.87mm

Output Swing 490mV single-ended p-p

Random Jitter 4.0ps rms (4-foot cable)3.9ps rms (15-foot cable)

Summary of Measured Performance

Ongoing Research Investigate transition detector more thoroughly

Understand trade-off between ISI reduction and random jitter generation

Investigate compensation of PMD in optical fiber

Random noise in Analog Equalizer

input eye(no noise added)

output eyeISI: 6.2ps p-p

input eye with added noise output eyeISI+random jitter: 23ps p-p

ISI is reduced but random jitter is increased due toamplification of random noise.

Decision Feedback Equalization (DFE)

Summing circuit:

Variable delay circuit:

output eyeno noise addedISI: 6.7ps p-p

output eyerandom noise added

ISI+random jitter: 7.4ps p-p

DFE Simulations (copper)

DFE Simulations (fiber)

input waveformexhibiting PMD

input eye output eyeISI: 7.9ps p-p

Research Topics

BiCMOS 10Gb/s Adaptive Equalizer

A Novel CDR with Adjustable Phase Detector Characteristics

Xinyu Chen, Graduate Student Researcher

A Distributed Approach to Broadband Circuit Design

Clock/Data Recovery Circuits

Binaryoperation

Linearoperation

• Ability to handle high bit rates• Low jitter generation• High jitter tolerance• Fast acquisition

CDR Requirements:

2-Loop CDR Architecture

Is it possible for a CDR to exhibit linear (quiet) behavior and fast acquisition with a single loop?

Deadband PD characteristic

“Ternary” latch:

CML version:

externalcontrol

Comparisons

Conventional Binary PD Hogge PD

Ternary PD;VG = 1.75V

Ternary PD;VG = 1.65V

Simulation Results

Varying VG During Acquisition

Future Work Using the variable PD characteristic as part of a lock detection circuit.

Minimizing jitter in a similar way.

Research Topics

BiCMOS 10Gb/s Adaptive Equalizer

A Novel CDR with Adjustable Phase Detector Characteristics

A Distributed Approach to Broadband Circuit Design

Ullas Singh, Graduate Student Researcher

Distributed Amplifier

• Signals travel ballistically through amplifier.• Higher gain-bandwidth product.• Naturally drives resistive load.• Trades off delay for bandwidth.

T

mmmdist C

Ng

c

g

lcc

lgGBW ==⎟⎟

⎠

⎞⎜⎜⎝

⎛⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=

22 T

mconv C

gGBW =

Distributed Frequency Divider

Distributed divider schematic

Lumped frequency divider schematic

– Buffer delay of lumped elements can be replaced by passive element delay in distributed divider

All simulations used 0.18 CMOS

Distributed Frequency Divider Simulations

Input/Output waveformDivider sensitivity curve

Frequency Divider Layout

Area=800m*807m

Distributed 2-to-1 Select Circuit

Proposed distributed select circuit

Lumped select circuit Timing diagram

PRBSgenerator

4:2MUX

2:1MUX

10Gb/s20Gb/s 40Gb/s

lumped circuitry distributed circuitry(180nm CMOS)

40Gb/s MUX Block Diagram

Simulated 40Gb/s Eye Diagram

ISI: 2ps (80mUI) p-p

0.6

0.4

0.2

0

-0.2

-0.4

-0.60 10 20 30 40 50 60 70 80

t (ps)

Vout (V)

Test Setup

die bondeddirectly to board

Measured Results

Measurements taken with Agilent 86-100C DCA-J with

80GHz plug-in module

Bit-rate: 34Gb/s (due to varactor variations)

Future Research Analyze nonlinear large-signal effects & derive a clear design methodology.

Investigate possible methods of electrically (or optically?) controlling characteristic impedances of tranmission lines.