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SPARK. U C I R V I N E. CECS. U C I R V I N E. Spark: A Parallelizing Compiler Framework for High-Level System Synthesis Sumit Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, A. Nicolau Center for Embedded Computer Systems, University of California, Irvine. - PowerPoint PPT Presentation
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•Prototyping of code transformations related to speculation and early condition execution completed•Accepts C input and outputs synthesizable RTL VHDL•Implemented synthesis tasks: scheduling, controller generation•Currently implementing operation and variable binding•Benchmarked on large real-life applications: MPEG, ADPCM
Spark: A Parallelizing Compiler Framework for High-Level System SynthesisSpark: A Parallelizing Compiler Framework for High-Level System Synthesis Sumit Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, A. Nicolau
Center for Embedded Computer Systems, University of California, Irvine
Spark’s Synthesis Design FlowSpark’s Synthesis Design Flow
http://www.cecs.uci.edu/~sparkCECSCECS
U C I R V I N E
Synthesis: from Behavior to CDFG to ArchitectureSynthesis: from Behavior to CDFG to Architecture
Scheduling under Resource ConstraintsScheduling under Resource Constraints
Generalized CodeMotions
Generalized CodeMotions
Extracting Parallelism using SpeculationExtracting Parallelism using Speculation
• Studying effects of code motion on controller complexity and clock cycle length•Use resource binding and other techniques to reduce interconnection and controller complexity•Develop Loop Pipelining heuristics to improve throughput•Implement into a user-driven toolbox of transformations
Long Term GoalsStatus and Implementation
SPARKSPARKU C I R V I N E
Effects of Code Motions on Various MetricsEffects of Code Motions on Various Metrics
Supported by Semiconductor Research Corporation
Supported by Semiconductor Research Corporation
•Evaluate conditions ASAP• Moves low priority ops into conditionals• Only moves to branches which require result
•Achieve significant reductions in longest path lengths and total delay•Minimal increase in clock cycle length•Area increase can be reduced by efficient binding
•Hierarchical code motions•Ops are moved across entire conditionals•Significantly reduce schedule length
•Currently being implemented•Enables across loop iteration compaction•Can lead to significant throughput gains
Resource Directed Loop Pipelining
Resource Directed Loop Pipelining
Operation and Variable BindingOperation and Variable Binding
0.8
1
1.2
1.4
1.6
1.8
2
Within BBs WithSpeculation
Early CondExecution
Type of Code Motion
Norm
ali
zed V
alu
e
Path Len Clock Cycle Delay Area
Reverse Speculationand Early Condition
Execution
Reverse Speculationand Early Condition
Execution
calc_forw_motion fcn from MPEG Prediction Block (61 Ops, 36 BBs)