–Properties –Examples

Andrew H. Fagg: EmbeddedReal-Time Systems: Digital Logic

1

Last Time

• Introduction to embedded systems– Properties

– Examples

• Class structure


2

Administrivia

Lab hours proposal

• Monday/Wednesday: 1-5

• Tuesday/Thursday: 10:30-12:30 and 1:30-4:30

Lab location: EL 124

• If you do not find the lab open, find one ofus (in 141 or 152)


3

AdministriviaOffice hours (until lab opens):

• Andrew Fagg (EL 152):– Monday: 1-2

– Wednesday: 4-5

– Or by appointment

• Mark Woehrer (EL 141):– Tuesday: 10:30-11:30

– Wednesday: 3:30-4:30

– Or by appointment


4

Schedule Notes

• Our class schedule is fluid– Changes will be announced in class and on

the Blackboard


5

Today: Introduction to Digital Logic

• Binary encoding

• Boolean algebra

• Transistors to logic gates


6

Encoding Information

In your ‘circuits and sensors’ class: how didyou encode information?

• e.g., the acceleration measured by youraccelerometer?

• or the rate of bend of a piezoelectricdevice?


7


Following some form of (implementationdependent) analog conditioning:

• Acceleration (or bend rate) is encoded inthe voltage that is output from the circuit

• As acceleration increases, the voltagealso increases


8


Following some form of (implementationdependent) analog conditioning:

• Acceleration (or bend rate) is encoded inthe voltage that is output from the circuit

• As acceleration increases, the voltagealso increases

• We say that this is an analog orcontinuous encoding of the information


9

Analog Encoding

What is the problem with analog encoding?


10

Analog Encoding

What is the problem with analog encoding?

• Small injections of noise – either in thesensor itself or from external sources – willaffect this analog signal

• This leads to errors in how we interpret thesensory data

How do we fix this?


11

Digital Encoding

How do we fix this?

• At any instant, a single signal encodesone of two values:– A voltage around 0 (zero) Volts is interpreted

as one value

– A voltage around +5 V is interpreted asanother value


12

Binary Encoding

• Binary digits can have one of two values:0 or 1

• We call 0V a binary “0” (or FALSE)

• And +5V a binary “1” (or TRUE)


13

Binary Encoding

• Exactly what these levels are depends onthe technology that is used (it is commonnow to see +1.8V as a binary 1 in low-power processors)

• This encoding is much less sensitive tonoise: small changes in voltage do notaffect how we interpret the signal


14

Transistors

What do transistors do for us?


15

Transistors

What do transistors do for us?

• They act as current amplifiers

• But if we operate below the threshold andabove the saturation level, we can usethem to process digital signals


16

Transistors to Digital Processing

Consider the following circuit:

• What is the output given an input of 0V?

• An input of +5V?


17

Transistors to Digital Processing

• Input: 0V -> Output +5V

• Input: +5V -> Output 0V

• We call this a “NOT” gate


18

The NOT Gate

• Logical Symbol:

• Algebraic Notation: B = A

• Truth Table:

01

10

BA


19

A Two-Input Gate

What does thiscircuit compute?

- A and B are inputs

- C is the output


20

The “NAND” Gate

011

101

110

100

CBA

• Logical Symbol:

• Algebraic Notation: C = A*B = AB

• Truth Table:


21

The “AND” Gate

111

001

010

000

CBA

• Logical Symbol:

• Algebraic Notation: C = A*B = AB

• Truth Table:


22

Yet Another Gate

What doesthis circuitcompute?


23

The “NOR” Gate

• Logical Symbol:

• Algebraic Notation: C = A+B

• Truth Table:

011

001

010

100

CBA


24

The “OR” Gate

• Logical Symbol:


• Truth Table:

111

101

110

000

CBA


25

N-Input Gates

Gates can have anarbitrary number ofinputs (2,3,4,8,16 arecommon)


26

Exclusive OR (“XOR”) Gates

• Logical Symbol:


• Truth Table:

011

101

110

000

CBA How would weimplement thiswithAND/OR/NOTgates?


27

An XOR Implementation


28

An Example

Problem: implement an alarm system• There are 3 inputs:

– Door open (1 represents open)– Window open– Alarm active (1 represents active)

• And one output:– Siren is on (1 represents on) when either the door or

window are open – but only if the alarm is active

What is the truth table?


29

Alarm Example: Truth Table

1111

0011

1101

0001

1110

0010

0100

0000

SirenAWD

+

+

D W A

D W A

D W A


30

Alarm Example: Circuit

Siren = D W A + D W A + D W A


31

Alarm Example: Circuit

Is a simpler circuit possible?


32


1111

0011

1101

0001

1110

0010

0100

0000

SirenAWD


33

Alarm: An Alternative Circuit


34

Next Time

• Some notes on Boolean Algebra

• DeMorgan’s Laws

• Multiplexers

• Demultiplexers

• Circuit reduction with Karnaugh Maps


35

Last Time

• Transistors to digital logic

• Basic gates: AND, OR, NOT

• Other gates: XOR, NOR, NAND


36

Today

Circuit reduction tools:

• Boolean Algebra

• DeMorgan’s Laws

• Karnaugh Maps


37

Administrivia

• Project 1 is delayed until next week

• You should have received the test email tothe class mailing list: if not we need to fix itASAP


38

Administrivia

Lab hours

• Monday/Wednesday: 9-11 and 2-5

• Tuesday/Thursday: 10:30-12:30 and 1:30-4:30

Until lab is handed out next week:

• Fagg: Monday: 10-11, Wednesday: 4-5

• Woehrer: Tuesday: 10:30-11:30, Thursday:3:30-4:30


39

Boolean Algebra

• There are exactly two numbers in BooleanSystem: “0” and “1”

• You are already familiar with the “integers”:{… -2, -1, 0, 1, 2, …}– (and Integer Algebra)


40

Boolean Algebra

• Like the integers, Boolean Algebra has thefollowing operators:

NOTnegationinverse

ANDproduct*

ORaddition+

BooleanIntegers


41

NOT Operator

Definition:

• 0 = 0’ = 1

• 1 = 1’ = 0

Suppose that “X” is a Boolean variable,then:

• X = X’’ = X

NOTE: this is identical to our truthtable (just a slightly differentnotation)


42

OR (+) Operator

Definition:

• 0+0 = 0

• 0+1 = 1

• 1+0 = 1

• 1+1 = 1


43

OR (+) Operator

Suppose “X” is a Boolean variable, then:

• 0 + X = X

• 1 + X = 1

• X + X = X

• X + X’ = 1


44

AND (*) Operator

Definition:

• 0*0 = 0

• 0*1 = 0

• 1*0 = 0

• 1*1 = 1


45

AND (*) Operator

Suppose “X” is a Boolean variable, then:

• 0 * X = 0

• 1 * X = X

• X * X = X

• X * X’ = 0


46

Boolean Algebra Rules:Precedence

The AND operator applies before the ORoperator:

A * B + C = (A * B) + C

A + B * C = A + (B * C)


47

Boolean Algebra Rules:Association Law

If there are several AND operations, it doesnot matter which order they are applied in:

A * B * C = (A * B) * C = A * (B * C)


48

Boolean Algebra Rules:Association Law

Likewise for the OR operator:

A + B + C = (A + B) + C = A + (B + C)


49

Boolean Algebra Rules:Distributive Law

AND distributes across OR:

A * (B + C) = (A * B) + (A * C)

A + (B * C) = (A + B) * (A + C)


50

Boolean Algebra Rules:Commutative Law

Both AND and OR are symmetric operators(the order of the variables does notmatter):

A + B = B + A

A * B = B * A


51

DeMorgan’s Laws

(A * B)’ = A’ + B’

How do we convince ourselves that this istrue?


52

Proof by Truth Table

0011

1101

1110

1100

A’ + B’(A * B)’BA

NOTE:change inthe NOTnotation


53

DeMorgan’s Laws (cont)

(A + B)’ = A’ * B’


54

Proof by Truth Table

0011

0001

0010

1100

A’ * B’(A + B)’BA


55


1111

0011

1101

0001

1110

0010

0100

0000

SirenAWD

+

+

D’ W A

D W’ A

D W A


56

Reduction with Algebra

X + X’ = 1= 1* W A + 1* DA

AssociativeLaw

= (D’ + D) WA + (W’ + W) DA

“= D’ WA + DWA + W’DA + WDA

Commutative

Law

= D’ WA + DWA + DW’A + DWA

X + X = X= D’ W A + D W’ A + DWA + DWA

D’ W A + D W’ A + DWA


57

Reduction with Algebra (cont)

AssociativeLaw

= (W + D) * A

X * 1 = X= WA + DA

1* W A + 1* DA

We have the same circuit as before!


58

Karnaugh Maps

Geometric technique for reducing circuits

• Step 1: Construct the map

• Step 2: Fill in the output

• Step 3: Identify “clusters” in the map

• Step 4: Read out the terms


59

Suppose We Have the FollowingTruth Table:

1111

1011

0101

0001

1110

1010

1100

0000

DCBA

3 Inputs

1 Output


60

Karnaugh MapsStep 1: Construct Map

1

0

10110100ABC


61


1

0

10110100ABC

C

B A


62


1

0

10110100ABC

C

B A

A*B*C


63


1

0

10110100ABC

C

B A

A’ B C’


64

Karnaugh MapsStep 2: Insert Output Values

1111

1011

0101

0001

1110

1010

1100

0000

DCBA

Enter outputvalues intomap


65

Karnaugh Maps Step 2: Insert Output Values

01111

01100

10110100ABC

C

B A


66

Karnaugh MapsStep 3: Identify Clusters of 1’s

01111

01100

10110100ABC

C

B A

A’ B C


67


01111

01100

10110100ABC

C

B A

A’ B


68


01111

01100

10110100ABC

C

B A

C B


69


01111

01100

10110100ABC

C

B A

B


70


Clustering Rules:

• A cluster may not contain a ‘0’

• All ‘1’s must be covered

• But: it is OK for a ‘1’ to be covered bymore than one cluster


71


01111

01100

10110100ABC

C

B A

B A’ C


72

Karnaugh MapsStep 4: Read Out the Terms

“OR” the clusters together

Resulting logical rule:

B + A’C


73

The Alarm Example (again)

1111

0011

1101

0001

1110

0010

0100

0000

SirenAWD

+

+

D’ W A

D W’ A

D W A


74

Karnaugh Maps Step 1: Construct Map

1

0

10110100DWA

A

W D


75

Karnaugh Maps Step 2: Insert Output Values

11101

00000

10110100DWA

A

W D


76

Karnaugh Maps

Step 3: Identify Clusters of 1’s

11101

00000

10110100DWA

A

W D

W A D A


77



WA + DA


78



WA + DA

Which can be simplified to:

A * (W + D)


79

Next Time

• More on Karnaugh Maps

• Multiplexers

• Demultiplexers


80

A New K-Map Example

• Four input variables: A, B, C, D

• One output variable: E


81

Truth Table

1

1

1

1

1

1

1

1

A

0111

0011

0101

1001

1110

0010

1100

0000

EDCB

0

0

0

0

0

0

0

0

A

1111

1011

0101

0001

1110

1010

1100

0000

EDCB


82

Step 1: Construct Map

10

11

01

00

10110100ABCD

C

B A

D


83

Step 2: Insert Output Values

001110

101111

100101

010000

10110100ABCD

C

B A

D


84

Step 3: Identify Clusters

001110

101111

100101

010000

10110100ABCD

C

B A

D

C A’


85


001110

101111

100101

010000

10110100ABCD

C

B A

D

?


86


001110

101111

100101

010000

10110100ABCD

C

B A

D

B’ D


87


001110

101111

100101

010000

10110100ABCD

C

B A

D

ABD’C’


88

Step 4: Read Out the Terms

C A’ + B’ D + A B D’ C’

What does the circuit look like?


89

Resulting CircuitC A’ + B’ D + A B D’ C’


90

“Don’t Care” Cases

• For some functions that we will implement,some of the input cases will never occur

• How does this affect our Karnaugh Map?


91

Modified Truth Table

1

1

1

1

1

1

1

1

A

0111

0011

X101

1001

1110

X010

1100

0000

EDCB

0

0

0

0

0

0

0

0

A

1111

1011

0101

0001

1110

1010

1100

0000

EDCB


92

Step 2: Insert Output Values

X01110

101111

1X0101

010000

10110100ABCD

C

B A

D


93


X01110

101111

1X0101

010000

10110100ABCD

C

B A

D

ABD’C’


94


X01110

101111

1X0101

010000

10110100ABCD

C

B A

D

ABC’


95

Last Time

• Boolean Algebra

• Karnaugh Maps


96

Today

• More on Karnaugh Maps

• Multiplexers

• Demultiplexers

• Tristate buffers


97

Administrivia

Current office hours:

• Fagg: Monday: 10-11, Wednesday: 4-5

• Woehrer: Tuesday: 10:30-11:30, Thursday:3:30-4:30


98


X01110

101111

1X0101

010000

10110100ABCD

C

B A

D

ABC’


99

Step 4: Read Out the Terms

C A’ + B’ D + A B C’

The resulting circuit is simpler (but just alittle in this case)


100

A Diagonal Example

01011

10100

10110100ABC

C

B A


101

Working Through the Algebra…

“=A B C

XORDefinition

=(A B)’C + (A B)C’

DeMorgan=(A’B + AB’)’C + (A B)C’

Commutative

Law; XOR

=(A’B’ + AB)C + (A B)C’

AssociativeLaw

=(A’B’ + AB)C + (A’B + AB’)C’

A’B’C + ABC + A’BC’ + AB’C’

+

+

+ +

+ +


102

Diagonal Example II

01101

10100

10110100ABC

C

B A


103

Diagonal Example IIBA’ + CB + AB’C’

Can we get away with fewerterms?


104

Diagonal Example II

01101

10100

10110100ABC

C

B A


105

Diagonal Example IICB + C’(A XOR B)

We can also arrive at this through algebraicmanipulation of our previous solution.How?


106

Diagonal Example II

X + 1 = 1= CB + C’ (B XOR A)

Distributive Law= CB(A’ + 1) + C’(B XOR A)

XOR Definition= BA’C + CB + C’(B XOR A)

“= BA’C + CB + C’(BA’ + AB’)

Distributive Law= BA’C + BA’C’ + CB + AB’C’

X + X’ = 1= BA’(C + C’) + CB + AB’C’

BA’ + CB + AB’C’


107

Multiple Output Variables

Suppose we have a function with multipleoutput variables?

• How do we handle this with KarnaughMaps?


108

Multiple Output Variables

How do we handle this with KarnaughMaps?

• We produce one Karnaugh Map for eachoutput variable

• But: in the final implementation, some sub-circuits may be shared


109

Karnaugh Maps: Final Notes

• Always use clusters that are as large aspossible

• Possible to extend technique to 5 and 6inputs (and more), but it starts to get hairy– Tend to make use of circuit design

“assistants”


110

More Logical Components

• Multiplexer

• Demultiplexer

• Tristate buffer


111

Multiplexer

A multiplexer is a devicethat selects between twoinput lines

• A & B are the inputs

• S is the selection signal(also an input)

• C is a copy of A if S=0

• C is a copy of B if S=1


112

Multiplexer Truth Table

What would theKarnaugh map looklike?

1111

0011

1101

0001

1110

1010

0100

0000

CBAS


113

Multiplexer K-Map

01101

11000

10110100ABS

S

B A


114

Multiplexer Implementation

C = S’A + SB


115

N-Input Multiplexer

Suppose we want toselect from betweenN different inputs.

• This requires morethan one select line.How many?


116

N-Input Multiplexer

How many select lines?

• M = log2N

or

• N = 2M

What would the N=8implementation looklike?


117

8-Input Multiplexer Implementation

C = I0S’2S’1S’0 + I1S’2S’1S0 + I2S’2S1S’0 +I3S’2S1S0 + I4S2S’1S’0 + I5S2S’1S0 +I6S2S1S’0 + I7S2S1S0

Note that we have one of eachpossible select line combination(or addressing terms)


118

Last Time

• Karnaugh Maps

• Multiplexers


119

Today

• Demultiplexers

• Tristate buffers

• Practical issues in digital logicimplementation

• Project 1


120

Administrivia

Make sure you fill out and hand-in groupplacement forms today


121

What Is It?


122

A Mechanical Implementationof an OR Gate

goldfish.ikaruga.co.uk/logic.html


123



124



125



126

Demultiplexer

• The multiplexer reducesN signals down to 1 (withM select lines)

• A demultiplexer routes adata input (D) to one of Noutput lines (As)– Which A depends on the

select lines


127

2-Input DemultiplexerTruth TableInputs Outputs

0001111

0000011

0010101

0000001

0100110

0000010

1000100

0000000

A0A1A2A3DS0S1


128

Demultiplexer Implementation

• What does it look like?


129

DemultiplexerImplementation


130

M-Input (Select) Demultiplexer

• Will have 2M output lines

• Useful for converting a binary address intoselect lines for devices and memoryelements– (more on binary soon)


131

Tristate Buffers

• Until now: the output line(s) of each deviceare driven either high or low– So the line is either a source or a sink of

current

• Tristate buffers can do this or leave theline floating (as if it were not connected toanything)


132

Tristate Buffers

111

001

floating10

floating00

BAS

How are tristatebuffers useful?


133

Tristate Buffers

We can wire the outputs ofmultiple tristate bufferstogether without any otherlogic


134

Tristate Buffers

• We must guarantee that only one selectline is active at any one time

• Tristate buffers will turn out to be usefulwhen we start building data and addressbuses


135

Another Tristate Buffer

What does the truth table look like?


136

Another Tristate Buffer

floating11

floating01

110

000

BAS


137

Next Time

• Practical issues in digital logicimplementation

• Project 1 details

Documents

–Properties –Examples