Project Final Dfcc

2011Digital Flight Control Computer

A Report on Project Work inBharat Electronics Limited

Electronic Warfare & Avionics Division

Bangalore

DEVELOPING THE OFP CODE FOR

TESTING DFCC DIGITAL CARD OF

LCA

AUTHORS

LUV VERMAStudent (4th Year)

B.Tech.(Aerospace) + M.Tech. (Avionics)Amity University, Noida

[email protected]

RAJWANT BAINSStudent (4th Year)


[email protected]

ABHA GUPTAStudent (4th Year)


[email protected]

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mailto:[email protected]



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A project report on

Developing the OFP code for testing DFCC Digital Card of LCA

Submitted for partial fulfillment of the requirements for the award of the

degree of

B.Tech. (Aerospace) + M.Tech. (Avionics) – Dual Degree

From

Amity Institute of Space Science & Technology

By

Luv Verma 1906

Rajwant Bains 1912

Abha Gupta 1934

Carried out at

Bharat Electronics Limited, Jalahalli Post, Bangalore.

UNDER THE GUIDENCE OF

Mr. Atma Dev Singh

Senior Engineer

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(Avionics Testing/FCS, EW&A)

Print the sheets of OFP test that was carried out by sir in DFCC and

attach in the project

Fig names

Add verma sir’s name in acknowledgemnt?

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5

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ACKNOWLEDGEMENTThe satisfaction and euphoria that accompany the successful completion of any

task would be incomplete without mention of individuals, who throughtheir

guidance, discussion or by providing facilities for our work, have served as a

beacon light and crowned our efforts with success.

We are extremely grateful to BEL, Bangalore for giving us an

opportunity to undergo the Project Work from 1st June, 2011 to 9th July, 2011 in

the DFCC Manufacturing. We take this opportunity to express our profound

sense of gratitude and respect to all those who helped us throughout the duration

of this project.

We sincerely thank Mr.K. Muralidharan, DGM (EW&A/Testing) and all

other executives of the “DFCC Manufacturing” whose cooperation and help

has been vital to make the project work successful.

Weexpress our gratitude towards Mr. AtmaDev Singh, Senior Engineer

(Avionics Testing/FCS, EW&A)for active guidance, project directive and their

continuous interaction and monitoring till the completion of the project.

We are grateful to Prof. V.P. Sandlas, Head of Department, “Amity

Institute of Space Science and Technology” for encouraging us and fostering

an excellent academic climate in the institute.

We express our sincere gratitude to all our professors, our parents and

friends who have directly or indirectly helped us in the successful completion of

this project.

A report of this nature is a product of ideas and experiences of several

persons, accumulated over years, though we are unable to mention them all, our

debt of gratitude to them is no less.

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TO THE READERSTo understand the material in this text, the reader is assumed to have basics of

avionics along with some basic idea aboutthe aircraft stability and control.

This text covers the theoretical knowledge of the controls of the aircraft through

Digital Flight Control Computer (DFCC) as well as practical knowledge of

Operational Flight Programme (OFP). To know about OFP, the reader must

have prior knowledge of Assembly Language. For the ease of readers we have

included the Instruction Set Reference for microprocessor i960. To test and

reinforce your learned skills, it is imperative that you try to solve the programs

on your own.

You can learn the skills of making program of testing OFP by seeing how each

program is approached and built. This increases your store of necessary

knowledge.

To really master a subject, a continuous interplay between skills and knowledge

must take place. We would like to emphasize that there is no short cut to

learning except by “doing.”

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CONTENTSPage

PREFACE

CHAPTER 1 INTRODUCTION

1.1 About BEL

1.2 Initial Phase of LCA

1.3 Brief About the Project

1.4 Fly-By-Wire

1.5 DFCC

1.6 Distributed Quadruplex ADC

CHAPTER 2 TEST PROCEDURES AND SYSTEMS

2.1 Acceptance Test Procedure

2.2 ETS for LCA

2.3 ATS for LCA

2.4 ADC Test System

2.5 Onboard FCS for LCA

2.6 DFCC Digital ATE

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CHAPTER 3 OFP: OPERATIONAL FLIGHT PROGRAMME

3.1 Digital Card

3.2 Coding of the Program

3.3 Process.s Explanation

3.4 DFCC Digital ATE - OFP Test Report

CHAPTER 4 ADVAMTAGES & APPLICATIONS OF DFCC

4.1 Advantages

4.2 Applications

CHAPTER5 CONCLUSION

APPENDICES

A Instruction Set Refernce

B Assembler Directives

C IC’s Used

ABREVIATIONS

REFERENCES

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PREFACEDFCC (Digital Flight Control Computer) has been designed and developed by

Aeronautical Development Establishment (ADE) for Digital Fly-By-Wire

(FBW) Flight Control System (FCS) of Light Combat Aircraft (LCA). DFCC

has four electrically independent identical channels housed in a single Line

Replaceable Unit (LRU). Majority of industrial Robots are position controlled

devices that move exactly in co-ordination with the data provided by the

feedback system within a robotic environment. Here the feedback system

becomes a very important aspect of the robotic operation. DFCC works

according to the output given by Air Data Computer (ADC).

Operational Flight Program (OFP) Test is SRU level test performed on Digital

Card to test the functionality of various components like SRAM, NVRAM,

Timer, Cross Channel Data Link (CCDL), RS-422, Watch Dog Monitor

(WDM) etc. Generally we test the correctness of the components.

LUV VERMA

RAJWANT BAINS

ABHA GUPTA

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CHAPTER1

INTRODUCTION

1.1 About BELBEL was setup at Bangalore by the Government of India (GoI) in 1954 to meet

the specialized professional electronics needs of the Indian Defence Services.

Over the years, it has grown into a multi-product, multi-unit company serving

the needs of customers in diverse fields in India and abroad.

BEL’s vast product spectrum includes Communication equipment, Radars,

Sonars, Naval Systems, Tank Electronics, Electronic Warfare Equipment, C41

Systems, Electro Optics, Satcom, turnkey projects etc. meeting stringent

military specifications.

BEL also meets the requirements of the civilian segment in areas such as

telecommunication and broadcasting, solar photovoltaics, components and

turnkey system solutions. BEL has developed and supplied electronic voting

machines to the election commission of India.

A leader in professional electronics, BEL is among an elite group of public

sector undertakings which have been conferred the Navratna Status by the GoI.

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1.2 Initial Phase of LCAIn 1983, India commenced a programme to develop an aircraft to replace

itsaging MiG-21s as the Air Force's primary multi-role tacticalfighter. The ADA

was established with the sole purpose of developing the Tejas.

LCA’s design was finalized in 1990 as a small, delta-winged machine. To avoid

failures in the development of the final variant, it was decided that Full Scale

Engineering Development would proceed in two phases.

Phase 1 would consist of DDT of two aircraft that would be Technology

Demonstrators (TD-1 and TD-2) and construction of a Structural Test

Specimen. After the TD aircraft were to be tested extensively, construction of

two Prototype Vehicles (PV1and PV-2) would commence, and creation of

infrastructure and test facilities for all the aircraft would take place.

The two Technology Demonstrators (TD-1 and TD-2) were completed by 1995,

but were kept grounded due to structural concerns, and trouble with the

development of the FCS. In 1992, the LCA National Control Law team was set

up by NAL, since no nation exports Fly-by-Wire technology to other nations.

Since India did not possess advanced real time ground simulators, eventually

the US firm Lockheed Martin was brought in to consult on the latter of these

difficulties.

Eventually, the integration of the flight control laws was done indigenously by

the NAL team. It has been successful; one of the test pilots said that he found it

easier to take off with LCA than Mirage. The LCA has been given Level 1 (top-

most) rating by all its Test pilots. Nevertheless, the first LCA technology

demonstrator finally took to the air in 2001.

LCA – Tejas

The LCA is the smallest and lightest combat jet in the world. It is a single pilot,

single engine, supersonic delta wing aircraft. The Tejas has the delta wing

13

configuration, with no tailplanes or foreplanes, features a single vertical fin. It

integrates technologies such as relaxed static stability, fly-by-wire flight control

system, advanced digital cockpit, multi-mode radar, integrated digital avionics

system, advanced composite material structures and a flat rated engine.

Since the Tejas is a relaxed static stability design, it is equipped with a

quadrupledigital FBW flight control system to ease handling by the pilot.The

Tejas' aerodynamic configuration is based on a pure delta-wing layout with

shoulder-mounted wings. Its control surfaces are all hydraulically actuated. The

wing's outer leading edge incorporates three-section slats, while the inboard

sections have additional slats to generate vortex lift over the inner wing and

high-energy air-flow along the tail fin to enhance high-AoA stability and

prevent departure from controlled flight. The wing trailing edge is occupied by

two-segment elevons to provide pitch and roll control. The only empennage-

mounted control surfaces are the single-piece rudder and two airbrakes located

in the upper rear part of the fuselage, one each on either side of the fin.

Fig 1 - An overview of LCA-TEJAS aircraft

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http://en.wikipedia.org/wiki/Air_brake_(aircraft)

http://en.wikipedia.org/wiki/Rudder#Aircraft_rudders

http://en.wikipedia.org/wiki/Empennage

http://en.wikipedia.org/wiki/Flight_dynamics

http://en.wikipedia.org/wiki/Elevon

http://en.wikipedia.org/wiki/Vertical_stabilizer

http://en.wikipedia.org/wiki/Vortex_lift

http://en.wikipedia.org/wiki/Leading_edge_slats

http://en.wikipedia.org/wiki/Flight_control_surfaces

http://en.wikipedia.org/wiki/Wing

http://en.wikipedia.org/wiki/Aircraft_flight_control_systems

http://en.wikipedia.org/wiki/Relaxed_static_stability

http://en.wikipedia.org/wiki/Flat_rated

http://en.wikipedia.org/wiki/Fly-by-wire

http://en.wikipedia.org/wiki/Fly-by-wire

http://en.wikipedia.org/wiki/Relaxed_stability

1.3 Brief about the ProjectDFCC is a state of the art, multiple redundant (improving its reliability, one

channel will take over if another fails) digital fly by wire flight control system

of the LCA, Tejas, which basically controls the maneuvering (pitch, yaw & roll)

of the aircraft.

The Digital module is the core of the DFCC unit and it consists of a main

computing unit for control law and redundancy management. The Digital card

provides the basic hardware interfaces controlling the DFCC.

OFP tests are performed for the various components of the Digital Card of the

DFCC:

1. SRAM Read

2. SRAM Write

3. NVRAM Read

4. NVRAM Write

5. Timer Read & Write

6. Timer Signal Generation

7. To transmit and receive serially through UART

8. CCDL Communication Test

The advantages of FBW controls were first exploited by the military and then in

the commercial airline market. DFCC has the following advantages:

1. Automatic Stability Systems

2. Safety and Redundancy

3. Weight Saving

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1.4 Fly-By-WireFBW is a system that replaces the conventional manual flight controls of an

aircraft with an electronic interface. The movements of flight controls are

converted to electronic signals transmitted by wires and flight control computers

determine how to move the actuators at each control surface to provide the

ordered response. The FBW system also allows automatic signals sent by the

aircraft's computers to perform functions without the pilot's input, as in systems

that automatically help stabilize the aircraft.

DevelopmentMechanical and hydro-mechanical flight control systems are relatively heavy

and require careful routing of flight control cables through the aircraft by

systems of pulleys, cranks, tension cables and hydraulic pipes. Both systems

often require redundant backup to deal with failures, which again increases

weight. Furthermore, both have limited ability to compensate for

changing aerodynamicconditions. Dangerous characteristics such as stalling,

spinning and PIO, which depend mainly on the stability and structure of the

aircraft concerned rather than the control system itself, can still occur with these

systems.

The term "fly-by-wire" implies a purely electrically-signalled control system.

However, it is used in the general sense of computer-configured controls, where

a computer system is interposed between the operator and the final control

actuators. This modifies the manual inputs of the pilot in accordance with

control parameters.

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http://en.wikipedia.org/wiki/Stall_(flight)

http://en.wikipedia.org/wiki/Aerodynamics

http://en.wikipedia.org/wiki/Aircraft_flight_control_systems

http://en.wikipedia.org/wiki/Actuator

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Aircraft_flight_control_system#Hydro-mechanical

Basic operationFly-by wire systems are by their nature quite complex; however their operation can be explained in relatively simple terms. When a pilot moves the control column, a signal is sent to a computer through multiple wires (channels) to ensure that the signal reaches the computer. A 'Triplex' is when there are three channels being used. The computer receives the signals, performs a calculation (adds the signal voltages and divides by the number of signals received to find the mean average voltage) and adds another channel. These four 'Quadruplex' signals are then sent to the control surface actuator, and the surface begins to move. Potentiometers in the actuator send a signal back to the computer (usually a negative voltage) reporting the position of the actuator. When the actuator reaches the desired position, the two signals (incoming and outgoing) cancel each other and the actuator stops moving (completing a feedback loop).

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http://en.wikipedia.org/wiki/Feedback

http://en.wikipedia.org/wiki/Potentiometer

http://en.wikipedia.org/wiki/Actuator

http://en.wikipedia.org/wiki/Arithmetic_mean

1.5 DFCCDFCC is a quad redundant flight critical computer based on Intel 80960 32 bit

RISC microprocessor. Each of the four identical channels consists of:

Digital Card

Analog-1-L Card

Analog-1-R Card

Analog-2 Card

Power Supply Card

Fig 2 –A Complete DFCC Chassis

Each channel is powered by an independent power supply and all housed in a

single LRU. High-speed serial links (CCDL) connect these four channels under

the control of redundancy management software to perform system failure

detection and control reconfiguration. The DFCC channels use a safe subset of

‘Ada’ language for the implementation of software.

The Digital module is the core of the DFCC unit and it consists of a main

computing unit for control law and redundancy management, and MIL-STD-

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1553B, & RS-422 interfaces to different subsystems like ADT, GUH panel,

FTP and CDR.

The analog boards in each channel provide drive/interfaces for all FCS related

items in the aircraft like primary and secondary actuators, sensors, cockpit

controls and indicators.

The power supply unit provides DC power to the internal circuits and sensor

units like RSA,ASA, ADT, LVDT and actuators. Provision is made in the

design for extensive signal monitoring and built-in test and recording. Each

channel has a transputer based high-speed serial link for real-time DMA,

interfaces for on-ground testing/debugging and special purpose ASICs for I/O

interfaces.

Fig 3 - Integrated Flight Control Systems

The DFCC receives signals from quad rate, acceleration sensors, pilot control

stick, rudder pedal, triplex air data system, dual air flow angle sensors, etc. The

DFCC channels excite and control the elevon, rudder and leading edge slat

hydraulic actuators. The computer interfaces with pilot display elements like

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multi-function displays through MIL-STD-1553B avionics bus and RS 422

serial link.

The DFCC incorporates state-of-the-art technology for chassis, printed wiring

boards, board assembly and front panel interconnection with the motherboard

through flex circuitry. The box has a dip-braised chassis, and double walled

construction for force air-cooling.

The DFCC is designed to operate upto 1 hour after failure in supply of cooling

air. The printed wiring boards are 10-22 layer type with heat sink bonding for

thermal management. The average power dissipation is around 300 watts and

the unit weighs 27.8 kgs.

The DFCC is qualified through multi-level testing such as assembly validation,

SRU level testing using ATE, and LRU level ATPusing high performance test

equipment (ETS) to ensure confirmation of performance. The unit meets all the

environmental test standards specified for installation on military aircraft.

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1.6 Distributed Quadruplex ADCADC developed by ADE is an extremely compact real-time embedded

computer based on INTEL 80960MC 32-bit processor. The architecture is

optimized for quad redundant application under the control of redundancy

management software to perform failure detection and control reconfiguration.

ADC houses four pressure transducers with pneumatic connections at the front

panel. The variable frequency output of the pressure transducer is converted

through hardware implemented Frequency to Digital Converters assuring

accuracy of 0.02% of full scale value. It also provides analog and discrete

interfaces to sense Total Air Temperature through 3 wire RTD Sensor, Angular

Position through RVDT Sensors and De-icing currents through current

transformers. ADC is equipped with high speed serial links for ground support

applications like ‘real-time debugging’, and ‘program download’ essential for

pre and post flight checks. It can communicate with other three similar ADC’s

for quad redundant application through dedicated Inter ADC Communication

Links. It can communicate with host DFCC through a dedicated RS-422 Serial

Links.

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CHAPTER 2

TEST PROCEDURES AND SYSTEMS

2.1 Acceptance Test Procedure

PROCEDURAL INSTRUCTIONS

ATP is the sequence of performing manual/automatic test on the DFCC. The

tester might follow this procedure or have the flexibility to carry out manual

checks after completing all automatic checks while performing these tests since

tests are self-contained within an interface and will not depend on prior setups

in order to achieve the desired results.

STANDARD INITIALIZATION

Power Application:

DFCC Power Supplies of all four channels should be OFF initially. Apply +28.0

VDC to DC power.

Warning:

Power is applied to the four channels of DFCC, one channel at a time. As the

power is applied to each channel, steady state input current monitored at the

front panel meter of the DFCC power supply should not exceed 7.5A per

channelat +28.0 VDC.If it exceeds the current limit, DFCC power supply

should be switched off immediately for fault diagnosis.

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ETS-DFCC SPIL Link Check

Through appropriate ‘tip’ command, observe that ETS-DFCC SPIL link, in all four

channels is established.

ATP’s are defined for SRU Test and LRU Test performed on DFCC.

SRU TEST

SRU test is the card level testing for digital, analog and power supply card.

Digital Card Test

Transputer Test (301 Tests)

OFP Test (100 Tests)

Interrupt Test (15 Tests)

Analog Card Test

Gain Test (24 Tests)

Frequency Response Test (17 Tests)

Transition Test (4 Tests)

Digital Performance Test (12 Tests)

Power Supply Card Test (23 Tests)

LRU TEST

LRU test is the DFCC unit level test. LRU Test is performed to check the

functionality of primary and secondary actuators.

Primary Test

Rudder

Elevon

Left Inboard

Left Outboard

Right Inboard

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Right Outboard

Secondary Test

Slat

Left Inboard

Left Midboard

Left Outboard

Right Inboard

Right Midboard

Right Outboard

Airbrake

De-icing Sensor

LRU test is divided into three sub-tests, the sequence of which is described as

follows:

Pre-ESS Test

Group I Test

Automatic

Semi-automatic

Power Auto Test

Manual

Frequency Response Test

ESS Test

Random Vibration I Test

Group III Test

Power Auto Test

CPU Interrupt Test

Discrete Test (Analog-Digital-Analog)

WDM Test

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Group II Test

Thermal Test

Post ESS Test

Random Vibration II Test

Group I Test

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2.2 ETS for LCAThe Engineering Test Station is a real-time automatic/manual test station used

for functional verification of the quadruplex redundant digital fly-by-wire FCS

of the LCA. It provides the capability to simulate FCS related sensors,

actuators, aircraft panels and real aircraft interfaces with provisions for

connecting real sensors and actuators including fault insertion capability. The

test equipment is used to support real-time hardware/software integration testing

and systems testing of the FCS.

The ETS is used for verifying the functionality of DFCC and carrying out the

real-time HSI of DFCC with other elements of FCS. To meet these

requirements, the ETS provides the simulated stimulants to DFCC inputs,

monitors the DFCC outputs, simulates the loads required for the DFCC outputs

and provides fault injection capability. The ETS has the capability to simulate

all the actuators which can be replaced with real equipment. ETS provides a

means for carrying out the incremental integration of all the sub-systems of

LCA FCS.

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2.3 ATS for LCAThe two main types of actuators used in the LCA are DDV type quadruplex

actuators used for actuating the primary control surfaces of the aircraft i.e. the

elevons and rudder, and EHSV type duplex actuators used for actuating the

secondary control surfaces viz. the leading Edge Slats and the Air-Brake. The

ATS is a Special Type to Test Equipment developed for testing all aspects of

these complex state-of-the-art Actuators in normal, fail operational and fail safe

modes.

The ATS principally duplicates the functionalities of the DFCCof LCA. It

incorporates failure injection facility and has capabilities to overcome force

fighting in the redundant coils of DDV Actuators. The ATS provides quad

channel electronics servo-loop closure, coil current equalization, excitation to

position sensors (LVDTs), signal conditioning and fail safe shut-off functions.

The ATS has been designed to provide flexibility in injection of signal for

testing and monitoring of actuator performance. A total of nine test sets (in

several combinations of actuators) have been built and supplied to different

users in the LCA program.

Special Computer/Actuators test sets can be custom designed and built to meet

specific requirements of users.

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2.4 ADC Test SystemThe AIRDATS is a real-time multi-processor, cPCI based system using current

state-of-the-art hardware and software (RT-Linux) for complete

hardware/software integration, verification and validation of all the four ADCs

simultaneously, that have been developed newly for the LCA to augment the

DFCC. Custom-built software includes Integrated Test Environment System

Software with GUI that enables the test engineers to carry out manual or

automated tests on the target hardware and software exhaustively.

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2.5 Onboard FCS for LCAADE has developed the onboard software of FCS for LCA. It is class I, Safety

Critical software resident in DFCC which is a real-time embedded system. This

class of software demands a very strict implementation of Software Quality

Assurance and Software Configuration Management. Development of FCS

software is a critical technology area, which has been developed by very few

countries and ADE has taken the initiative to develop this software for the self

reliance.

LCA-FCS is full authority digital FBW system for an unstable aircraft with

stability augmentation and carefree maneuvering. The FCS software primarily

acquires the inputs (pilot & sensors), implements redundancy management of

inputs and controls laws and commands the Flight Control Actuation. Beside

this, it is also responsible for auto-piloting, information to the pilot about

vehicle parameters, failure annunciation and fault logging. This software is

designed with fault tolerance features and is developed using ‘Ada’ language

satisfying the latest aviation standards (DO/DoD) for software.

15 versions of FCS software have flown for over 1000 flights on 7 different

LCAs. The flawless flights of the air vehicles show the quality of the software

developed by ADE.

In order to take care of the hardware obsolescence of air data system ADC was

developed. Thus single CSCI software has been re-designed as two CSCI for

two different LRU’s (DFCC & ADC). Further FCS software is also being

developed for the LCA Trainer and LCA Navy by re-using the software

components.

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2.6 DFCC Digital ATEThe DFCC Digital Module is an assembly of two boards integrated into one

module- the CPU board and the CCDL/ 1553 board. Both the boards are tested

together by the ATE, as a single module.

Power Supplies:

The DFCC Digital Module will be powered with +5V, +15V and -15V power

supplies. The power supplies are fixed power supplies and has sufficient margin

in their current rating relative to the maximum current that is expected to be

drawn by the modules in their specifications. The 15VDC supply has 200mA

current rating, the -15VDC supply will have 500mA current rating and the

5VDC supply has a 10A current rating. The 5VDC supply has remote sense and

compensates for up to 2V line drop and ensures 5V at the card pins. All the

power supplies have enable / disable through relays.

Digital Input / Output:

The Digital In, Out and bidirectional signals will be driven or read with signals

from digital I/O cards in the ATE. These bits will be for static set/clear or

monitoring (i.e., the Digital I/O are not intended for high speed switching). The

functional test is carried out by the test software that will be downloaded to the

on-board CPU through Transputer Communication Link. The digital output bits

are CMOS voltage level compatible. The I/Os will be handled by two numbers

of 128 output TTL I/O cards, which are CMOS voltage compatible.

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Analog Inputs:

The 7 analog input channels of the DFCC Digital Module are excited from a

Programmable DC source with 16 channels, and there is one DC source channel

allotted per channel of analog input of the DFCC. These signals are to be

programmed to any DC voltage from -10V to +10V with 16 bit resolution. The

analog output monitoring caters also to the monitoring of these analog signals

which are input to the DFCC allowing for self-test of the ATE.

Open – Ground Input / Output:

Open collector outputs are provided for the data transfer acknowledge signal.

Similarly, for open collector input signals, relay contacts are provided.

1553B Communication Interface:

For handling the 1553B communications, an IP based 1553B communication

module (DP-IP-5532) is mounted on a cPCI compatible IP carrier board.

RS422 Communication Interface:

8 channels of RS422 transmit / receive is provided for the testing of RS422

channels in the DFCC Digital module. These will be used to test each of the RS

422 communication links, independent of the RS422 communication links of

the board itself. These interfaces are also provided on IP form factor mounted

(DP-IP-4221) on a cPCI compatible IP-carrier board.

Cross Channel Data Link Interface:

The cross channel data link testing is catered with 1 board with 4 transmitters

(Data input for all the transmitters are from same source) and 4 receivers. This

board is provided in PMC form factor and provides the CCDL communication

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link. The CCDL interface is achieved by using the SILC ASIC. The CPLD

available on the board provides the glue logic between the SILC interface and

the PCI-PCIBridge local bus interface.

Transputer Interface Board (Link Adapter Card):

The Transputer link testing is carried out with the Transputer Interface Board

(Link Adapter Card). This board is provided in PMC form factor and provides

the Transputer link with RS422 compatible physical interface,

Manchesterencoding and decoding as required by the module specifications,

and of the ARINC like frame formats shown in the module specifications.

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CHAPTER 3

OFP: OPERATIONAL FLIGHT PROGRAMME

3.1 Digital CardThe Digital module is the core of the DFCC unit and it consists of a main

computing unit for control law and redundancy management, and MIL-STD-

1553B, & RS-422 interfaces to different subsystems like ADT, GUH panel,

FTP and CDR.

Digital module design is centered on the Intel’s 80960MC

processorarchitecture. All hardware interfaces of Digital card, Analog card and

power supply cards are accessed by the software via the following two systems

by read/write to a valid address:

1. Processor -i80960MC

2. Transputer -T805

The above mentioned two systems are connected to the following buses:

1. Local Bus

2. System Bus

MICRO-PROCESSOR -I80960MC

The i960 MC microprocessor is the military grade member of the i960

architecture family, designed especially for high reliability embedded

applications. The i960 processor family is based on a 32-bit architecture

designed specifically to meet the needs of embedded applications such as

avionics, integration and performance is critical.

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The i960 architecture can best be characterized as a high-performance

computing engine. It features high-speed instruction execution and ease of

programming. It is also easily extensible, allowing processors and controllers to

be conveniently customized to meet the needs of specific processing and control

applications.

Some of the important attributes of the i960 architecture include:

1. Full 32-bit registers

2. High speed, pipelined instruction execution

3. A convenient program execution environment with 32 general purpose

registers and a versatile set of special-function registers

4. Highly optimized procedure call mechanism that features on chip caching

of local variables and parameters.

5. Extensive facilities for handling interrupts and faults.

6. Extensive tracing facilities to support efficient program debugging and

monitoring.

The i960 MC processor implements the i960 architecture, plus it offers several

extensions to the architecture. Some of these extensions, such as on-chip

support for floating-point arithmetic, virtual memory management and

multitasking are designed to enhance overall system performance and

integration. Several other extensions are designed to enhance system reliability

and robustness, including facilities for hardware enforced protection of software

modules.

TRANSPUTER -T805

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The Transputer(INMOS T805) is used for interface with the processor and for

real time interface with the ground equipment. Transputer has access to all

theinterfaces that processor can access.

INTERFACES ON DIGITAL CARD

The interfaces on the Digital card with theProcessor and the Transputer access

are as follows:

1. EEPROM interface

2. SRAM interface

3. NVRAM interface

4. Interrupt Controller

5. Timer Controller

6. Local Discrete I/O

7. 1553 B Interface

8. CCDL

9. RS – 422 Interface

10.Analog I/O

11.Analog Discrete I/O

12.GYRO Interface

13.WDM

The interfaces which are on “Local Bus” and physically located on CPU A2

assembly are:

1. EEPROM interface:

Two separate banks of EEPROM are provided,

160k x 32 word for OFP

160k x 32 word for DBU

Each bank contains low and high speed EEPROMs, for the time criticalcode.

2. SRAM interface:

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Very high speed SRAM chips with total capacity of 32 k x 32 words are usedas

Scratchpad memories.

3. NVRAM interface:

2k x 16 word of Non-volatile memory is used for storage of data duringpower

Failure.

4. Interrupt Controller:

The CPU (processor) is interfaced with PIC which handles up to eight

independent interrupts, resolves the priorityand returns 8 bit vector to the CPU.

5. Timer Controller:

The programmable interval timer is used to generate iteration interrupt, 12.5ms

Time frames to the processor and this is a direct interrupt to theprocessor.

6. Local Discrete I/O:

There are 24 discrete inputs and 16 discrete outputs. These are used

forinterfacing the local discrete, sync discrete and channel IDs.

The other I/O interfaces on “System Bus”located on CPU A1 assembly are as

follows:

7. 1553 B Interface:

1553B interface provides the MIL-STD-1553B interface between the DFCCand

the aircraft’s avionics bus.

8. CCDL:

The CCDL interface provides a 2 MHz serial link between each local

(self)channel of the DFCC and its foreign channels.

9. RS – 422 Interface:

This interface provides the serial links between the DFCC and the Air Data

System, FTP, FTI,GUH panel and CDR.

10.Analog I/O:

The Analog I/O interface consists of the Analog -To- Digital (A/D) and Digital-

36

To-Analog (D/A) interface. The A/D interface converts inputs from analogcards

to digital form for use by the software. The D/A interface convertssoftware

computed output values to the analog form for the use by theanalog cards.

11. Analog Discrete I/O:

The Discrete I/O interface consists of the discrete input (DI) and the

discreteoutput (DO) interface. The ‘DI’ interface groups discrete input signals

intobuffered registers that can be read by the software. The DO

interfacetransfers computed software discrete values into buffered register

outputs foruse by the software. The D/A interface converts software computed

outputvalues to analog form for use by the analog cards.

Fig 4–Block Diagram of the DFCC Digital Module

12.GYRO Interface:

37

Three rate gyros namely Pitch Rate Gyro, Roll Rate Gyro & Yaw Rate Gyro

aresupposed to spin at constant speed. This interface detects whether the

gyrosare spinning at their operating rates. Failure to spin at this designated

rateshall output a discrete, indicating failure.

13.Watch Dog Monitor (WDM):

The WDM interface independently monitors the health of the CPU. It triggersa

hardware interrupt if the software does not communicate with WDMaccording

to the protocol.

All the interfaces on the system bus except RS - 422 interfaces are controlled

and/or physically implemented in one ASIC, SILC located on CPU A1 side of

the assembly.

The DFCC Digital Module is an assembly of two boards integrated into one

module- the CPU board and the CCDL/ 1553 board. Both the boards are tested

together by the ATE, as a single module.

The communication between A1 and A2 side is established using bottom

connector on the digital card. Each IC’s are powered up through bottom

connector.

The following functions are provided for by the circuit card assembly towards

A2side:

Clock Generator

i960MC Processor

Local Bus Controller

OFP memory EEPROMs Interface

DBU memory EEPROMs Interface

SRAM

NVRAM

Local Discrete I/O

38

Interrupt controller (82C59A)

Programmable Timer (82C54)

Transputer Interface

System Bus Interface

DBU Engage Logic

Boundary Scan Chain

The following functions are provided for by the circuit card assembly and

different interfaces in the board towards A1 side:

System Bus Interface Control

System Bus Arbiter

Cross Channel Data Link

MIL-STD-1553B Remote Terminal

Watch Dog Monitor

RS-422 Serial Interface

Digital to Analog Interface

Spin Motor Rate Detector

Discrete Input / Output Control

Test UART Interface

IEEE 1149.1 Boundary Scan Test Interface.

39

3.2 Coding of the ProgramOFP tests are performed for the various components of the Digital Card of the DFCC.

Fig 5–DFCC CPU Memory Map

40

STEPS TO COMPILE & TEST THE PROGRAM

COMPILING:

1. After completing the coding save all thefive .s files in a folder.

2. Copy your folder to C:\Program Files\Dos-Box\Programs\ASM\

3. Now open Dos-Box

4. mount C programs

5. C:\

6. C:\>cd ASM\project ◄┘

7. C:\ASM\Project>i960 ◄┘

8. C:\ASM\Project>build ◄┘

9. C:\ASM\Project>dir ◄┘

10.A list of files will open. Check the size of ERRORS file. If the size is 0

byte then proceed to the next step else goto your folder and check the

errors & resolve them.

11.C:\ASM\Project>rom960 ◄┘

12.rom960>mkimage a.out a.ima ◄┘

13.rom960>ihex a.ima in.hex mode32 ◄┘

14.rom960>exit ◄┘

15.C:\ASM\Project>trim ◄┘

16.Copy the compressed HEX (OFP_I960.HEX) file and paste it in D:\

readwritetogether>

17. Now open EEPROM_fuse.dsw

18. Run or press F5

19. Then press 2 for OFP test & then 6 for downloading the files.

20.After fusing is over press 7 to exit

21.Switch on the main unit.

22. Goto WDM.

41

42

43

TESTING:

1. TIP # dmas ◄┘ Set the Microprocessor

1. TIP # dmar ◄┘ Reset the Microprocessor

2. TIP # ld addressdata ◄┘ Load Data

3. TIP # fd addressaddressdata ◄┘ Fuse Data

4. TIP # dd addressaddress ◄┘ Read Data

5. TIP # mrhp address ◄┘ Read Single Data

Check the link from the SRU test jig.

If the link is not present then press RESET button.

/* FILE NAME : STACK.S */

/* DFCC CPU CARD, I960 TEST CODE (INTEL HEX FORMAT) DOWNLOAD TO CPU CARD, PROCESS SOURCE FILE

* AUTHORS: ABHA GUPTA, RAJWANT BAINS & LUV VERMA, PROJECT TRAINEES, BEL

* DATE: JULY 2011

* REFERENCE:

* 1. I960 REFERENCE MANUAL

* 2. MMOC CPU A1 DEVICE DRIVER MANUAL

* 3. 8259A INTERRUPT CONTROLLER REF MANUAL */

/* Stack has to be set properly during initialization (Unlike in other processors,

i960 stack grows towards higher address.)

* Stack should contain the following elements during initialization (at 0 offset).

44

* PFP - Previous Frame Pointer (register r0) - This will be initialized to 0 in

the beginning.

* SP - Stack pointer (register r1)

* Local registers (r0 through r15) are stored in the process stack. So, the SP is

initialized to process stack + 0x40 in the beginning, so as to make room for the

16 local registers.

* RIP - Return Instruction Pointer (register r2) - This is the address to which

the controlgoes when a return instruction is executed.In the beginning RIP is

loaded with thestarting address of the process.

* 13 words should be allocated for registers r3 to r1and should be initialized

to zeros.*/

.data

.globl Proc_stack

.globl intstack

.align 12

Proc_stack:

.word 0 /* PFP (register r0) */

.word Proc_stack + 0x40 /* SP (register r1) */

.word Process /* RIP (register (r2) */

.space 4 * 13 /* local registers r3-r15 */

45

.space 4 * 256 /* 1k stack */

intstack :

.space 0x1024 /* this is for interrupts */

/* FILE NAME : DATA.S */



* DATE: JULY 2011

* REFERENCE:




.globl NewPRCB

.globl NewPCB

.globl Frame_num

.globl Fault_count

.globl Nvm_index

.globl NVM

.text

46

.align 4

NewPRCB :

.space 172 /* The space is for copying the PRCB from ROM to RAM */

.data

.align 8

NewPCB:

.space 236 /* The space is for copying the PCB from ROM to RAM */

Frame_num:

.word 7 /* The following space is from Non Volatile Memory to store the fault information.*/

Fault_count:

.word 0 /* Gives total number of faults and fault interrupts */

Nvm_index:

.word 0 /* Pointer into NVM where the fault information is stored */

NVM:

.space 256 /* Space for storing fault information */

/* FILE NAME : PROCESS.S */

47



* DATE: JULY 2011

* REFERENCE:




.set Discrete_Add, 0x00320000

.set Nvram_Select_Val, 0x00000004

.set Nvram_Ofp_Start_Add, 0x00300000

.set Nvram_Ofp_End_Add, 0x00300fff

.set Nvram_Ofp_Size, 0x00300fff - 0x00300000

.set Clear_Val, 0x0000

.set Ram_1553_Start_Add, 0x003c8020

.set Ram_1553_End_Add, 0x003cfffc

.set Ram_1553_Size, 0x003cfffc - 0x003c8020

.set Atod_Ram1_Start_Add, 0x003d0000

.set Atod_Ram1_End_Add, 0x003d03fc

.set Atod_Ram1_Size, 0x003d03fc - 0x003d0000

.set Atod_Ram2_Start_Add, 0x003d0400

.set Atod_Ram2_End_Add, 0x003d07fc

.set Atod_Ram2_Size, 0x003d07fc - 0x003d0400

.set Com_Fill_Start_Add, 0x00206000

48

.set Com_Fill_End_Add, 0x00206100

.set Com_Fill_Size, 0x00206100 - 0x00206000

.globl Process

.text

.align 4

Process:

lda 0x211000,g7 /* Write 12345678 at address 211000 */

ldconst 0x12345678,g8

st g8,(g7)

Test:

lda 0x210000,g7 /* Command Instruction*/

ld (g7),g3

ldconst 0x0,g8

cmpibe g8,g3,Test

ldconst 0x2,g8

cmpibe g8,g3,proc2

ldconst 0x1,g8

cmpibe g8,g3,proc1

ldconst 0x3,g8

cmpibe g8,g3,proc3

ldconst 0x4,g8

49

cmpibe g8,g3,proc4

ldconst 0x5,g8

cmpibe g8,g3,proc5

ldconst 0x6,g8

cmpibe g8,g3,proc6

ldconst 0x7,g8

cmpibe g8,g3,proc7

ldconst 0x8,g8

cmpibe g8,g3,proc8

proc1: /* To check the write operation of SRAM */

lda 0x210000,g7 /* Clear Command */

ldconst 0x0,g8

st g8,(g7)

lda 0x210004,g7 /* Starting Address */

ld (g7),g4

lda 0x210008,g7 /* Ending Address */

ld (g7),g5

lda 0x21000C,g7 /* Data */

ld (g7),g6

loop1:

addi g4,4,g4 /* Increment in Starting Address */

st g6,(g4)

cmpibne g4,g5,loop1

50

b Test

proc2: /* To check read operation of SRAM */

ldconst 0x0,g8 /* Clear Command */

lda 0x210000,g7

st g8,(g7)


ld (g7),g4


ld (g7),g5

loop2:

ldconst 0xFFFFFFFF,g7/* Giving g6 a value for XOR operation */

ld (g4),g2

xor g2,g7,g8 /* XORing, if equal output will be zero */

st g8,(g4)


cmpibne g4,g5,loop2 /* Compare if not equal and run the loop */

b Test /* Goto Command Instruction */

proc3: /* To check the write operation of NVRAM */


ldconst 0x0,g8

st g8,(g7)

lda 0x320000,g7 /* Enable NVRAM */

51

ldconst 0x4,g8

st g8,(g7)

ldconst 0xabababab,g4

lda 0x210020,g10

st g4,(g10)


ld (g7),g4


ld (g7),g5

lda 0x21002C,g7 /* Data */

ld (g7),g6

loop3:

addi g4,4,g4 /* Increment in Starting ess*/

st g6,(g4)


b Test

proc4: /* To check the read operation of NVRAM*/


ldconst 0x0,g8

st g8,(g7)

lda 0x320000,g7 /* Enable NVRAM */

ldconst 0x4,g8

st g8,(g7)

52


ld (g7),g4


ld (g7),g5

loop4:


ld (g4),g2

ldconst 0xFFFFFFFF,g6/* Giving g6 a value for XOR operation */

xor g2,g6,g8 /* XORing, if equal output will be zero */

st g8,(g4)



proc5: /* To Read & Store the Counter Value */


ldconst 0x0,g8

st g8,(g7)

lda 0x34000C,g7 /* Control Register */

ldconst 0x34,g8

st g8,(g7)

lda 0x340000,g7

ldconst 0x00,g8 /* Loading LSB */

st g8,(g7)

lda 0x340000,g7

53

ldconst 0x00,g8 /* Loading MSB */

st g8,(g7)


ldconst 0xD2,g8

st g8,(g7)

loop5:

ldconst 0x22, g6 /* Loading any value for Delay Operation */

ldconst 0x0, g8

addi g8,0x1,g8

cmpibne g6,g8, loop5 /* Compare if not equal and run the loop */

lda 0x340000,g7 /* Read Counter Value - LSB */

ld (g7),g9

ldconst 0xFF,g12

and g9,g12,g9

lda 0x340000,g7 /* Read Counter Value - HSB */

ld (g7),g8

ldconst 0xFF,g12

and g8,g12,g8

shli 8,g8,g8

or g8,g9,g9

lda 0x205000,g7

st g9,(g7)


54

proc6: /* To Generate a square wave using the Timer*/


ldconst 0x0,g8

st g8,(g7)

lda 0x21005c,g7

ld (g7),g9

ldconst 0xFF,g12

and g12,g9,g8

ldconst 0xFF00,g12

and g12,g9,g10

shri 8,g10,g11


ldconst 0x76,g9

st g9,(g7)

lda 0x340004,g7

st g8,(g7)

lda 0x340004,g7

st g11,(g7)

b Test

proc7: /* To transmit and receive serially through UART */


ldconst 0x0,g8

st g8,(g7)

55

lda 0x320000, g10

ldconst 0x80, g11

stos g11,(g10)

ldconst 0x00, g11

stos g11, (g10)

lda 0x3D8004, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D800C, g10

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8008, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8014, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D801C, g10

56

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8018, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8024, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D802C, g10

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8028, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8034, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D803C, g10

57

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8038, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8044, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D804C, g10

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8048, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8054, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D805C, g10

58

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8058, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8064, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D806C, g10

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8068, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8074, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D807C, g10

59

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8078, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8084, g10

ldconst 0x32, g11

stos g11, (g10)

lda 0x3D808C, g10

ldconst 0x7C, g11

stos g11, (g10)

lda 0x3D8088, g10

ldconst 0x24, g11

stos g11, (g10)

lda 0x3D8060, g10

ldconst 0xAA, g11

stos g11, (g10)

lda 0x3D8070, g10

60

ldconst 0xBB, g11

stos g11, (g10)

lda 0x3D8080, g10

ldconst 0xCC, g11

stos g11, (g10)

b Test

proc8: /* CCDL Communication Test */


ldconst 0x0,g8

st g8,(g7)

lda 0x3D6000, g7

ldconst 0x00000800, g8

stos g8, (g7)

lda 0x3D6004, g7


stos g8, (g7)

lda 0x3D6008, g7


stos g8, (g7)

61

lda 0x3D600C, g7


stos g8, (g7)

lda 0x3D6010, g7


stos g8, (g7)

lda 0x3D6044,g7 /*CCDL Control Register*/

ldconst 0x0000,g8

stos g8,(g7)


ldconst 0x0004,g8

stos g8,(g7)


ldconst 0x0000,g8

stos g8,(g7)

lda 0x212000, g7

lda 0x3c2000,g8

ldconst 0x100,g9

62

movstr g8,g7,g9


ldconst 0x0001,g8

stos g8,(g7)

b Test

end_loop:

b end_loop

/* FILE NAME : INTRPT.S */



* DATE: JULY 2011

* REFERENCE:




ldconst 0x2000, g13 /* delay timing */

ldconst 0x0, g3

.set TIMER_8254_T0, 0X00340000

.set TIMER_8254_T1, 0X00340004

63

.set TIMER_8254_T2, 0X00340008

.set TIMER_8254_CW, 0X0034000C

.set TIMER_8254_CW_VAL, 0X30

.set TIMER_8254_TO_LSB, 0XFF /* Timer 0 programmed to 24 */

.set TIMER_8254_TO_MSB, 0XF0 /* 12.5 miliseconds 84*/

.set WDM_REG, 0X003D6028 /* For WDM initialization */

.set WDM_VAL1, 0X6000 /* WDM_VALI is written first */

.set WDM_VAL2, 0X6200 /* and then WDM_VAL2 */


.set WDM_STROBE_BIT, 9 /* WDM strobe bit number */

.set FAULT_ACK_WORD, 0X003d4020 /* This is word where acknowledge has to be checked */

.set FAULT_ACK_BIT, 12 /* bit in FAULT_ACK_WORD */

.set REG_SW_FAIL_WORD, 0X00320000 /* This is the word where the bitto indicate fault is to be set */

.set REG_SW_FAIL_BIT, 8

.set MAX_FAULT_RECS, 5

.set FAULT_REC_SIZE, 20 /* 5 words of 4 bytes */

/*The following two constants are used to differentiate between override and normal faults. */

.set OVERRIDEFAULT, 1 /* To indicate that the fault is a double fault */

64

.set NORMALFAULT, 0 /* The fault is a normal fault*/

.set INTERRUPT_REC_OFFSET, 8 /* Offset of Interrupt record from New Frame pointer */

.set SYS_ERR_FAULT_OFFSET, 72 /* field in PRCB */

.set FAULT_REC_OFFSET, 48 /* Offset of Fault record from New Frame pointer */

.set FAULT_TYPE_OFFSET, 40 /* Offset for fault type in Fault Record */

.set OVERRIDE_FAULT_TYPE_OFFSET, 28 /* Offset for Override faulttype in Fault Record */

.set FAULT_INSTR_ADDR_OFFSET, 44 /* Offset for Address of thefaulting instruction */

.text

.globl GenFaultHandler

.globl OverRideFaultHandler

.globl SysErrorHandler

.globl inthandler

.globl FaultIntHandler

.globl IterationTimer0

.globl ADInitiate

.globl Inv_Add_Int

65

.globl Inv_Acc_Int

.globl Parity_Err_Int

.globl Timer1_Int

.globl Atod_Comp_Int

.globl Wdm_Int

.globl Mil_1553b_Int

.globl Rs232_Int

.globl Tip_Enable_Int

.globl Trace_FaultHandler /* trace fault */

.globl Operation_FaultHandler /* operation fault */

.globl Arith_FaultHandler /* arithmetic fault */

.globl Float_FaultHandler /* floating point fault */

.globl Constr_FaultHandler /* constraint fault */

.globl Vmem_FaultHandler /* virtual memory fault */

.globl Protect_FaultHandler /* protection fault */

.globl Machine_FaultHandler /* machine fault */

.globl Structural_FaultHandler /* structural fault */

.globl Type_FaultHandler /* type fault */

.globl Reserved_FaultHandler /* reserved */

.globl Process_FaultHandler /* process fault */

.globl Descriptor_FaultHandler /* descriptor fault */

.globl Event_FaultHandler /* event fault */

/*

66

* For all the Faults and fault interrupts the following informationis saved in NVM and the processor is restarted.

* Fault number, fault type and subtype

* Instruction pointer causing the fault

* Frame number (will be imported from ADA package)

* Whether Override and System Error fault

*/

.align 4

SysErrorHandler:

lda 0x2003E0, g2

ldconst 0x11111111,g8

lda 0x21F000, g9

st g8, (g2)

st g8, (g9)

b WaitForDiscrete

.align 4

OverRideFaultHandler:

/*This is an Override fault. So, save the fault information and restart the processor. */

lda 0x2003Ec, g2

ld (g2), g3

addi g3, 1,g3

67

st g3, (g2)

lda 0x2003fc, g2

ld (g2), g3

lda 0x2003f0, g2

st g3, (g2)

lda 0x21F110, g9

lda 0x2003E0, g2

ldconst 0xafafafaf, g8

st g8, (g9)

st g8, (g2)

b FaultAction /* jump to actual fault handler */

.align 4

GenFaultHandler:

/* Save the fault information and restart the processor. */

lda 0x2003E0, g2

lda 0x21F120, g9


st g8, (g9)

st g8, (g2)

68

b FaultAction /* handle it */

.align 4

Trace_FaultHandler:

lda 0x2003E0, g2

lda 0x21F120, g9


st g8, (g9)

st g8, (g2)


.align 4

Operation_FaultHandler: /* operation fault */

lda 0x2003E4, g2

ld (g2), g3

addi g3, 1,g3

st g3, (g2)

lda 0x2003fc, g2

ld (g2), g3

lda 0x2003e8, g2

st g3, (g2)

69

lda 0x2003E0, g2

lda 0x21F124, g9


st g8, (g9)

st g8, (g2)


.align 4

Arith_FaultHandler:

lda 0x2003E0, g2

lda 0x21F128, g9


st g8, (g9)

st g8, (g2)


.align 4

Float_FaultHandler:

lda 0x2003E0, g2

lda 0x21F12c, g9


st g8, (g9)

70

st g8, (g2)


.align 4

Constr_FaultHandler:

lda 0x2003E0, g2

lda 0x21F130, g9


st g8, (g9)

lda 0x2003E0, g2

st g8, (g2)


.align 4

Vmem_FaultHandler:

lda 0x2003E0, g2

lda 0x21F134, g9


st g8, (g9)

st g8, (g2)


71

.align 4

Protect_FaultHandler:

lda 0x2003E0, g2

lda 0x21F138, g9


st g8, (g9)

st g8, (g2)


.align 4

Machine_FaultHandler:

lda 0x2003E0, g2

lda 0x21F13c, g9


st g8, (g9)

st g8, (g2)


.align 4

Structural_FaultHandler:

lda 0x2003E0, g2

lda 0x21F140, g9

72


st g8, (g9)

st g8, (g2)


.align 4

Type_FaultHandler:

lda 0x2003E0, g2

lda 0x21F144, g9

ldconst 0xaaaaaaaa, g8

st g8, (g9)

st g8, (g2)


.align 4

Reserved_FaultHandler:

lda 0x2003E0, g2

lda 0x21F148, g9

ldconst 0xbbbbbbbb, g8

st g8, (g9)

st g8, (g2)

73


.align 4

Process_FaultHandler:

lda 0x2003E0, g2

lda 0x21F14c, g9

ldconst 0xcccccccc, g8

st g8, (g9)

st g8, (g2)


.align 4

Descriptor_FaultHandler:

lda 0x2003E0, g2

lda 0x21F150, g9

ldconst 0xdddddddd, g8

st g8, (g9)

st g8, (g2)


.align 4

Event_FaultHandler:

74

lda 0x2003E0, g2

lda 0x21F154, g9

ldconst 0xeeeeeeee, g8

st g8, (g9)

st g8, (g2)


.align 4

Inv_Add_Int:

lda 0x21F044, r4

ldconst 0x44444444, r5

st r5, (r4)

lda 0x360004, r4 /* Duumy read from 8259 */

ld (r4), r5

lda 0x21F048, r4


st r5, (r4)

lda 0x21F04c, r4


st r5, (r4)

ret

75

.align 4

Inv_Acc_Int:

lda 0x21F038, r4


st r5, (r4)

ret

.align 4

Parity_Err_Int:

lda 0x21F038, r4


st r5, (r4)


ld (r4), r5

lda 0x21F03c, r4


st r5, (r4)

lda 0x21F040, r4


st r5, (r4)

ret

76

.align 4

Atod_Init_Int:

ret

.align 4

Atod_Comp_Int:

lda 0x21F028, r4

ldconst 0xaaaabbbb, r5

st r5, (r4)


ld (r4), r5

lda 0x21F030, r4

ldconst 0xbeedfeed, r5

st r5, (r4)

lda 0x21F034, r4

ldconst 0xfeedbeed, r5

st r5, (r4)

ret

.align 4

Mil_1553b_Int:

lda 0x21F050, r4

77


st r5, (r4)


ld (r4), r5

lda 0x21F058, r4


st r5, (r4)

lda 0x21F05c, r4


st r5, (r4)

ret

.align 4

Wdm_Int:

lda 0x2003dc, g0

ld (g0), g1

cmpibne 8, g1, RetWdmN

lda 0x34000C, r4

ldconst 0x34, r5

st r5, (r4)

lda 0x340000, r4

ldconst 0x24, r5

78

st r5, (r4)

ldconst 0xF4, r5

st r5, (r4)

RetWdmN:

ld (g0), g1

cmpibne 4,g1, RetWdmSFE

lda 0x34000C, r4

ldconst 0x34, r5

st r5, (r4)

lda 0x340000, r4

ldconst 0x24, r5

st r5, (r4)

ldconst 0xF4, r5

st r5, (r4)

lda 0x3d6028, r4

ldconst 0x6000, r5

st r5, (r4)

ldconst 0x6200, r5

st r5, (r4)

lda 0x2003D4, r8


st r9, (r8)

79

RetWdmSFE:

ld (g0), g1

cmpibne 16,g1, RetWdmPR

lda 0x2003d4, r8


st r9, (r8)

RetWdmPR:

ret

.align 4

Rs232_Int:

ret

.align 4

Tip_Enable_Int:

lda 0x21F018, r4


st r5, (r4)

lda 0x360004, r4 /* Dummy read from 8259 */

ld (r4), r5

lda 0x21F000, r4

80


st r5, (r4)

lda 0x21F004, r4


st r5, (r4)

ret

.align 4

ADInitiate:

/* A/D Initiate is an interrupt that has to be serviced. Just return from the interrupt, don't do anything else. */

ret

.align 4

Timer1_Int:

lda 0x21F018, r4

ldconst 0xABCDE123, r5

st r5, (r4)

lda 0x21F01C,r4


st r5, (r4)

lda 0x21F100,r4

81

ldconst 0xABCDEDCB,r5

st r5, (r4)

lda 0x21F104,r4

ldconst 0xAAAAAAAA,r5

st r5, (r4)

ret

.align 4

IterationTimer0:

lda 0x2003E4, r4

ldconst 0xBEBEBEBE, r5

st r5, (r4)

ld (g0), g1

cmpibne 8,g1, RetIterN

lda 0x3D6028, r4

ldconst 0x6000, r5

st r5, (r4)

ldconst 0x6200, r5

st r5, (r4)

ldconst 0x6000, r5

st r5, (r4)

lda 0x2003D0, r8


82

st r9, (r8)

RetIterN:

ld (g0), g1

cmpibne 1, g1, RetIterNWS

lda 0x2003D0, r8


st r9, (r8)

RetIterNWS:

ld (g0), g1

cmpibne 2, g1, RetIterWTS

lda 0x3D6028, r4

ldconst 0x6000, r5

st r5, (r4)

ldconst 0x6200, r5

st r5, (r4)

ldconst 0x6000, r5

st r5, (r4)


ld (r4), r5

ld (r4), r5

ld (r4), r5

ld (r4), r5

83

lda 0x3D6028, r4

ldconst 0x6000, r5

st r5, (r4)

ldconst 0x6200, r5

st r5, (r4)

ldconst 0x6000, r5

st r5, (r4)

lda 0x2003D0, r8


st r9, (r8)

RetIterWTS:

ld (g0), g1

cmpibne 4, g1, RetIterWSFE

lda 0x3D6028, r4

ldconst 0x6000, r5

st r5, (r4)

lda 0x2003D0, r8


st r9, (r8)

RetIterWSFE:

ret

84

.align 4

FaultIntHandler:

/* This interrupt indicates some serious fault;save the fault information and restart the processor. */

b inthandler /* just branch to default interrupt handler everything is taken care of there itself */

.align 4

inthandler:

lda 0x21F104,r4

ldconst 0xAAAAAAAA,r5

st r5, (r4)

ret

.align 4

FaultAction :

ret

.align 4

WaitForDiscrete:

ret

Time_Delay:

addi g3, 1, g3 /* increment g3 */

cmpibne g3, g13, Time_Delay

ret

85

/* FILE NAME : INIT.S */



* DATE: JULY 2011

* REFERENCE:




/* i960 code area in EEPROM is 960*4*4 bytes ( 16 K BYTES )

* the starting address is 0x00000000

* the end address is 0x00003FFC

* the PRCB and PCB are in SRAM

* PRCB is 176*4 bytes

* PCB is 240*4 bytes

* the starting address is 0x00200000

* the end address is 0x002003FC ( 1 K BYTES )

* the interrupt table 256*4 bytes (1k)

* the interrupt table address starts at 0x00200400

* the interrupt table end address is 0x002008FC */

.set NewPRCB,0x200000

.set NewPCB, 0x200180

.set PRCB_LEN, 176

.set PCB_LEN, 240

.set RAM_START_CONST, 0x200000

86

.set ROM_START_CONST, 0x0

.set ROM_SIZE_CONST, 0x1FFFF

.set RAM_SIZE_CONST, 0x21FFFF - 0x200000

.set Discrete_Add, 0x00320000

.set Nvram_Select_Val, 0x00000004

.set Nvram_Ofp_Start_Add, 0x00300000

.set Nvram_Ofp_End_Add, 0x00301FFC

.set Nvram_Ofp_Size, 0x00301FFC - 0x00300000

.set Clear_Val, 0x00000000

.set Interrupt_Enable_Value, 0x0000C000

.set New_int_table, 0x00200400

.set int_table_len, 1280

.set New_intstack, 0x00200900

.set intstack_len, 1536

.set INT_CNTRL_VAL, 0xFF0074FF

.set INT_CNTRL_REG, 0xFF000004

.set TIMER_8254_T0, 0x00340000

.set TIMER_8254_T1, 0x00340004

.set TIMER_8254_T2, 0x00340008

.set TIMER_8254_CW, 0x0034000C

.set TIMER_8254_CW_VAL, 0x30

.set TIMER_8254_TO_LSB, 0x99

.set TIMER_8254_TO_MSB, 0x99

87

/* .set TIMER_8254_TO_LSB, 0X24

.set TIMER_8254_TO_MSB, 0X84

Timer 0 programmed to 12.5 milliseconds for clock of 5 MHz */

.set WDM_REG, 0X003D6028 /* For WDM initialization */

.set WDM_VAL1, 0X6000 /* WDM_VAL1 is written first */



.set ICW1_8259A, 0X00360000 /* These addresses are to be verified */

.set ICW2_8259A, 0X00360004

.set ICW3_8259A, 0X00360004

.set ICW4_8259A, 0X00360004

.set OCW1_8259A, 0X00360004

.set OCW2_8259A, 0X00360000

.set OCW3_8259A, 0X00360000

.set IMASK, 0x00 /* Mask all the interrupts */

.set ICW1_VAL, 0x1D

.set ICW2_VAL, 0xF3

.set ICW3_VAL, 0x0

.set ICW4_VAL, 0x9F

.set OCW1_VAL, IMASK

.set OCW2_VAL, 0xFB

.set OCW3_VAL, 0xBE

.set proc_stack,0x00200E00

.set intstack, 0x00201400

88

/* Initial memory image (IMI) should always be in physical memory locations

0X0 to 0X1F

* Following is a description of IMI.

* Word 0 - physical address pointer to initialization segment table

* Word 1 - physical address pointer to base of initialization PRCB

* Word 2 - check word

* Word 3 - instruction pointer to the first instruction of the initialization code

(either physical or virtual depending upon the translation mode specified in

PRCB's processor control word).

* Word 4-7 -check words. (Along with word 2)

* During the first stage of initialization of the processor these words are added

to the pointers for the, initialization segment table initialization PRCB &

startup code to determine a checksum. The check words should be chosen in

such a way that the checksum is zero. */

.globl segtable

.text

.align 12

segtable:

ste0:

.word segtable

.word initPRCB

.word 0

.word start_ip

.word chksum

.word 0,0, -8

.word 0, 0, 0, 0 /* ste 2 */

89

.word 0, 0, 0, 0 /* ste 3 */

.word 0, 0, 0, 0 /* ste 4 */

.word 0, 0, 0, 0 /* ste 5 */

.word 0, 0, 0, 0 /* ste 6 */

.word 0, 0, 0, 0 /* ste 7 */

.set segtable_SS, ((.-ste0) << 2 ) | 0x3F

.word 0, 0

.word 0

.word 0X00FC00FB /* segment table descriptor */

.set pcb_SS, ((.-ste0) << 2) | 0x3F

.word 0, 0

.word NewPCB /* Address in RAM */

.word 0X204000FB /* process descriptor */

/* The following is the fault handler table. Segment Selectors are not required

because the processor is configured for physical Addressing mode. */

.globl ftable

.text

.align 4

ftable:

.word OverRideFaultHandler /* override */

.word 0 /* Segment selectior not required */

.word Trace_FaultHandler /* trace fault */

.word 0

90

.word Operation_FaultHandler /* operation fault */

.word 0

.word Arith_FaultHandler /* arithmetic fault */

.word 0

.word Float_FaultHandler /* floating point fault */

.word 0

.word Constr_FaultHandler /* constraint fault */

.word 0

.word Vmem_FaultHandler /* virtual memory fault */

.word 0

.word Protect_FaultHandler /* protection fault */

.word 0

.word Machine_FaultHandler /* machine fault */

.word 0

.word Structural_FaultHandler /* structural fault */

.word 0

.word Type_FaultHandler /* Fault Type */

.word 0

.word Reserved_FaultHandler /* reserved */

.word 0

.word Process_FaultHandler /* process fault */

.word 0

.word Descriptor_FaultHandler /* descriptor fault */

.word 0

.word Event_FaultHandler /* event fault */

.word 0

91

.space 136

/* First 36 bytes of the interrupt table are reserved for pending interrupts. The

first word (4 bytes) contains the pending priority bits. The following eight words

(32 bytes) contain the information about the particular interrupt that is pending.

*/

.globl int_table

.data

.align 4

int_table:

.space 36 /* pending interrupts */

.word inthandler /* int 8(8) */


.word inthandler /* int 10(a) */

.word inthandler /* int 11(b) */

.word inthandler /* int 12(c) */

.word inthandler /* int 13(d) */

.word inthandler /* int 14(e) */

.word inthandler /* int 15(f) */




.word Rs232_Int /* int 19(13) */





92



.word inthandler /* int 26(1a) */

.word inthandler /* int 27(1b) */

.word inthandler /* int 28(1c) */

.word inthandler /* int 29(1d) */

.word inthandler /* int 30(1e) */

.word inthandler /* int 31(1f) */




















.word Tip_Enable_Int /* int 51(33) */

93





























94




.word Mil_1553b_Int /* int 83(53) */

























95








.word Atod_Comp_Int /* int 115(73) */

.word IterationTimer0 /* int 116(74) */




















96












.word Timer1_Int /* int 147(93) */













.word inthandler /* int 160(a0) */




97







.word inthandler /* int 170(aa) */

.word inthandler /* int 171(ab) */

.word inthandler /* int 172(ac) */

.word inthandler /* int 173(ad) */

.word inthandler /* int 174(ae) */

.word inthandler /* int 175(af) */

.word inthandler /* int 176(b0) */



.word Parity_Err_Int /* int 179(b3) */







.word inthandler /* int 186(ba) */

.word inthandler /* int 187(bb) */

.word inthandler /* int 188(bc) */

.word inthandler /* int 189(bd) */

.word inthandler /* int 190(be) */

.word inthandler /* int 191(bf) */

98

.word inthandler /* int 192(c0) */










.word inthandler /* int 202(ca) */

.word inthandler /* int 203(cb) */

.word inthandler /* int 204(cc) */

.word inthandler /* int 205(cd) */

.word inthandler /* int 206(ce) */

.word inthandler /* int 207(cf) */

.word inthandler /* int 208(d0) */



.word Inv_Acc_Int /* int 211(d3) */







.word inthandler /* int 218(da) */

.word inthandler /* int 219(db) */

99

.word inthandler /* int 220(dc) */

.word inthandler /* int 221(dd) */

.word inthandler /* int 222(de) */

.word inthandler /* int 223(df) */

.word inthandler /* int 224(e0) */










.word inthandler /* int 234(ea) */

.word inthandler /* int 235(eb) */

.word inthandler /* int 236(ec) */

.word inthandler /* int 237(ed) */

.word inthandler /* int 238(ee) */

.word inthandler /* int 239(ef) */

.word inthandler /* int 240(f0) */



.word Inv_Add_Int /* int 243(f3), IRO */

.word 0 /* int 244(f4), reserved */




100

.word SysErrorHandler /* int 248(f8) */


.word 0 /* int 250(fa), reserved */

.word 0 /* int 251(fb), reserved */

.word inthandler /* int 252(fc) */

.word inthandler /* int 253(fd) */

.word inthandler /* int 254(fe) */

.word Wdm_Int /* int 255(ff), INT0 */

/* Startup PRCB contains the initial controls for the processor.

* PRCB should be aligned on a 16 byte boundary.

* word 0 - reserved

* word 1 - processor control word

* bit 0 - reserved

* bit 1 - for multiprocessor preempt - 1

* bit 2,3 - initial state of the processor;

* bit 4 - reserved

* bit 5-9 - non preempt field; required formulti-process execution

(initialize to 0)

* bit 10 - addressing mode; for physical

* addressing - 0

* virtual addressing - 1

* bit 11 - check dispatch port (initialize to 0)

* bit 11-15 - reserved

* bit 16-20 - interim priority (initialize to 0)


* bit 31 - write external priority (initialize to 0)

* word 2 - reserved

101

* word 3 - current process SS; points to PCBvfor the process that is

currently bound to the processor

* word 4 - dispatch port SS (initialize to 0)

* word 5 - physical address of interrupt table

* word 6 - interrupt stack pointer

* word 7 - reserved

* word 8 - region 3 Segment Selector

* word 9 - system procedure table segment selector (initialize to 0)

* word 10 - physical address of fault table

* word 11 - reserved

* word 12-14 - Multiprocessor preemption (initialize to 0)


* word 16,17 - idle time (initialize to 0)

* word 18 - system error fault; used by the processor (initialize to 0)


* word 20-31 - resumption record; used by the processor for instruction

resumption data (initialize to 0)

* word 32-43 - system error fault record; used by the processor to store

system error fault records (initialize to 0) */

.globl initPRCB

.text

.align 4

initPRCB :

.word 0 /* reserved */

.word 0x8 /* except for processor state everything else is zero */


102

.word pcb_SS /* segment selector for the Process Control Block of

the process */

.word 0 /* no dispatch port */

.word int_table /* physical address of interrupt table */

.word intstack /* Address of the interrupt stack */

.word 0 /* reversed */

.word 0x0000027f /* region 3 ss */

.word 0 /* no system procedure table */

.word ftable /* physical address of fault table */


.space 3*4 /* multiprocessor resumption field; not used

initialized to zeros */


.word 0,0 /* idle time */

.word 0 /* system error fault */


.space 12*4 /* resumption record 12 words */

.space 12*4 /* system error fault record; 12 words */

/* PCB should be aligned to 256 byte boundary.

* PCB consists of the follwoing fields :

* word 1,1 - queue record; several PCBs can be linked together to form a

queue (initialize to 0)

* word 2 - Receive message; (initialize to 0)

* word 3 - dispatch port SS; (initialize to 0)

* word 4 - upper 16 bits reserved; lower 16 bits for Residual-time-slice used

by processor in case of multiprocess configuration (initialize to 0)

* word 5 - Process Controls Word

103

* bit 0 - trace enable; if set generates tracefault (initialize to 0)

* bit 1 - execution mode; user mode –0&supervisor mode -1


* bit 6 - time slice reschedule (initialize to 0)

* bit 7 - time slice (initialize to 0)

* bit 8 - timing; used for updating execution time (initialize to 0)

* bit 9 - resume; signals the processor that an instruction has been

suspended (initialize to 0)

* bit 10 - trace fault pending; allows the processor to keep track of the

fact that an enable trace event has been detected. software should not modify

this flag (initialize to 0)

* bit 11 - preempt; determines whether or not the process is eligible to

be preempted (initialize to 0)

* bit 12 - refualt; is set by the processor on override fault to indicate

that another fault has to be serviced (the original fault) (initialize to 0)

* bit 13,14 - state; 00 - executing, ready orblocked

* 01 - interrupted

* 10,11 - reserved

* bit 15 - reserved

* bit 16-20 - priority of the process (can be set 0 )

* bit 21-31 - internal state (don't know a bit)

*word 6 - bit 0-7 - lock; used for multiprocessor configuration.

* When bit 0 is 1 - process bound to a processor

* 0 - process is not bound

* bit 8-31 - process notice;

* bit 16,31 - event request flag

* bit 8 - set to 0


104

* bit 17-30 - preserved (initialize entire word to 0 in the beginning)

*word 7 - trace controls (initialize to 0)

*word 8-11 - reserved

*word 12 - region 0 ss



*word 15 - arithmetic controls

*word 16 - reserved

*word 17 - upper 16 bits reserved; lower 16 bits - next timeslice (initialize to

0)

*word 18-19 - execution time (initialize to 0)

*word 20-31 - resumption record (initialize to 0)

*word 32-59 -global and floating point registers (initialize to 0) */

.globl PCB

.data

.align 8

PCB:

.word 0, 0 /* link SS and current */

/* port_semaphore SS */

.word 0 /* receive message */

.word 0 /* no dispatch port SS */

.word 0 /* residual time slice */

.word 0X00010000 /* process controls word */

/* priority is set to 1 */

/* all other fields set to 0 */

.word 0 /* process notice and lock */

105

.word 0 /* trace controls */

.word 0, 0, 0, 0 /* reserved */

.word 0x0000027f /* region 0 SS */



.word 0X20000000 /* arithmetic controls */


.word 0 /* next time slice */

.word 0, 0 /* execution time */

.space 48 /* resumption record */

.space 4 * 15 /* global registers go-g14 */

.word proc_stack /* frame pointer g15 */

/* this field should point */

/* to the stack frame of */

/* the process */

.space 12 * 4 /* floarting point registers */

/* The startupcode does the following things:

* 1. copy the following data structures from ROM to RAM:

*

* 2. Initialize the stack (process and interrupt). (process stack should contain

the PFP, SP, RIP, of the process).

*

* 3. Initialize the Interrupt control Register.

* The configuration of the INTO - INT3 is as follows:

* INTO - External interrupt 1

* INT1 - External interrupt 2

* INT2 – INTR (for 8259A programmable Interrupt Controller.

106

* INT3 – INTA

*

* 4. Initialize the WDM register (SILC register 10).

* This is a 16 bit register and is stored in the 16 lsbs of memory location

16#003d6028#. Bit definitions are as follows:

* bit 0-4 - Unused. Initialize to zero.

* bit 5 - ? (initialized to zero).



* bit 8 - Unused. Initialize to zero.

* bit 9 - WDM strobe. (This would be set to 1 in iteration 0 interrupt).

* bit 10 - WDM resetHas to be set to 0 first and then to 1 (for simulating

edge sensitivesignal).

* bit 11-13- Major window length. set to 2#100# (15 milliseconds)

* bit 14,15- Minor window length. set to 2#01# (200 micro seconds)

*

* 5. Initialize 8254 timer.

* Load the control word with 16#30# to configure forbinary count,

read/write, mode 0, lsb, msb. program timer 0 for 100 micro seconds (initially)

* (This timer will be reprogrammed by iteration 0 timer ISR).

*

* 6. Initialize the 8259A (Programmable Interrupt Controller).

*

* After performing the above actions, initialization code issues RESTART - IAC

to bind the process to the processor, with new PRCB.

*

* The start up code follows:

*/

107

.globl start_ip

.globl Reset Processor

.text

.align 4

start_ip:

lda 0x200000, r4


ldconst 0x1FFFF, r3

fill r4, r5, r3 /* clear sram */

/* Copy Initial PRCB from ROM to RAM. Then load the processor Controls

wordswith Oxc i.e., to set processor to process execution mode. */

lda initPRCB, r3 /* load address of initPRCB */

lda NewPRCB, r4 /* load address of NewPRCB */

ldconst PRCB_LEN, r5 /* load PRCB length */

movstr r4, r3, r5 /* copy initPRCB to NewPRCB */

mov 0xC, r5 /* load processor Controls Word */

st r5, 4(r4) /* with 0xc */

lda New_int_table, r6

ldconst int_table_len, r8

lda 20(r4), r9

ld (r9), r7

movstr r6,r7,r8

st r6, 20(r4)

108

lda PCB, r3 /* load address of PCB */

lda NewPCB, r4 /* load address of New PCB */

ldconst PCB_LEN, r5 /* PCB lenrth */

movstr r4, r3, r5 /* copy PCB from ROM to New PCB in RAM */

lda 0x201000, r4


ldconst 0x1EFFF, r3

fill r4, r5, r3

lda 0x360000, r3 /* clear pending interrupt */

ldconst 0x1D, r4

st r4, (r3)

lda 0x360004, r3

ldconst 0xF3, r4

st r4, (r3)

lda 0x360004, r3

ldconst 0x1E, r4

st r4, (r3)

lda 0x360004, r3

ldconst 0xFF, r4

st r4, (r3)

lda 0x2003F0,r4


st r5, (r4)

lda inter_i960_mask, r3 /* Masking i960 interrupt*/

109

lda 0xFF000004, r4

synmov r4, r3

lda 0x2003F0,r4


st r5, (r4)

lda 0x320000, r3 /* set software fail reset */

ldconst 0x0100, r4

st r4, (r3)

lda 0x320000, r3

ldconst 0x0200, r4

st r4, (r3)

lda 0x2003F0,r4


st r5, (r4)

lda 0x3D6028, r3 /* set wdm reset */

ldconst 0x6000, r4

st r4, (r3)

lda 0x3D6028, r3

ldconst 0x6400, r4

st r4, (r3)

lda 0x3D6028, r3

ldconst 0x6000, r4

st r4, (r3)

110

lda 0x2003F0,r4


st r5, (r4)

lda set_i960_intr, r3 /* Initilization of interrupt in i960 */

lda 0xff000004, r4

synmov r4, r3

lda 0x2003F0,r4


st r5, (r4)

/* SILC control reg initlization */

lda 0x3D6000, r4

ldconst 0x0800, r5

stos r5, (r4)

lda 0x3D6004, r4

ldconst 0x0060, r5

stos r5, (r4)

lda 0x3D6008, r4

ldconst 0x0260, r5

stos r5, (r4)

lda 0x3D600C, r4

ldconst 0x0460, r5

111

stos r5, (r4)

lda 0x3D6010, r4

ldconst 0x0660, r5

stos r5, (r4)

lda 0x3D6044, r4

ldconst 0x0000, r5

stos r5, (r4)

lda 0x3D6014, r4

ldconst 0x41FF, r5

stos r5, (r4)

lda 0x3D6018, r4

ldconst 0x4000, r5

stos r5, (r4)

lda 0x3D601C, r4

ldconst 0x4210, r5

stos r5, (r4)

lda 0x3D602C, r4

ldconst 0x2005, r5

stos r5, (r4)

lda 0x3D6050, r4

ldconst 0x01FE, r5

112

stos r5, (r4)

lda 0x3D6054, r4

ldconst 0x000F, r5

stos r5, (r4)

lda 0x3D6058, r4

ldconst 0x0000, r5

stos r5, (r4)

lda 0x3D6020, r4

ldconst 0x5000, r5

stos r5, (r4)

lda 0x3D6024, r4

ldconst 0x5020, r5

stos r5, (r4)

/***************************************/

lda 0x2003F0,r4

ldconst 0x5a5a5a5a, r5

st r5, (r4)

ResetProcessor:

/*Set up the process stack*/

lda proc_stack, r3 /* ret the process stack address */

xor r4, r4, r4 /* clear r4 */

st r4, (r3) /* put at PFP of stack */

lda 0X40 (r3), r4

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st r4, 4 (r3) /* compute stack+64 */

lda Process, r4 /* put at SP of stack */

st r4, 8 (r3) /* put at RIP of stack */

lda 0x2003F4,r4

ldconst 0x5b5b5b5b, r5

st r5, (r4)

/* Set up miscellaneous things what else to setup !!! */

/*It is time for reseting the processor.*/

lda restart_iac, r3 /* Address of the restart messare */

lda 0xff000010, r4 /* IAC address */

synmovq r4, r3 /* restart processor */

lda 0x002003F8,r4

ldconst 0x5c5c5c5c, r5

st r5, (r4)

b segtable

restart_iac: /* Restart IAC message */

.word 0x81000000 /* IAC number 81 (restart) field 1 and 2

are not used */

.word 0 /* field 3 - new segment table */

.word NewPRCB /* field 4 - new PRCB */

.word 0 /* field 5 - not used */

inter_i960_mask:

.word 0x00000102

114

set_i960_intr:

.word 0xFF0074FF

3.3 Process.s ExplanationA register (210000) from the SRAM block is set aside to take the command.

115

When ‘1’ is written to the register, the microprocessor jumps to Process 1 and

executes the instructions in that process.

Similarly, when ‘2’ is written to the register, the microprocessor jumps to

Process2 and so on.

Process 1: SRAM Write

SRAM is accessed through i960 by writing the input data and the same is

verified by reading the output data through serial data link (Transputer).

First the command register is cleared, to prevent from infinite looping

into the same process.

Starting address from which read operation of the SRAM block needs to

be checked, is written at address- 210004

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Ending address till which read operation of the SRAM block needs to be

checked, is written at address- 210008

The data to be fused is written at 21000C

In the loop, the data is fused into the address (from the starting address to

the ending address) using “addi” and “cmpibne” instructions.

Process 2: SRAM Read

SRAM is accessed through i960 by writing, reading and comparing input

data. The result of compared values are written back to the same location

and verified through transputer.







117

Any data fused into the memory location between the address (specified

by the 210014 and 210018) is XOR-ed with “FFFFFFFF” and stored

back into the address. This is done using “xor”, “addi” and “cmpibne”

instructions.

Process 3: NVRAM Write

NVRAM memories are accessed through i960 for clearing the memory

locations by writing the input data and the same is verified by reading the

output data through transputer.



NVRAM is enabled by writing “004” at 320000(Local Discrete IO)





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The data to be fused is written at 21002C

In the loop, the data is fused into the address (from the starting address to

the ending address) using “addi” and “cmpibne” instructions.

Process 4: NVRAM Read

NVRAM is accessed through i960 by writing, reading and comparing the

input data. The results of compared values are written back to the same

location and verified through transputer.



NVRAM is enabled by writing “004” at 320000(Local Discrete IO)


be checked, is to be written at address- 210034



Any data fused into the memory location between the address (specified

by the 210014 and 210018) is XOR-ed with “FFFFFFFF” and stored

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back into the address. This is done using “xor”, “addi” and “cmpibne”

instructions.

Process 5: Timer – To read and store the counter value

Sets the required iteration control register through i960 by writing the

input data and the setting status is read and written to the output data and

the same is read through transputer.

First the command register is cleared, to

prevent from infinite looping into the same

process.

To select counter 0 of the Timer in Mode 2,

write “0x34” at 34000C (Timer control

register).

Now write the count value at

340000(Counter 0 Count Register), first

LSB then MSB.

Now the timer control register is set to

select Read back Command so as to read

the count value. This is done by writing

“0xD2” at 34000C.

Fig6 – Read Back Command Format Fig 7 -Control Word Format

In the loop, the count value is read and adjusted using “shli” ,”addi”,

“and”, “or”, and “compibne” instructions.

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Process 6: To generate a square wave using Timer



The count value is to be written at – 21005C

To select counter 1 of the Timer in Mode 3, write “0x76” at 34000C

(Timer control register).

This is stored as LSB First and then MSB at 340004 (Counter1 Register)

The square wave is viewed in the Logic analyzer.

Process 7: To transmit and

receive serially through UART

First the command register is

cleared, to prevent from

infinite looping into the same

process.

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UART is enabled by writing “80” at 320000(Local Discrete IO)

UART Control Register is set to have 1 stop bit, odd Tx and Rx and 8 bit

word-length . This is done by writing “0x32” at 0x3D8004, 0x3D8014,

0x3D8024 … 0x3D8084 (UCR’s of all the Transmitters and Receivers )

Fig 8 –UART Control Register

Baud Rate Select Register is set so as to get a Prescalar of 1. This is

done by writing “0x7C” at 0x3D800C, 0x3D801C, 0x3D802C …

0x3D808C (BRSR’s of all the Transmitters and Receivers )

Fig 9 –Baud Rate Select Register

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Modem Control Register is set

to enable receiver, enable

interrupt and work in the normal

mode. This is done by writing

“0x24” at 0x3D8008,

0x3D8018, 0x3D8028 …

0x3D8088 (MCR’s of all the

Transmitters and Receivers )

Data is transmitted through the

transmitters by writing it to the

transmit buffer registers

(3D8060, 3D8070, 3D8080) and

received at the receiver. This s

received at (3D8020, 3D8040,

3D8060 resp.) Fig10–Modem Control Register

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Fig11 – Pin Connections from Tx to Rx for UART

Process 8: CCDL Communication Test



Starting addresses for different buffer RAMs are put into the specific

control registers.

Fig12 -CCDL Interface Memory Map

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Table 1 - CCDL Interface Signals

Clearing the CCDL stack counter level, setting its value and then clearing

it again.

We are taking the data specified by the user from the SRAM (transmitting

to SRAM) which will be received by different channels.

Enable the CCDL transmitter

Table 2 – CCDL- DFCC Channels Cross Reference

Table 3-Control Register 0 Definition

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Starting Address:

Indicates CCDL Transmitter RAM starting address as viewed by the system

Bus, programmable in 256 word boundaries.

Table 4 -Reciever Initialization Control Register Definition

Starting Address:

Indicates CCDL Transmitter RAM starting address as viewed by the system Bus, programmable in 256 word boundaries.

Bit Rate:

Programmable receiver bit rates.

RCVR Depth:

Programmable receiver buffer RAM depth/label length.

Fig13 – Pin Connections from Tx to Rx for CCDL

126

127

128

129

130

131

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CHAPTER 4

ADVANTAGES AND APPLICATIONS OF DFCC

4.1 AdvantagesThe advantages of FBW controls were first exploited by the military and then in

the commercial airline market.

AUTOMATIC STABILITY SYSTEMS

Fly-by-wire control systems allow aircraft computers to perform tasks without

pilot input. Automatic stability systems operate in this way. Gyroscopes fitted

with sensors are mounted in an aircraft to sense movement changes in the pitch,

roll and yaw axes. Any movement results in signals to the computer, which

automatically moves control actuators to stabilize the aircraft.

SAFETY AND REDUNDANCY

Aircraft systems may be quadruplexed (four independent channels) to prevent

loss of signals in the case of failure of one or even two channels. High

performance aircraft that have FBW controls (also called CCVs or Control-

Configured Vehicles) may be deliberately designed to have low or even

negative stability in some flight regimes, the rapid-reacting CCV controls

compensating for the lack of natural stability.

WEIGHT SAVING

A FBW aircraft can be lighter than a similar design with conventional controls.

Partly due to the lower overall weight of the system components; and partly

because the natural stability of the aircraft can be relaxed, slightly for a

133

http://en.wikipedia.org/wiki/Flight_dynamics_(aircraft)

http://en.wikipedia.org/wiki/Flight_dynamics_(aircraft)

http://en.wikipedia.org/wiki/Sensor

http://en.wikipedia.org/wiki/Gyroscope

transport aircraft and more for a manoeuvrable fighter, which means that the

stability surfaces that are part of the aircraft structure can therefore be made

smaller. These include the vertical and horizontal stabilizers (fin and tailplane)

that are (normally) at the rear of the fuselage. If these structures can be reduced

in size, airframe weight is reduced.

Electronic fly-by-wire systems can respond flexibly to changing aerodynamic

conditions, by tailoring flight control surface movements so that aircraft

response to control inputs is appropriate to flight conditions. Electronic systems

require less maintenance, whereas mechanical and hydraulic systems require

lubrication, tension adjustments, leak checks, fluid changes, etc.

Furthermore, putting circuitry between pilot and aircraft can enhance safety;

for example the control system can try to prevent a stall, or it can stop the pilot

from over stressing the airframe.

The main concern with fly-by-wire systems is reliability. While traditional

mechanical or hydraulic control systems usually fail gradually, the loss of all

flight control computers could immediately render the aircraft uncontrollable.

For this reason, most fly-by-wire systems incorporate either redundant

computers (triplex, quadruplex etc.), some kind of mechanical or hydraulic

backup or a combination of both.

134

http://en.wikipedia.org/wiki/Flight_control_surfaces

http://en.wikipedia.org/wiki/Fuselage

4.2 ApplicationsADC has been developed newly for the LCA to augment the DFCC.

ADC takes input from:

1. AoA Vane Sensor

2. Nose Air Data Probe

3. Acceleration Sensor

4. Total Air Temperature Probe

5. Side Air Data Probe

6. Rate Sensor

And DFCC performs functions according to the output given by ADC, which

are stated below:

1. Rudder Deflection

2. Elevon Deflection

3. Leading Edge Slat Deflection

4. Airbrake

5. De-icing

De-icing Current Sensing Unit

Mother Earth is surrounded by atmosphere. The atmosphere is held close to the

earth by gravitation. As one ascends the altitude away from the earth the

gravitation force decreases. As a result the density of the atmosphere decreases.

The effect is that as the gravitation force, which holds the molecules of the air

together decreases with altitude, the molecules of the air suddenly are free,

which results in adiabatic expansion and fall in temperature. Since the density

of the atmosphere is low at high altitude compared to the density on the surface

of the earth, the kinematic heating due to collision, friction of molecules as a

result of the random movement is low at high altitude. This also contributes to

135

fall in temperature at high altitude. Since the density of the atmosphere is low at

high altitude compared to the density on the surface of the pressure also is low

at high altitude compared to low altitude.

When the aircraft flies at high altitude where the outside temperature is subzero,

ice will form all over the body as well as cover the monitoring points of the air

data probes which are detrimental for both men and machinery.

Hence for safety of operation, the air data probes are provided with passive

resistor heaters to provide anti-icing as well as de-icing of the sensing ports of

the probes.

DCSU is a part quadruplex Digital Flight Control System. It is used in

monitoring the heater currents of the air data probes and sensors (vanes/case).

This is interfaced to the heatres of the probes/sensors on the primary side and to

the ADC on the secondary side. The DCSU is installed in the real cabin of the

LCA.

LCA has three pitot-static probes (two mounted on the sides and one mounted

on the nose of the aircraft) and one probe to capture the total air temperature.

The four air data probes have passive resistive heater coil for de-icing. In

addition to the probes there are two vane sensors mounted on either side to

measure the AoA and one vane sensor mounted on the ventral fuselage of

aircraft to measure the angle of sideslip. These sensors have two heater coils,

one for vane and the other for the case. All the heaters are powered by the 400

Hz, 115 Volts aircraft electric power. The DCSU monitors the health of heater

elements.

DFCC Interface Unit

Digital Flight Control computer interface unit (DIU) is part of quadruplex

digital Flight Control System for TWO seated LCA Trainer. It receives discrete

136

inputs from the two cockpits and connects them to digital flight Control

Computer (DFCC). This is a passive unit, which performs wired ‘OR’ functions

(Simplex/Duplex/Quadruplex) for the discrete signals received from both

cockpits and feeds to DFCC as single discrete signal input. The discrete outputs

from DFCC Digital card based on the inputs from both cockpits in normal

operating conditions and the failure conditions is handled in DFCC Digital

cardsoftware the applicable interfaces are Control Stick Discrete, Auto Pilot

Panel ,Central Warning Panel and Main Instrument Panel.

137

CHAPTER 5

CONCLUSIONIn this project we have developed the codes for some of the components of

DFCC Digital card like SRAM, NVRAM, TIMER, UART, CCDL. Application

of codes developed is that these cases are being used to detect the fault in the

components of DFCC Digital cards.

Same things can be implemented for the other units also.

From the detailed study of this report, we get to know about:

The primary goal of this report is to identify action initiatives that……..

To conclude with the words of one faculty member interviewed for the Project:

"Don't let this Millennium Project sit in a big folder and not be acted upon!"

138

APPENDICESAPPENDIX A: Instruction Set

ReferenceIn this section we have added those instructions which we have used for

building the OFP code for our project.

1) addi

Mnemonic: addi Add Integer

Format: addi src1, src2, dstreg/lit, reg/lit, reg

Description: Adds the src2 and src1 values and stores the result in dst.

Action: dst ← src2 +src1

Example: addi r4, g5, r9 #r9 ← g5+ r4

2) and

Mnemonic: and And

Format: and src1, src2, dstreg/lit, reg/lit, reg

Description: Performs a bitwise AND operation on the src2 and src1

value and stores the result in destination.

Action: dst ← src2 and src1

Example: and g9, g12, g9 # g9 ← g9 and g12

3) b

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Mnemonic: b Branch

Format: b target

Description: Branches to the instruction specified with target operand.

Action: IP← IP + displacement; # resume execution at the new IP

Example: b xyz #IP ←xyz

4) cmpibe

Mnemonic: cmpibe Compare Integer and Branch If Equal

Format: cmpibe src1, src2, targreg/lit reg

Description: Compares the src2 and src1 values and sets the condition

code according to the results of the comparison. If the

logical AND of the condition code and the mask-part of the

opcode is zero, the processor branches to the instruction

specified with the target operand; otherwise the processor

goes to the next instruction.

Example: cmpibe g4, g5, loop1 # Compare g4 & g5, ifequal goto

loop1 and IP← loop1

5) cmpibne

Mnemonic: cmpibne Compare Integer and Branch If Not Equal

Format: cmpibne src1, src2, targreg/lit reg

Description: Compares the src2 and src1 values and sets the condition

code according to the results of the comparison. If the

logical AND of the condition code and the mask-part of the

opcode is not zero, the processor branches to the instruction

140

specified with the target operand; otherwise the processor

goes to the next instruction.

Example: cmpibne g4, g5, loop1 # Compare g4 & g5, if not equal

goto loop1 and IP← loop1

6) ld

Mnemonics: ld Load

Format: ld src dstmem reg

Description: Copies a byte or string of bytes from memory into a register

or group of successive registers. The src operand specifies

the address of the first byte to be loaded.

Action: dst ← memory (src)

Example: ld (g7),g6 # g6 ← (g7)

7) lda

Mnemonic: lda Load address

Format: lda src dst

mem reg

Description: Compute the effective address specified with src and stores

it in dst. The src address is not checked for validity.

Action: dst ← add/(src)

Example: lda 0x21000C,g7 # loads the address‘21000C in g7

8) ldconst

Mnemonic: ldconst Load constant

Format: ldconst src dst

141

mem reg

Description: Loads a constant from src into dst. The src address is not

checked for validity.An important application of this

instruction is to load a constant longer than 5 bits into a

register.

Action: dst ← src(const value)

Example: ldconst 0x4,g8 # loads the constant‘4’ in g8

9) movstr

Mnemonic: movstr Move string

Format: movstr dst, src, lenreg reg reg/litaddr addr

Description: Copies a string of bytes from one location in memory to

another. The src operand specifies the address of the first

byte of the source string and the dst operand specifies the

address of the first byte of the destination string.

Example: movstr g5, g1, g9 # Copies string which is g9 bytes

long and begins at address g1, to

address g5

10)or

Mnemonic: or Or

Format: or src1, src2, dstreg/lit, reg/lit, reg

Description: Performs a bitwise OR operation on the src2 and src1 value

and stores the result in destination.

142

Action: dst ← src2 or src1

Example: or g9, g12, g9 # g9 ← g9 or g12

11) shli

Mnemonic: shli Shift Left

Format: shli len, src, dst

Reg/lit Reg/lit Reg

Description: Shifts src left by the number of digits indicated with the len

operand and stores the result in dst. Bits shifted beyond the

register boundary are discarded. For values of len greater

than 32, the processor interprets the value as 32.

Example: shli 8,g5,g6 # g6← g5 shifted left 8 bits

12) shri

Mnemonic: shri Shift Right

Format: shri len, src, dstreg/lit reg/lit reg

Description: Shifts src right by the number of digits indicated with the len

operand and stores the result in dst. Bits shifted beyond the

register boundary are discarded. For values of len greater

than 32, the processor interprets the value as 32.

13)st

Mnemonic: st Store

Format: st src, dstreg/lit mem

143

Description: Copies a byte or string of bytes from register or group of

registers to memory. The src operand specifies a register or

the first(lowest numbered) register of successive registers.

Action: memory (dst) ← src;

Example: st g8,(g7) # stores the value from g8 into the

address pointed by g7

14)stos

Mnemonic: stos Store Ordinal Short

Format: stos src, dstReg/lit mem

Description: Stores a half word (16 bits) from register to memory from

the low order bytes of the src register.

Action: memory (dst) ← src;

Example: stos g11, (g10) # g11 ← (g10)

15)xor

Mnemonic: xor Exclusive Or

Format: xor src1, src2, dstreg/lit reg/lit reg

Description: Performs a bitwise XORoperation on the src2 and src1

values and stores the result in dst.

Example: xor g13, g7, g4 # g4← g7 xor g13

Example: shri 13, g4, g6 # g6 ← g4 shifted right 13 bits

144

APPENDIX B: Assembler Directives

.align

Function: Align Location Counter

Format: .align align_expr

Description: This directive increments the location counter to the multiple

of . align_expr specifies an absolute, defined, non-

negative expression whose value is less than or equal to 16.

The skipped bytes are filled with zeros.

.align provides the boundary alignment required by the

processor for data accessed by single-, double-, triple-, and

quad-register operations.

Examples: # , , .align 2 .align 3 .align 4

.globl

Function: Declare Global Symbol

Format: .globl name

Description: .globl marks name as an externally visible symbol. This

allows combination of the object module with other modules

that use name, whether defined in the current assembly or

not. All undefined symbols are marked external.

Examples: .globl _strncmp

.set

Function: Set Temporary Symbol

145

Format: .set name, data_expr

Description: This directive defines name as a temporary symbol.

data_expr specifies the value of the symbol and must be a

constant expression. The symbol designated by name is

written to the object file as an absolute symbol. If more than

one value is assigned to the symbol, the value is the last

value assigned.

Examples: .set PI, 0f3.14159

.set TWO_PI, 2 * PI

.set Four_K, 4 * 1024

.text

Function: Switch to .text Section

Format: .text

Description: This directive sets the location counter to the .text section of

the program. No assumptions are made about this section's

contents.

Assembly begins with this section. If no sections are

explicitly declared, a single default section of .text is placed

in the object file. All program text is placed in the linker's

output object file.

.word

Function: Assemble Word Data

Format: .word data_expr [, data_expr] ...

Description: The .word directive stores the value of data_expr in

successive word (32-bit) locations, beginning at the current

location counter. Each value of data_expr is truncated to 32

bits.

146

When the optional format int_expr:data_expr is used, the

assembler first truncates the value to int_expr bits and then

stores the result in the next word location, truncating again if

necessary. Unused bits are set to zero.

Examples: .word 372

.word 7:672

.space

Function: Fill a Memory Block with Zeros

Format: .space size_expr

Description: The .space directive fills size_expr bytes with zeros,

beginning with the current location counter.

If one defines a segment with the attributes RW, then the

only way to give space to the segment is with a combination

of .space directives and .align directives. One may also use

the .seg directive to switch to the .bss segment and treat it as

any other RW segment. A segment with RW attributes only

is not initialized; the I attribute must be specified to create an

initialized segment.

Examples: .space 0xF

147

APPENDIX C: IC’s Used

82C52 –UARTBlock Diagram

Pin Discription

148

The Intersil 82C52 is a high performance programmable UART and BRG on a single chip.

82C54 – TimerThe 82C54 is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in system software.

System Interface:

The 82C54 is treated by the system software as an array of peripheral I/O ports; 3 are counters and 4th is a control register for MODE programming.

Basically, the select inputs A0,A1 connect to the A2,A3 address bus signal of the i960. The chip select can be derived directly from the address bus using a linear select mode or it can be connected to the output of the decoder.

149

82C59 – Interrupt Controller82C59 is a high performance CMOS priority Interrupt Controller. The PICfunctions as an overall manager in an interrupt driven system. IT accepts requests from the peripheral equipments, determines which of the incoming request is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination

150

ABBREVIATIONSADA - Aeronautical Development Agency

ADC – Air Data Computer

ADE – Aeronautical Development Establishment

ADT – Air Data Transducer

AIRDATS – Air Data Computer Test System

AoA – Angle of Attack

ASA – Acceleration Sensor Assembly

ASIC – Application Specific Integrated Circuit

ATE – Automatic Test Equipment

ATP – Acceptance Test Procedure

ATS – Actuator Test Set

BRG – Baud Rate Generator

CCDL – Cross Channel Data Link

CDR – Crash Data Recorder

CMOS – ComplementaryMetal Oxide Semiconductor

cPCI – compact Peripheral Component Interconnect

DBU – Digital Backup Unit

DCSU – De-icing Current Sensing Unit

DDT – Development Design & Test

DDV – Direct Drive Value

DFCC – Digital Flight Control Computer

DMA – Direct Memory Access

DoD – Department of Defence

EEPROM – Electrically Erasable Programmable Read Only Memory

EHSV – Electro Hydraulic Servo Valve

ESS – Environment Stress Screening

151

ETS – Engineering Test Station

EW&A – Electronic Warfare & Avionics

FBW – Fly-By-Wire

FCS – Flight Control System

FTP – Flight Test Panel

GUH – Get U Home

GUI – Graphical User Interface

HSI – Hardware/Software Integration

LCA – Light Combat Aircraft

LRU – Line Replaceable Unit

LVDT – Linear Variable Differential Transducer

MIL STD – Military Standards

NAL - National Aeronautics Laboratory

NVRAM – Non Volatile Random Access Memory

OFP – Operational Flight Programme

PIC – Programmable Interrupt Controller

PIO – Pilot Induced Oscillation

PMC –

PSU – Power Supply Unit

RISC – Reduced Instruction Set Computer

RSA – Rate Sensor Assembly

RTD – Resistance Temperature Detector

RVDT – Resistive Variable Differential Transformer

SILC – Serial Interface Logic Controller

SPIL – Serial Processor Interface Link

SRAM – Static Random Access Memory

SRU – Shop Replaceable Unit

TTL – Transistor Transistor Logic

152

http://en.wikipedia.org/wiki/Pilot-induced_oscillation

UART – Universal Asynchronous Receiver/Transmitter

WDM – Watch Dog Monitor

153

REFERENCES

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Documents

Project Final Dfcc