AI & NK, 10/31/2014 1

Project #2: Design of an Operational

Amplifier

By:

Adrian Ildefonso

Nedeljko Karaulac

I have neither given nor received any unauthorized assistance on this project.

Process: Baker’s 50nm

CAD Tool: Cadence Virtuoso

AI & NK, 10/31/2014 2

Topology Selection: Input

• Input topology decided by ICMR

(0.2–1V) for a supply voltage of 1.2V

• Use folded cascode topology for

high input swing

• PMOS folded cascode (shown in

figure):

– Vin,min = VOVN – VTHP – VSS = -210mV

– Vin,max = VDD – 2VOVP – VTHN = 780mV

• NMOS version would have the same

limitation on the minimum input

voltage

Solution: Use parallel NMOS and PMOS folded cascode

differential pair for the input stage.

Paul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog

Integrated Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.

AI & NK, 10/31/2014 3

Topology Selection: Output

• Output topology decided by output

swing (0.2–1V)

• Low output resistance is desirable

• Class AB Source follower buffer

(shown in Figure)

– Vout,min = 2VOV + VTHP – VSS = 420mV

– Vin,max = VDD – 2VOV – VTHN = 780mV

• Must use class AB Push-Pull

amplifier, which will also be a

second gain stagePaul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog

Integrated Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.

MG1

AI & NK, 10/31/2014

• Selected Topology:

– Input: Parallel NMOS and PMOS Folded Cascode

– Output/Second Stage: Push-Pull Amplifier

• Benefits

– Rail to Rail input

– High Swing output

– Higher Gain

• Drawbacks

– Gain is not constant across input range (not an issue due to high

open loop gain)

– Gain highly dependent on resistive load

– Added power consumption due to parallel differential amplifier

4

Selected Topology

AI & NK, 10/31/2014

• For SR of 120V/us

– IT = SR*CL = 120 uA

• Current in cascode branch is 1.2 – 1.5 times the tail current

• For parallel differential pairs (required to meet ICMR), we

need more than, which is over the required power

• After literature review, no circuit was found (in research or

industry) that meets all the criteria for this project.

• We decided to sacrifice SR and BW in order to save power

• Tail current chosen: 40 uA

• This means that our SR should be around 40 V/us

5

DesignMG2

AI & NK, 10/31/2014 6

Design

• Because we are no longer concerned with ICMR, we can

choose any overdrive voltage for the input differential pair.

• Let’s choose 50mV to obtain higher gm.

• This would require W/L of NMOS input pairs to be around

150/2 = 7.5u/100n and PMOS to be 300/2 = 15u/100n

• Cascode transistors were chosen to conduct 1.3 times

current in one side of the differential pair to prevent them

from turning on.

AI & NK, 10/31/2014

• Output stage is a push pull amplifier, sized to conduct 20uA

• Cascode device was added to increase output resistance

and gain

• Compensation capacitor was added before the cascode

device to use the cascode as a buffer

– This helped greatly with the frequency response of the amplifier but

did not remove the RHPZ

– Resulted in bigger compensation capacitor because now the miller

capacitance is in series with the CDS of the cascode device,

reducing the effective capacitance

– Zero nulling resistor was added to remove RHPZ

7

Design

AI & NK, 10/31/2014

Reference Schematic

8

Used topology in Baker’s Figure 20.47

Resistor value changed to obtain

desired currents

AI & NK, 10/31/2014

Amplifier Schematic

9

Complementary Folded

Cascode Differential PairPush/Pull Output Stage

Note these devices are 1.3 time the size of

the tail current sources. Also true for

NMOS at the bottom

Note cascode output to

increase gain and output

resistance. This requires

complementary

compensation as shown

Cascode tail currents to

increase CMRR

MG3

AI & NK, 10/31/2014

Simulation Test benches

10

Buffer configuration

ICMR: DC sweep from -0.2 to 1.4

SR: Step from 0.1 to 1.1 V

THD: 1kHz Sine wave covering full output swing

Non-inverting Amplifier

Output Swing: Sweep input from -0.2 to 1.4

and see where output saturates

Inductor in feedback

Open Loop Gain: Frequency sweep at input

ACM: Frequency sweep with shorted inputs

AC sources on supply

PSRR: Sweep frequency at VDD and GND.iprobe in feedback

Noise: Perform noise analysis on Cadence

Note: Infinitely large inductor is used

to act as a short in DC but open in

AC. It allows for Cadence to

calculate the DC operating point

correctly. Note: iprobe acts as a short in

DC but open in AC. This is the

same as using an infinitely large

inductor, and the same

simulation values were obtained.

Inductor was used in Open Loop

Gain because it was easier to

simulate CMRR.

MG4MG5

AI & NK, 10/31/2014 11

Open Loop Response

20.0

80.0

60.0

40.0

Open

Loop G

ain

(d

B)

100

-100

-80.0

-60.0

-40.0

-20.0

0.0

Ph

ase

(d

eg)

-180.0

-225.0

-270.0

-135.0

-360.0

-315.0

-45.0

-90.0

180.0

135.0

0.0

45.0

90.0

NamVis3d

Frequency (Hz)10

110

010

210

410

310

510

610

710

810

910

10

35.4858udB

45.86191deg

Unity Gain

179.9968deg

80.22635dB

DC Gain

134.8967deg

77.22662dB

3dB Frequency

AI & NK, 10/31/2014

Input and Output Swing

12

Min Input: (55.929347mV, 990.0m)

Max Input: (1.1597325V, 990.0m)

.75

0.0

.25

.5

Vou

t (B

uff

er)

(V

)

1.25

-.25

1.0

.5

dV

ou

t/d

Vin

0.0

.25

1.25

.75

1.0

-.25

Max Output: 1.0756326V

Min Output: 58.881285mV

7.5

-2.5

2.5

dV

ou

t/d

Vin

12.5

5.0

0.0

10.0

-.25

.25

1.25

1.0

.5

0.0

.75

Vo

ut

(Non

-In

vert

ing A

mp

lifi

er,

A =

10

) (V

)

1.0 1.25 1.5

Vin (V)

-.25 0.0 .25 .5 .75

AI & NK, 10/31/2014

Transient Response

13

M1: 1.0202096us 1.0V

M6: 1.1595978us 1.0985998V

M2: 1.0024586us 199.78604mV

M4: 1.5279524us 200.41284mV

M3: 1.5042119us 1.0001732V

M5: 1.6098323us 100.21264m

1.0

Vo

ltag

e (

V)

.25

.5

.75

1.7

Time (us)

1.4 1.5 1.61.0 1.1 1.2 1.3

AI & NK, 10/31/2014

PSRR

14

-30.0

-40.0

-50.0

-10.0

-20.0

PS

RR

- G

ND

(d

B)

-20.0

PS

RR

- V

DD

(d

B)

-70.0

-60.0

-50.0

-40.0

-30.0

freq (Hz)10

010

110

210

310

410

510

610

710

810

910

10

-21.762635dB

-64.79598dB

V1

AI & NK, 10/31/2014

Noise

15

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Spec Summary

Spec Target Achieved

Differential amplifier topology N/AParallel Folded

Cascode

Reference topology N/A Baker 50 nm

Supply (V) 1.2 1.2

Loading (pF || kOhm) 1 || 100 1 || 100

Differential Gain (dB) 80 80.23

CMRR (dB) 120 94.76

ICMR (V) 0.2 - 1 56m – 1.16

Output Swing (V) 0.1- 1.1 59m – 1.08

Bandwidth - 3dB (kHz) (Loaded/Unloaded) 100 18.47 / 1.69

Gainbandwidth product (MHz) N/A 76.4

Compensation capacitor (pF) N/A See schematic

Phase margin (degrees) 45 45.86

Gain of differential amplifier (dB) N/A 47.7

Max Power consumption (uW) (Loaded/Unloaded) (Buffer Configuration) 200 178.4 / 173.5

Reference power consumption (uW) N/A 93.4

OpAmp power consumption with zero input (uW) (Buffer Configuration) N/A 178.4

Total power consumption (uW) N/A 271.8

Slew Rate (V/us) (Positive/Negative) 120 / -120 40 / -34.7

MG6

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Spec Summary Cont’d

Spec Target Achieved

Supply Voltage (V) (Maximum/Minimum) N/A 0.55 / 3.06

Nominal output voltage (V) N/A 0.6

Input offset voltage (mV) N/A -12

Rise/Fall time (ns) (to 90% of final value) N/A 20 / 23

Settling time (ns) (Rising / Falling Edge) N/A 160 / 109

RMS Input referred noise (V) (1 Hz – 100MHz) (Simulated in open loop) N/A 7.51 n

THD for full swing output (%) (Simulated in Buffer mode) N/A 1.165 %

AI & NK, 10/31/2014

• To improve CMRR, make tail current sources longer to increase RTail

• To improve SR, increase tail current and current at output stage.

• Ideally a buffer should be used for the output, but implementation of

high-swing low impedance buffer is difficult. Using a buffer would make

gain and bandwidth independent of loading

• Use advanced compensation techniques, such as those shown in the

references, to reduce capacitor size and increase phase margin

• Better match currents in PMOS and NMOS differential pairs to reduce

offset voltage. This can be done by selecting a different overdrive

voltage for the input devices so that the tail current sources have a VDS

that results in better current matching. Constant gm amplifier might

also reduce this offset.

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How to improve design?

MG7

AI & NK, 10/31/2014

• Completed design of two stage operational amplifier

• Opted for low power operation instead of high speed (SR

and Bandwidth)

• Parallel input differential pairs were necessary to meet

ICMR requirements

• Push pull amplifier was needed to meet output swing

requirements. Cascode devices were added to increase the

gain and output resistance. However, buffer should be used

for the output

• Design could be improved with relaxed power

specifications

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Conclusion

AI & NK, 10/31/2014

• R. Jacob Baker. 2010. CMOS Circuit Design, Layout, and Simulation (3rd ed.). Wiley-IEEE Press.

• Paul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog Integrated Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.

• Grasso, A.D.; Palumbo, G.; Pennisi, S., "Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.55, no.11, pp.1099,1103, Nov. 2008

• http://www.eit.uni-kl.de/koenig/deutsch/TESYS_Lutgen_09.pdf

• http://www.ece.tamu.edu/~spalermo/ecen474/lecture14_ee474_folded_cascode_ota.pdf

• http://www.ijser.org/researchpaper%5CDESIGN-OF-HIGH-GAIN-FOLDED-CASCODE-OPERATIONAL-AMPLIFIER-USING-1.25-M-CMOS-TECHNOLOGY.pdf

• http://www.aicdesign.org/SCNOTES/2010notes/Lect2UP250_%28100328%29.pdf

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References