Programmable Logic Programmable Logic Devices (PLDs)Devices (PLDs)

Wannachai wannasaeadeWannachai wannasaeadeDepartment of Computer EducationDepartment of Computer EducationKMUTNB.KMUTNB.

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OverviewOverview

Three-State BuffersThree-State Buffers Programmable Logic TechnologiesProgrammable Logic Technologies

– Read-Only Memory (ROM)Read-Only Memory (ROM)– Simple Programmable Logic DeviceSimple Programmable Logic Device

Programmable Logic Arrays (PLA)Programmable Logic Arrays (PLA) Programmable Array Logic (PAL)Programmable Array Logic (PAL) Gate Array Logic (GAL)Gate Array Logic (GAL)

– Complex Programmable Logic (CPLD)Complex Programmable Logic (CPLD)– Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)

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Three-State BuffersThree-State Buffers

Buffer output has 3 states: 0, 1, ZBuffer output has 3 states: 0, 1, Z Z stands for High-Impedance Z stands for High-Impedance

Open circuitOpen circuit

EN = 0 EN = 0 out = Z (open circuit) out = Z (open circuit)

EN = 1 EN = 1 out = in (regular buffer) out = in (regular buffer)

in out

EN ENEN inin outout

00 XX ZZ

11 00 00

11 11 11

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Three-state Three-state buffer(BUF)/inverter(INV) buffer(BUF)/inverter(INV)

symbolssymbols

in out

EN

in out

EN

in out

EN

in out

EN

3-state BUF, EN high

3-state BUF, EN low 3-state INV, EN low

3-state INV, EN high

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Multiplexed output lines using Multiplexed output lines using three-state buffersthree-state buffers

Assume an output line that can receive Assume an output line that can receive data from either a system (circuit) A or a data from either a system (circuit) A or a system B.system B.

A

B

out

wiredlogic

If A = B out = A = BIf A B a large enough current can be created, that causes excessive heating and could damage the circuit.

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Multiplexed output lines Multiplexed output lines using three-state buffers using three-state buffers (cont.)(cont.)

Solution:Solution:

A

B

out

ENA

ENB

S

SS AA BB ENEN

AA

ENEN

BB

outout

00 00 00 11 00 00

00 00 11 11 00 00

00 11 00 11 00 11

00 11 11 11 00 11

11 00 00 00 11 00

11 00 11 00 11 11

11 11 00 00 11 00

11 11 11 00 11 11

A

B

A

B

S

out0

1

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Programmable Logic Programmable Logic Devices (PLDs)Devices (PLDs)

StandardStandard logic devices that can logic devices that can be be programmed programmed to implement to implement any combinational logic circuit.any combinational logic circuit.

Standard Standard of regular structure of regular structure Programmed Programmed refers to a refers to a

hardware process used to specify hardware process used to specify the logic that a PLD implementsthe logic that a PLD implements

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Gate SymbolsGate Symbols

...

Conventional AND gate symbol

...

Array Logic AND gate symbol

One major difference!

abc

F

F = a.b.c

a b cF = 0

F = a.c

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Read-Only Memory Read-Only Memory (ROM)(ROM)

Stores binary information permanently Stores binary information permanently Non-Volatile (info is kept even when Non-Volatile (info is kept even when

power is turned off)power is turned off)

k inputs = specify the # of k inputs = specify the # of addresses availableaddresses available

n outputs = n outputs = specify the size of specify the size of data data

ROM2k x nk n

Block Diagram

1010

Read-Only Memory Read-Only Memory (cont.)(cont.)

Example: k=3, Example: k=3, n=4n=4

There are 2There are 233=8 =8 available available addressesaddresses

4-bits are stored 4-bits are stored in each addressin each address

00

11

22

33

44

55

66

77

Address

3 4

8x4 ROM

1111

ROM construction: ROM construction: Example of an 2Example of an 255x8 x8 ROMROM Use a 5-to-32 decoder to generate the 32 addresses.Use a 5-to-32 decoder to generate the 32 addresses. Use 8 OR gates, each can be programmed to be Use 8 OR gates, each can be programmed to be

driven by any of the decoder outputs.driven by any of the decoder outputs.

Programmablelogic. # of interconnectionsis 2255x8x8

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Programming the ROM, i.e. Programming the ROM, i.e. load desired data at specified load desired data at specified addressesaddresses

ROM addresses ROM data

Address(in decimal)

0123

28293031

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Programming the ROM Programming the ROM (cont.)(cont.)

Example: Let I0I1I3I4 = 00010 (address 2). Then, output 2 of thedecoder will be 1, the remaining outputs will be 0, and ROM outputbecomes A7A6A5A4A3A2A1A0 = 11000101.

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ROM-based circuit ROM-based circuit implementationimplementation

Given a 2Given a 2kkxn ROM, we can implement xn ROM, we can implement ANY combinational circuit with ANY combinational circuit with at at mostmost k inputs and k inputs and at mostat most n outputs. n outputs.

Why?Why?– k-to-2k-to-2k k decoder will generate all 2decoder will generate all 2k k

possible mintermspossible minterms– Each of the OR gates must implement a Each of the OR gates must implement a

m()m()

– Each Each m() can be programmedm() can be programmed

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ExampleExample

Find a ROM-based circuit Find a ROM-based circuit implementation for:implementation for:– f(a,b,c) = a’b’ + abcf(a,b,c) = a’b’ + abc– g(a,b,c) = a’b’c’ + ab + bcg(a,b,c) = a’b’c’ + ab + bc– h(a,b,c) = a’b’ + ch(a,b,c) = a’b’ + c

Solution:Solution:– Express f(), g(), and h() in Express f(), g(), and h() in m()m() format (use format (use

truth tables)truth tables)– Program the ROM based on the 3 Program the ROM based on the 3 m()’sm()’s

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Example (cont.)Example (cont.) There are 3 inputs and 3 outputs, thus we need a There are 3 inputs and 3 outputs, thus we need a

8x3 ROM block.8x3 ROM block. f = f = m(0, 1, 7)m(0, 1, 7) g = g = m(0, 3, 6, 7)m(0, 3, 6, 7) h = h = m(0, 1, 3, 5, 7)m(0, 1, 3, 5, 7)

3-to-8decoder

01234567

a

b

c

f g h

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Programmable Logic Programmable Logic Arrays (PLA)Arrays (PLA)

Similar concept as in ROM, except Similar concept as in ROM, except that a PLA does not necessarily that a PLA does not necessarily generate all possible minterms (ie. generate all possible minterms (ie. the decoder is not used).the decoder is not used).

More precisely, in PLAs both the AND More precisely, in PLAs both the AND and OR arrays can be programmed and OR arrays can be programmed (in ROM, the AND array is fixed – the (in ROM, the AND array is fixed – the decoder – and only the OR array can decoder – and only the OR array can be programmed).be programmed).

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Programmable Logic Arrays Programmable Logic Arrays (PLA)(PLA)

A PLA consists of wide input programmable AND gates followedby a programmable OR gate plane.

The routing architecture in a PLA is simple where every output is connected to every input through one switch. The switches are organized into crossbar-like structures.

As such, PLAs are suitable for implementing logic in two-level sum-of-products form.

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ProgrammablProgrammable e Logic Arrays Logic Arrays (PLA)(PLA)

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PLA ExamplePLA Example

AND array

OR array

• f(a,b,c) = a’b’ + abc• g(a,b,c) = a’b’c’ + ab + bc• h(a,b,c) = c

PLAs can be more compactimplementations than ROMs,since they can benefit fromminimizing the numberof products required toimplement a function

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Another PLA ExampleAnother PLA Example

Find a PLA-based circuit Find a PLA-based circuit implementation for:implementation for:– F1(A,B,C) = AB’ + AC + A’BC’F1(A,B,C) = AB’ + AC + A’BC’– F2(A,B,C) = (AC + BC)’F2(A,B,C) = (AC + BC)’

Solution:Solution:– 3 inputs, 2 outputs ( 2 OR gates)3 inputs, 2 outputs ( 2 OR gates)– 4 distinct product terms (4 AND gates)4 distinct product terms (4 AND gates)– Use XOR array to find complementsUse XOR array to find complements

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PLA Example (cont.)PLA Example (cont.)

XOR array

F2’ F1

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PLA Example (cont.)PLA Example (cont.)Tabular Form SpecificationTabular Form Specification

of interconnection of interconnection programmingprogramming

F1 = AB’+AC+A’BC’F2 = AC+BC

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Determining the size of a Determining the size of a PLAPLA

Given:Given:– nn inputs inputs– pp product terms product terms– mm outputs outputs

PLA size is:PLA size is:– Gates: Gates: nn INV (and maybe INV (and maybe nn BUF) + BUF) + pp ANDs ANDs

+ + mm ORs + ORs + mm XORs XORs– Programmable interconnections: Programmable interconnections:

2np + pm + 2m2np + pm + 2m

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Programmable Array Logic Programmable Array Logic (PAL)(PAL) OR plane (array) is fixed, AND OR plane (array) is fixed, AND

plane can be programmedplane can be programmed Less flexible than PLALess flexible than PLA # of product terms available per # of product terms available per

function (OR outputs) is limitedfunction (OR outputs) is limited

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Programmable Array Logic Programmable Array Logic (PAL)(PAL)

PALs offers one level of programmability where inputs can beconnected to programmable AND gates followed by a fixed OR gate plane.

In order to support sequential circuits, the OR gates are usuallyfollowed by flip-flops.

PALs are easier to program than PLAs, but they are not as flexible.

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ProgrammablProgrammable e Array Logic Array Logic (PAL)(PAL)

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PAL ExamplePAL Exampleinputs

1st output section

2nd output section

3rd output section

4th output section

Only functions withat most four products can be implemented

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PAL-based circuit PAL-based circuit implementationimplementation

W = ABC + CDX = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD

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Can we implement more Can we implement more complex functions using complex functions using PALs?PALs?

Yes, by allowing output lines to also Yes, by allowing output lines to also serve as input lines in the AND serve as input lines in the AND plane.plane.

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ExampleExample

Implement the combinational circuit Implement the combinational circuit described by the following equations, described by the following equations, using a PAL with 4 inputs, 4 outputs, using a PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure.and 3-wide AND-OR structure.– W(A,B,C,D) = W(A,B,C,D) = m(2,12,13)m(2,12,13)– X(A,B,C,D) = X(A,B,C,D) = m(7,8,9,10,11,12,13,14,15)m(7,8,9,10,11,12,13,14,15)– Y(A,B,C,D) = Y(A,B,C,D) = m(0,2,3,4,5,6,7,8,10,11,15)m(0,2,3,4,5,6,7,8,10,11,15)– Z(A,B,C,D) = Z(A,B,C,D) = m(1,2,8,12,13)m(1,2,8,12,13)

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Example (cont.)Example (cont.)

Use function simplification Use function simplification techniques to derive:techniques to derive:– W = ABC’+A’B’CD’W = ABC’+A’B’CD’– X = A+BCDX = A+BCD– Y=A’B+CD+B’D’Y=A’B+CD+B’D’– Z=Z=ABC’+A’B’CD’ABC’+A’B’CD’+AC’D’+A’B’C’D+AC’D’+A’B’C’D

= = WW + AC’D’+A’B’C’D + AC’D’+A’B’C’D

3333

Example (cont.)Example (cont.)

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Example (cont.)Example (cont.)Tabular Form Specification

of interconnection programming

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Complex Complex ProgrammablProgrammable e Logic Logic Devices Devices (CPLD)(CPLD)

Multiple PLDs can be combined on a single chip by using programmable interconnect structures. These PLDsPLDs are calledCPLDs.CPLDs.

3636

FPGAsFPGAsFPGAs are somewhatsimilar to CPLDs. However, the latter tend to have a more predictable delay due to their interconnect structure.

3737

Implementation Implementation StrategiesStrategiesBCD to Excess 3 Converter

D2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X• Q1 + X • Q1

175X Q2 Q1 Q0

Z D2 D1 D0

converter PLA10

CLK

10

1

\Reset

CLK

13 12

X D C B A

QD QD

QC QC

QB QB

QA QACLR

9

1

15 14

10 117 6

2 3

Z

5 4

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Implementation Implementation StrategiesStrategiesBCD to Excess 3 Serial Converter

10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate

D1 = D11 + D12

D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0

D12 = X • Q2 • Q0 + Q1 • Q0

0. Q2 • Q01. Q2 • Q08. X • Q2 • Q1 • Q09. X • Q2 • Q016. X • Q2 • Q017. Q1 • Q024. D1125. D1232. Q033. not used40. X • Q141. X • Q1

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41

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Implementation Implementation StrategiesStrategiesBCD to Excess 3 Serial Converter

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41

PAL10H8

X Q2 Q1 Q0

D2

D1

D0

Z

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

1211

AND Gate Array

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Implementation Implementation StrategiesStrategies

More Advanced PAL Architectures

Registered PAL ArchitectureBuffered Input

or product term

Negative LogicFeedbackD2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X • Q1 + X • Q1

CLK OE

D2 Q2+

Q2+

Q2 Q2 Q0 Q0

X

D Q

Q

Q2 • Q0

Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2+

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Programming Programming TechnologyTechnology

The first user programmable switch is the fuse used in simple PLDs.For high density devices (CPLDs, FPGAs), different approaches are used to achieve programmability. The properties of these programmable switches, such as size, volatility, process technology, on-resistance, and capacitance, determine the major features of an FPLD architecture.