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PLDss
Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches
Main types of PLDs PLA PAL ROM CPLD FPGA
C t hi t d d ll f t Custom chips: standard cells, sea of gates
PLD as a Black Boxas a ac o
Logic gates andInputs
Outputsand programmable
switches(logic variables)
Outputs(logic functions)
Programmable Logic Array (PLA)og a ab e og c ay ( )
Use to implement x 1 x 2 x n
circuits in SOP form
Th ti iInput buffers
d The connections inthe AND plane areprogrammable
inverters and
x 1 x 1 x n x n
The connections inth OR l
P 1
1 1 n n
the OR plane areprogrammable
AND plane OR planeP k
f 1 f m
Gate Level Version of PLAGa e e e e s o ox1 x2 x3
Programmable
P1OR plane
Programmableconnections
f1 = x1x2+x1x3'+x1'x2'x3
P2
f2 = x1x2+x1'x2'x3+x1x3
P3
P4
f1 f2
AND plane
Customary Schematic of a PLACus o a y Sc e a c o ax 1 x 2 x 3
f1 = x1x2+x1x3'+x1'x2'x3P 1
OR plane
f2 = x1x2+x1'x2'x3+x1x3
1
P 2
P 3
P 4
f 1 f 2
AND plane x marks the connections left in place after programming
Limitations of PLAsa o s o s
PLAs come in various sizes Typical size is 16 inputs, 32 product terms, 8 outputs
Each AND gate has large fan-in this limits the number of inputs that can be provided in a PLA
16 inputs 316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates as well This makes PLAs slower and slightly more expensive than
l i b di d h lsome alternatives to be discussed shortly
8 outputs could have shared minterms, but not required
Programmable Array Logic (PAL)og a ab e ay og c ( )
Also used to implement x 1 x 2 x n
circuits in SOP form
Th ti iInput buffers
d The connections inthe AND plane areprogrammable
inverters and
x 1 x 1 x n x n
fixed connections
The connections inth OR l
P 1
1 1 n n
the OR plane areNOT programmable
AND plane OR planeP k
f 1 f m
Example Schematic of a PALa p e Sc e a c o ax 1 x 2 x 3
f1 = x1x2x3'+x1'x2x3
f 1
P 1
P2
f2 = x1'x2'+x1x2x3
P 2
P 3
f 2 P 4
AND plane
Comparing PALs and PLAsCo pa g s a d s
PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs
PALs are simpler to manufacture, cheaper, and faster (better performance)
PALs also often have extra circuitry connected to the t t f h OR toutput of each OR gate
The OR gate plus this circuitry is called a macrocell
Macrocellac oce
f1
SelectEnable
OR gate from PAL 01
D Q
1
D Q
Clock Flip-flop
back to AND plane
Macrocell Functionsac oce u c o s
Enable = 0 can be used to allow the output pin for f1to be used as an additional input pin to the PAL
Enable = 1 Select = 0 is normal Enable = 1, Select = 0 is normalfor typical PAL operation
f1
SelectEnable
0
1
Enable = Select = 1 allowsthe PAL to synchronize the output changes with a clock
D Q
Clock
1
output changes with a clockpulse back to AND plane
The feedback to the AND plane provides for multi-level design
Multi-Level Design with PALsu e e es g s
f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag' where g = BC + B'C' and C = h below
A B
Sel = 0En = 0
0
1 h
D Q
Clock Sel = 0
En = 10
1g
Select
0
1
D Q
Clock
f
D Q
Clock
1
ROMO
A ROM (Read Only Memory) has a fixed AND plane and a programmable OR plane
Si f AND l i 2n h b f i t Size of AND plane is 2n where n = number of input pins Has an AND gate for every possible minterm so that all
input combinations access a different AND gate
OR plane dictates function mapped by the ROM OR plane dictates function mapped by the ROM
4x4 ROMO
22x4 bit ROM has 4 addresses that are decoded
oder
a 0
2 -to
-4 d
eco0
a 1
3 d 2 d 1 d 0 d
Programming SPLDsog a g S s
PLAs, PALs, and ROMs are also called SPLDs –Simple Programmable Logic Devices
SPLD t b d th t th it h SPLDs must be programmed so that the switches are in the correct places CAD tools are usually used to do this
A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit
There are two basic types of programming techniques Removable sockets on a PCB In system programming (ISP) on a PCB
This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs
An SPLD Programming UnitS og a g U
The SPLD is removed from the PCB, placed into the punit and programmed there
Removable SPLD Socket Packagee o ab e S Soc e ac age
PLCC (plastic-leaded chip carrier)
PLCC socket soldered toPLCC socket soldered to the PCB
ard
Printed circuit board
In System Programming (ISP)Sys e og a g ( S )
Used when the SPLD cannot be removed from the PCB
A i l bl d PCB ti i d t A special cable and PCB connection are required to program the SPLD from an attached computer
Very common approach to programming more complex PLDs like CPLDs, FPGAs, etc.
CPLDC
Complex Programmable Logic Devices (CPLD)
SPLDs (PLA, PAL) are limited in size due to the ll b f i t d t t i d th li it dsmall number of input and output pins and the limited
number of product terms Combined number of inputs + outputs < 32 or so
CPLDs contain multiple circuit blocks on a single chipchip Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an
interconnection network that is programmable Each block is connected to an I/O block as well
Structure of a CPLDS uc u e o a C
ck I/
PAL-likeblock
I/O
blo
c
PAL-likeblock
/O block
i iInterconnection wires
PAL-likeblockO
blo
ck
PAL-likeblock
I/O bloblock
I/O block ock
Internal Structure of a PAL-like Blocke a S uc u e o a e oc
Includes macrocells Usually about 16 each
Fixed OR planes PAL-like block Fixed OR planes
OR gates have fan-inbetween 5-20 PAL-like block
XOR gates providenegation ability
D Q
D Qg y XOR has a control
input D Q
D Q
More on PAL-like Blockso e o e oc s
CPLD pins are provided to control XOR, MUX, and tri-state gates
Wh t i t t t i di bl d th di When tri-state gate is disabled, the corresponding output pin can be used as an input pin The associated PAL-like block is then useless
The AND plane and interconnection network are programmableprogrammable
Commercial CPLDs have between 2-100 PAL-like Commercial CPLDs have between 2 100 PAL like blocks
Programming a CPLDog a g a C
CPLDs have many pins – large ones have > 200 Removal of CPLD from a PCB is difficult without breaking
the pins Use ISP (in system programming) to program the CPLD( y p g g) p g JTAG (Joint Test Action Group) port used to connect the
CPLD to a computer
Example CPLDa p e C
Use a CPLD to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
(from interconnection wires)( )x 1 x 2 x 3 x 4 x 5 x 6 x 7 unused
PAL-like block
0 0 1
f D Q
FPGAG
SPLDs and CPLDs are relatively small and useful for simple logic devices Up to about 20000 gates
Field Programmable Gate Arrays (FPGA) can handle larger circuits No AND/OR planes Provide logic blocks, I/O blocks, and interconnection wires
and switchesand switches
Logic blocks provide functionalityInterconnection switches allow logic blocks to be connected Interconnection switches allow logic blocks to be connected to each other and to the I/O pins
Structure of an FPGAS uc u e o a G
I/O bl kI/O block
interconnectionswitch
I/O oc
k block I/
O b
lo
I/O block logic block
LUTsU s
Logic blocks are implemented using a lookup table (LUT) Small number of inputs, one output Contains storage cells that can be loaded with the desired Contains storage cells that can be loaded with the desired
values
A 2 input LUT uses 3 MUXes A 2 input LUT uses 3 MUXesto implement any desired functionof 2 variables Shannon's expansion at work!
0/1
x 1
Shannon s expansion at work!f
0/1
0/1
0/10/1
x 2
Example 2 Input LUTa p e pu U
x1 x2 fx1 x2 f0 0 10 1 01 0 0
f = x1'x2' + x1x2, or using Shannon's expansion:
f = x1'(x2') + x1(x2)= x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))1 1 1 x1 (x2 (1) + x2(0)) + x1(x2 (0) + x2(1))
x1
1
0
x 1
f 0
0
1
x 2
3 Input LUT3 pu U
7 2x1 MUXes and x 1
8 storage cells arerequired 0/1
x 2
Commercial LUTs have4-5 inputs, and 16-32
0/1
0/1
0/1storage cells f 0/1
0/1
0/10/1
0/1
0/10/1
x 3
Programming an FPGAog a g a G
ISP method is used
LUTs contain volatile storage cells None of the other PLD technologies are volatile FPGA storage cells are loaded via a PROM when power is
first applied
The UP2 Education Board by Altera contains a JTAG port a MAX 7000 CPLD and a FLEX 10KJTAG port, a MAX 7000 CPLD, and a FLEX 10K FPGA The MAX 7000 CPLD chip is EPM7128SLC84-7 EPM7 MAX 7000 family; 128 macrocells; LC84 84 pin
PLCC package; 7 speed grade
Example FPGAa p e G
Use an FPGA with 2 input LUTS to implement the function f = x1x2 + x2'x3
f = x x
x 3 f
f1 = x1x2
f2 = x2'x3
f = f1 + f2 0 0 x 1 x 2
x 1
1 0 0
0 0 1
1
x 2
2
x 3
f 1 f 2 x 2
0 1 1
f 1 f
1 1 f 2
Another Example FPGAo e a p e G
Use an FPGA with 2 input LUTS to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
Fan in of expression is too large for FPGA (this was simple Fan-in of expression is too large for FPGA (this was simple to do in a CPLD)
F t f t t b i ith f i 2 Factor f to get sub-expressions with max fan-in = 2 f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5)
= (x1x6' + x2x7)(x3 + x4x5)
Could use Shannon's expansion instead Goal is to build expressions out of 2-input LUTs
FPGA ImplementationG p e e a o
f = (x1x6' + x2x7)(x3 + x4x5)x 4 f x 5 x 3
0 0
x 4
x 1
0 1
x 3 0 0
x 1 0 0 1 x 5
C x 6
1 1 1 C
E 0 1 0 x 6
A
0 A 0 D
x 2
0 x 2 1 1 1 B
D 0 0 1 E
f x 7
0 0 1 x 7
B
Custom ChipsCus o C ps
PLDs are limited by number of programmable switches Consume space Reduce speed Reduce speed
Custom chips are created from scratch Expensive used when high speed is required, volume
sales are expected, and chip size is small but with high density of gates
ASICs (Application Specific Integrated Circuits) are custom chips that use a standard cell layout to reduce design costs
Standard CellsS a da d Ce s
Rows of logic gates can be connected by wires in the routing channels Designers (via CAD tools) select prefab gates from a library
and place them in rowsp Interconnections are made by wires in routing channels
Multiple layers may be used to avoid short circuiting A hard-wired connection between layers is called a via A hard wired connection between layers is called a via
f 1
f 2 x 1
x 3
x 2
f 1
Example: Standard Cellsa p e S a da d Ce s
f1 = x1x2 + x1'x2'x3 + x1x3' f2 = x1x2 + x1'x2'x3 + x1x3
f 2 x 1
x 2
f 1
x 3
Sea of Gates Gate ArraySea o Ga es Ga e ay
A Sea of Gates gate array is just like a standard cell except all gates are of the same type Interconnections are run in channels and use multiple
layersy Cheaper to manufacture due to regularity
Example: Sea of Gatesa p e Sea o Ga es
f1 = x2x3' + x1x3 bl k b ttblack bottom layer channels
red top layer channels
Digital Logic Technology Tradeoffsg a og c ec o ogy adeo s
Full customVLSI design
Speed / Density / Complexity / Likely
ASICs
Complexity / LikelyMarket Volume CPLDs
FPGAs
PLDs
Engineering cost / Time to develop
