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1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 1
Processor Data Paths -ALU and RegistersIncorporating the ALU into a Processor Data Path
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 2
L4 – Incorporint ALU into data pathBuilding up the data pathControl of the data path
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 3
Have our multifunction ALUWill now put an interface around the ALU and build up a data path
P0 P1 P2 P3
Pi
K0 K1 K2 K3
Ki
R0 R1 R2 R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0 P1 P2 P3
Pi
K0 K1 K2 K3
Ki
R0 R1 R2 R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0 P1 P2 P3
Pi
K0 K1 K2 K3
Ki
R0 R1 R2 R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0 P1 P2 P3
Pi
K0 K1 K2 K3
Ki
R0 R1 R2 R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0 P1 P2 P3
Pi
K0 K1 K2 K3
Ki
R0 R1 R2 R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 4
The wrapperEstablish an interface to the ALU slicesHave the data inputsHave a Carry inHave control inProduce
The result RA carry out
A B
CinCout
R
PctlKctl
Rctl
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 5
Build up step 1Add input and output latches/bus driversAdd 2 internal data bussesAdd flag generationInputs & control –A,B,Cin,Pctl, Kctl, RctlOutputs – Cout, R, Nflag, Zflag
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 6
Build up step 2Now add a general purpose registersThese are dual ported registersLoading or driving of registers on the bus is controlled by the clockBusses are tristate
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 7
Dual Ported RegistersRegister are dual ported
Registers can be loaded from or drive a value onto both the A Bus and B Bus simultaneouslyPossible combinations on same cycle
Drive both the A Bus and B BusLoad from both the A Bus and B Bus
Must be different registers!!!!!!!!!Register bank does not check for this – responsibility of the controller
Load from one Bus and drive the other
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 8
Now add the controllerNote the Instruction Register and Flags register
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
CO
NTR
OLL
ERIR
Flag
s
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 9
Program Counter and MDR, MARMDR – Memory Data RegisterMAR – Memory Address RegisterPC Register increment and offset integrated into register design
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUSMDR
MDR dir MDRlatch
To/From Memory
Prog Cntr
MARMAR_Aload MAR_Bload
Offset adder +1PC Ctl sig
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 10
Other Functional UnitsMay want to incorporate
ShifterFloating Point UnitsIndex addressing registersEtc.
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUSMDR
MDR dir MDRlatch
To/From Memory
Prog Cntr
MARMAR_Aload MAR_Bload
Offset adder +1PC Ctl sig
ShifterDist
Shifter DriveShifter Load
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 11
General Operation of a DatapathDatapaths are generally synchronousInternal clock most likely higher than bus clockTypical RTL of datapath
Cyc 1: Mem(PC) -> IRPC + 1 -> PC
Cyc 2: RS1+RS2 -> ALUoutCyc 3: ALU out -> RS1
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 12
Datapath Control EvolutionFinite State Machine (FSM)
Fixed and unvarying action of a datapathFSM implemented with PLA
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 13
Use of flagsHere the current data can affect the action of the controller
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 14
Load flagsBy loading a flags register can use them to affect the controller only at specific points in the “program”
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 15
Data from memory usedIn addition to flags, data from memory can affect the state and the datapaths action
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 16
Instruction RegHave now progressed to a “stored” program
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 17
Alternative formHere use a ROM rather than a PLA finite state machine
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 18
Another alternativeUse a microprogram counter
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 19
A different sliceJust a different visualization
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 20
OperationShows steps the controller would go through to execute the instructions
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 21
Operation Examples – ALU op
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 22
Store result back to memory
