Processing Unit

Fetch cycle

CPU: • Fetches an instruction from primary storage • Increments a pointer to location of next instruction • Separates instruction into components (instruction

code and data inputs) • Stores each component in a separate register

Execution cycle

ALU: • Retrieves instruction code from a register • Retrieves data inputs from registers • Passes data inputs through internal circuits to

perform data transformation • Stores results in a register

◦ Fetch instructions Processor reads instructions from the memory ◦ Interpret instructions Instruction is decoded to determine what action is required ◦ Fetch data Execution of an instruction may require reading data from

memory or an I/O Module. ◦ Process data Execution of an instruction may require performing some

arithmetic or logical operation on the data ◦ Write data The results of an execution may require writing data to

memory or an I/O module.

CPU must have some working space (temporary storage) called registers

Number and function vary between processor designs

Control and Status Registers Used by control unit to control the operation of the

processor User Visible Registers Enable the machine or Assembly Language

Programmer to minimize the main memory references by optimizing the registers

Data Registers Used only to hold data and cannot be

employed In the calculation of an operand address Address Registers Devoted to particular addressing mode

Four Registers essential for instruction execution Program Counter Contains the address of the instruction to be fetched Instruction Decoding Register Contains the instruction most recently fetched Memory Address Register Contains the address of a location in memory Memory Buffer Register Contains a word of data to be written to memory or

the word most recently read.

Fetch Read the next instruction from memory into

the processor Execute Interpret the Opcode and perform the

indicated operation. Interrupt If interrupts are enabled and an interrupt

has occurred, save the current process state and service the interrupt

May require memory access to fetch operands

Indirect addressing requires more memory accesses

Fetching of indirect address as one more instruction sub cycle

Fetch ◦ PC contains address of next instruction ◦ Address moved to MAR ◦ Address placed on address bus ◦ Control unit requests memory read ◦ Result placed on data bus, copied to MBR, then to

IR ◦ Meanwhile PC incremented by 1

IR is examined If indirect addressing, indirect cycle is

performed ◦ Right most N bits of MBR transferred to MAR ◦ Control unit requests memory read ◦ Result (address of operand) moved to MBR

Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to

MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be

fetched

Six stages in pipelining Fetch instruction Read the next expected instruction into a buffer. Decode instruction Determine the opcode and the operand specifiers Calculate operands Calculate the effective address of each source

operand

Fetch operands Fetch each operand from memory. Operands in

register need not be fetched Execute instructions Perform the indicated operation and store the

result, if any in the specified destination operand location

Write result Store the result in memory.