12
Processing mechanics for flip-chip assemblies J. Wang *, W. Ren, D. Zou, Z. Qian, S. Liu Department of Mechanical Engineering, Wayne State University, Detroit, MI 48202, USA Received 25 February 1997; received in revised form 1 July 1998; accepted 11 September 1998 Abstract In this paper, a non-linear finite element framework has been implemented to simulate the sequential build-up of a flip-chip package. A generalized deformation model with element removal and addition is used to activate and deactivate the underfill material layer to simulate flip-chip package fabrication. Using process models, one can determine the warpage stresses at any intermediate stage in the process. In addition, topological change is also considered in order to model the sequential steps during the flip-chip assembly. Geometric and material nonlinearity which includes the creep behavior of underfill and solder balls, and temperature-dependent material properties are considered. Dierent stress-free temperatures for dierent elements in the same model are used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. This approach (the processing model established in this paper) is in contrast to the non-processing model employed by many researchers, which is shown to yield overly conservative and sometimes erroneous results, leading to non-optimal design solutions. From the finite element analysis, it is found that the strains and deflections obtained from the non-processing model are generally smaller than those obtained from the processing model due to the negligence of the bonding process- induced residual strains and warpage. Furthermore, the fatigue life for the outmost solder ball predicted by the processing model is much shorter than that predicted by the non processing model based on the Con–Manson equation. On the other hand, in order to prove the soundness of the framework established in this paper, the test results obtained by using the laser moire´ interferometry technique are compared with the results achieved from the proposed numerical analysis vehicle. It is shown that the deformation values of the flip-chip package predicted from the finite element analysis are in a good agreement with those obtained from the test. # 1999 Elsevier Science Ltd. All rights reserved. Keywords: Processing mechanics; Finite element analysis; Residual stress; Flip-chip; Creep; Warpage; Moire´ interferometry 1. Introduction The trend in the development of new electronic package is low cost, fine pitch, high performance and high reliability. A lot of eorts have been made to minimize process steps for producing an electronic device. However, the reliability has to be assured. In particular, the process-induced stresses have to be reasonably modeled. In addition, what has been trou- bling the electronic packaging and polymer-related fields in terms of the residual stress modeling is the so- called stress-free temperature. Although there exist a number of processing issues that are of significant con- cern in the fabrication of multi-layered material con- figurations, the process engineer would like to reduce, from the thermo-mechanical standpoint, the warpage and the stresses. A common practice which is often employed by many researchers [1–5] in predicting the residual warpage and the stresses is to employ a ‘non- processing’ model of the final configuration. In the non-processing model, the entire structure is assumed to be stress-free at the cure temperature of the poly- mer, and then cooled down to room temperature. Thus, if multiple processes are involved, it would be Computers and Structures 71 (1999) 457–468 0045-7949/99/$ - see front matter - # 1999 Elsevier Science Ltd. All rights reserved. PII: S0045-7949(98)00202-8 PERGAMON * Corresponding author. Tel.: +1-313-577-4037; fax: +1- 313-577-8789; e-mail: [email protected]

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Page 1: Processing mechanics for flip-chip assemblies

Processing mechanics for ¯ip-chip assemblies

J. Wang *, W. Ren, D. Zou, Z. Qian, S. Liu

Department of Mechanical Engineering, Wayne State University, Detroit, MI 48202, USA

Received 25 February 1997; received in revised form 1 July 1998; accepted 11 September 1998

Abstract

In this paper, a non-linear ®nite element framework has been implemented to simulate the sequential build-up ofa ¯ip-chip package. A generalized deformation model with element removal and addition is used to activate anddeactivate the under®ll material layer to simulate ¯ip-chip package fabrication. Using process models, one can

determine the warpage stresses at any intermediate stage in the process. In addition, topological change is alsoconsidered in order to model the sequential steps during the ¯ip-chip assembly. Geometric and material nonlinearitywhich includes the creep behavior of under®ll and solder balls, and temperature-dependent material properties are

considered. Di�erent stress-free temperatures for di�erent elements in the same model are used to simulate practicalmanufacturing process-induced thermal residual stress ®eld in the chip assembly. This approach (the processingmodel established in this paper) is in contrast to the non-processing model employed by many researchers, which isshown to yield overly conservative and sometimes erroneous results, leading to non-optimal design solutions. From

the ®nite element analysis, it is found that the strains and de¯ections obtained from the non-processing model aregenerally smaller than those obtained from the processing model due to the negligence of the bonding process-induced residual strains and warpage. Furthermore, the fatigue life for the outmost solder ball predicted by the

processing model is much shorter than that predicted by the non processing model based on the Co�n±Mansonequation. On the other hand, in order to prove the soundness of the framework established in this paper, the testresults obtained by using the laser moire interferometry technique are compared with the results achieved from the

proposed numerical analysis vehicle. It is shown that the deformation values of the ¯ip-chip package predicted fromthe ®nite element analysis are in a good agreement with those obtained from the test. # 1999 Elsevier Science Ltd.All rights reserved.

Keywords: Processing mechanics; Finite element analysis; Residual stress; Flip-chip; Creep; Warpage; Moire interferometry

1. Introduction

The trend in the development of new electronic

package is low cost, ®ne pitch, high performance and

high reliability. A lot of e�orts have been made to

minimize process steps for producing an electronic

device. However, the reliability has to be assured. In

particular, the process-induced stresses have to be

reasonably modeled. In addition, what has been trou-

bling the electronic packaging and polymer-related

®elds in terms of the residual stress modeling is the so-

called stress-free temperature. Although there exist a

number of processing issues that are of signi®cant con-

cern in the fabrication of multi-layered material con-

®gurations, the process engineer would like to reduce,

from the thermo-mechanical standpoint, the warpage

and the stresses. A common practice which is often

employed by many researchers [1±5] in predicting the

residual warpage and the stresses is to employ a `non-

processing' model of the ®nal con®guration. In the

non-processing model, the entire structure is assumed

to be stress-free at the cure temperature of the poly-

mer, and then cooled down to room temperature.

Thus, if multiple processes are involved, it would be

Computers and Structures 71 (1999) 457±468

0045-7949/99/$ - see front matter - # 1999 Elsevier Science Ltd. All rights reserved.

PII: S0045-7949(98 )00202-8

PERGAMON

* Corresponding author. Tel.: +1-313-577-4037; fax: +1-

313-577-8789; e-mail: [email protected]

Page 2: Processing mechanics for flip-chip assemblies

impossible to use this alleged stress-free temperature.

Indiscriminate application of this method may provide

misleading results because the material layers are

deposited at di�erent temperatures, and therefore, not

all layers are stress-free at the same temperature. In

addition, residual stresses might develop due to plastic

deformations (under a large thermal load) at an inter-

mediate process step, which cannot be captured by the

non-processing models. It is, therefore, important to

take into account the entire history of the fabrication

process and the evolution of stresses to understand the

thermo-mechanical behavior of a multi-layered struc-

ture. Since sequential processing of electronic packages

consisting of a multi-layered con®guration with dissim-

ilar materials is common in the electronic packaging

industry today, the increased demand for miniaturiza-

tion with smaller line widths and spaces, high-density

interconnects and the advent of new materials and pro-

cesses requires a better understanding of the mechanics

of the processes so as to be able to reduce the high

costs associated with the traditional trial-and-error,

build-and-test approach. A virtual prototyping

approach employing numerical modeling can serve as

a powerful tool to perform quick `what-if' parametric

studies and simulate the design±build±operate (DBO)

philosophy. Therefore, process modeling can be e�ec-

tively used to determine such evolution of stresses and

strains as a multi-layered structure is sequentially fabri-

cated. Results from such process models can then be

used for selecting the optimum material, geometry, and

process parameters.

On the other hand, the topological change has never

been considered except by Yeh et al. [6], which is

proved to be important even when all the material

properties are assumed to be linear elastic. If all the

temperature and time dependent material properties

are considered, the topological change and the

sequence of processing steps could have signi®cant

e�ects on the ®nal residual stress calculations. The im-

plementation of the addition and removal of materials

has been demonstrated in electronic packaging appli-

cations by a few researchers. Among them, Cifuentes

and Shareef [7, 8] have used arti®cial nodes with multi-

point constraints to activate and deactivate di�erent

layers. They have used the models to study the manu-

facturing of a copper line. The work done by Wu et

al. [9] uses element birth and death to add and remove

materials in HDI processing. However, both of these

studies only use non-creep constitutive models, without

any experimental validation of the results. It has been

found that the materials employed in electronic

packages such as solder alloys and polymers (under®lls

and epoxies) exhibit strong viscoelastic and viscoplastic

behavior even at room temperature, to say nothing of

the operation environment which is generally at elev-

ated temperature. Therefore, in order to more accu-

rately evaluate the sequential process-induced stress

®eld in the chip assembly, a non-linear ®nite element

framework which cannot only re¯ect the nonlinearity

(plasticity, viscoelasticity, viscoplasticity and time-

dependent properties) of the materials involved, but

also simulate a series of manufacturing processes, is

required.

The objective of this study is to build such a non-

linear ®nite element framework. As a demonstration, a

¯ip-chip package has been investigated in this paper.

The ¯ip-chip package consists of a silicon chip bonded

to the top of a substrate. Under®lling is carried out by

dispensing under®ll material under and around all of

the chip, as shown in Fig. 1 schematically. In general,

the manufacturing processes of ¯ip-chip mainly

include: (a) bonding the silicon chip onto the substrate

at temperature T1, and then cooling the chip to tem-

perature T2; (b) dispensing with the under®ll material

under and around all of the chip at temperature T2,

and ®nally cooling the ¯ip-chip to room temperature.

T1 is generally higher than T2.

Fig. 1. Structure and cross section of ¯ip-chip.

Fig. 2. Boundary conditions, dimensions and geometry of ¯ip-

chip (unit: mm).

J. Wang et al. / Computers and Structures 71 (1999) 457±468458

Page 3: Processing mechanics for flip-chip assemblies

2. Modeling and method of solution

2.1. Modeling

A typical ¯ip-chip has been taken into consideration.Due to the symmetry, only one-half of the chip crosssection is investigated. Assume the ¯ip-chip package

considered satis®es the plane stress conditions. It cantherefore be simpli®ed to be a 2-D FE model. Theboundary conditions, dimensions and geometry of the

¯ip-chip model are illustrated in Fig. 2 (not drawn toscale). The problem is idealized by a ®nite elementmesh shown in Fig. 3. A close-up view of ®ne mesh is

plotted in Fig. 4. The nodes along the symmetric lineare set to u=0, whereas the node at the left bottomcorner is set to u= v=0.The material behavior of the silicon chip is assumed

to be linear elasticity and temperature-independent.

The Young's modulus and Poisson's ratio of the sili-con chip are 169.5 GPa and 0.278, respectively. The

coe�cient of thermal expansion of the silicon chip is3.2 ppm/8C. The substrate is composed of elastic FR-4material. The Poisson's ratios nxz, nxy and nyz are 0.02,0.143 and 0.143, respectively. The Young's moduli Ex,

Ez and Ey are 22.4, 22.4 and 1.6 GPa, respectively.The CTEs of FR-4, ax, ay and az are 16, 35 and 16ppm/8C, respectively [10]. The x and y directions are

de®ned in Fig. 2. The solder balls of the ¯ip-chip aremade of eutectic solder alloy. They are assumed to beelastic±plastic isotropic materials at initial stress state.

The Poisson's ratio is assumed to be 0.4. The Young'smodulus is determined by the following equation:

E � 63:875ÿ 0:137T�K� �1�The true stress±strain relationship of the considered

solder alloy is plotted as shown in Fig. 5 [11]. The

Fig. 3. Finite element mesh for ¯ip-chip.

Fig. 4. Local general ®nite element ®ne mesh for ¯ip-chip.

J. Wang et al. / Computers and Structures 71 (1999) 457±468 459

Page 4: Processing mechanics for flip-chip assemblies

CTE values of the solder balls are tabulated in

Table 1 [16]. It is found that they are temperature-dependent.The under®ll is also considered to be elastic±plastic

isotropic materials at initial stress state. The Poisson'sratio is assumed to be 0.4. The Young's modulus isdetermined by the equation as follows:

E � 17:3145� 0:1871 ln _E�1=s� ÿ 0:02795T�K� �2�The true stress±strain relationship of the under®ll is il-

lustrated in Fig. 6 [12]. In addition, the coe�cients ofthermal expansion of the under®ll employed aremeasured by authors using the moire interferometry

technique in a vacuum chamber [13]. The values of theCTEs of the under®ll are plotted in Fig. 7. It is clearthat the CTEs of the under®ll are also temperature-

dependent.The creep behavior of the solder balls and the

under®ll is described by the hyperbolic power

law [14, 15]:

_Ecr � A�sinhBs�n exp�ÿDH=RT� �3�where EÇ cr is the uniaxial equivalent creep strain; s theequivalent stress; DH the activation energy; R the uni-versal gas constant; T the temperature; A, B and n

some constants which are related to temperature andloading etc. For the eutectic solder balls, the par-ameters, A, B, n, DH and R can be found in Ref. [14].

For the under®ll, the parameters, A, B, n, DH and Rcan be found in reference [15].

The ¯ip-chip package is subjected to a thermal load.

In order to simulate the practical manufacturing pro-cess in the chip assembly, the thermal loads for twotemperature drops are considered. These include (a)

temperature drop after bonding process (180 to1358C), and (b) temperature drop after under®llingprocess (135 to 258C).The silicon chip and substrate are bonded together

at around 1808C, and then cooled down to 1358C. Theunder®ll is dispensed under and around all of the ¯ip-

chip package and cured at around 1358C, and thencooled down to room temperature (258C).Two types of FE models for di�erent thermal load-

ing conditions are analyzed to perform comparable

studies. These two models are described as follows:

1. Under®lled model with two steps of temperature drop

(processing model). The analysis conducted in thismodel is separated into two steps to simulate thepractical manufacturing process in the chip assem-bly. The under®ll elements in this FE model are

inactive in the ®rst step of temperature drop afterthe bonding process, and then are activated in thesecond step of temperature drop after the under®ll-

Fig. 5. True stress±strain relationship of eutectic solder alloy.

Table 1

CTE values of solder ball alloys as a function of temperature

(reference value of temperature=76.858C)

Temperature (8C) CTE for 63%Sn/37%Pb(ppm/8C)

19.85 24.07

26.85 24.20

76.85 25.11

126.85 26.01

Fig. 6. True stress-strain relationship of under®ll.

Fig. 7. Variation of CTE of under®ll against temperature.

J. Wang et al. / Computers and Structures 71 (1999) 457±468460

Page 5: Processing mechanics for flip-chip assemblies

ing process. Two stress-free temperatures for di�er-ent manufacturing processes are selected in the

same FE model. The ®rst stress-free temperature isT1 (1808C) for the silicon chip, solder balls, andsubstrate after the bonding process. The other

stress-free temperature is T2 (1358C) for the under-®ll after the under®lling process. The manufacturingprocesses treated in the processing model are shown

in Fig. 8 schematically.2. Under®lled model with second step temperature drop

(non-processing model). The process-induced ther-

mal residual stress ®eld caused by the ®rst step ofthe temperature drop thermal loading after thebonding process is neglected in this model. The pro-cess-induced thermal residual stress ®eld in the ¯ip-

chip is only based on the second step of the tem-perature drop thermal loading after the under®llingprocess. Therefore, T2 (1358C) is selected as the

stress-free temperature for the whole package.

Since the elastic±plastic and creep constitutive modelsare considered in this ®nite element framework, it is

imperative to use e�ective elements [17]. Hence, theeight-noded plane stress element is used in combi-nation to the ¯ip-chip package FE models in the

analysis.

2.2. Method of solution

As elastic±plastic properties, viscoelasticity, visco-

plasticity and geometric nonlinearity are used in theanalysis the ®nite element models generated for theencapsulated package considered in this paper are

strongly non-linear. The equilibrium equationsobtained by discretizing the virtual work equation may

be written symbolically as

FN�uM� � 0 �4�where FN is the force component conjugate to the Nth

variable in the problem, and uM is the value of theMth variable.In order to solve Eq. (4) for the uM throughout the

history of interest, a series of `small' increments mustbe chosen in the solution. Due to its convergence ratecompared with the convergence rates exhibited by

alternate methods (usually modi®ed Newton or quasi-Newton methods) for the types of non-linear problems,Newton's method was selected in the FE analysis. Thebasic formalism of Newton's method is as follows.

Assume that, after an iteration i, an approximation,uMi , to the solution has been obtained. Let cMi+1 be

the di�erence between this solution and the exact sol-

ution to the discrete equilibrium Eq. (4). This meansthat

FN�uMi � cMi�1� � 0 �5�Expanding the left-hand side of this equation in aTaylor series about the approximate solution uM

i thengives

FN�uMi � �@FN

@uP�uMi �cPi�1 �

@2FN

@uP@uQ�uMi �cPi�1cQi�1 � � � �

� 0 �6�

If uMi is a close approximation to the solution, the

magnitude of each cMi+1 will be small, and so all but

the ®rst two terms above can be neglected giving a lin-ear system of equations:

KNPi cPi�1 � ÿFN

i �7�where

KNPi �

@FN

@uP�uMi � �8�

is the Jacobian matrix, and

FNi � FN�uMi � �9�

The next approximation to the solution is then

uMi�1 � uMi � cMi�1 �10�and the iteration continues.

Convergence of Newton's method is best measuredby ensuring that all entries in FN

i and all entries incMi+1 are su�ciently small.

2.3. Numerical strategy for two stress-free temperaturestates in the processing model

As the bonding process and the under®lling processare treated at two di�erent temperatures, two stress-Fig. 8. Manufacturing processes treated in processing model.

J. Wang et al. / Computers and Structures 71 (1999) 457±468 461

Page 6: Processing mechanics for flip-chip assemblies

free temperatures need to be selected. To begin with,

the whole ®nite element model of the ¯ip-chip con-

sidered is generated. Then, T1 (1808C) is chosen as ®rst

stress-free temperature for the elements of the silicon

chip, solder balls and substrate. After that, when the

bonding process-induced thermal stress ®eld is simu-

lated in the ®rst step of temperature drop, the under®ll

elements are inactive. Finally, T2 (1358C) is selected as

second stress-free temperature only for the under®ll el-

ements. At this very moment, there have already

existed the residual stresses in the elements of the sili-

con chip, solder balls and substrate. After the new

under®ll elements are added to the deformed structure

in their originally de®ned con®guration, they are acti-

vated during the under®lling process. The numerical

procedures in dealing with two stress-free temperature

states in the processing model are summarized as fol-

lows.

Along the interface where new elements are to be

added to the existing mesh separate nodes on the exist-

ing and new elements are used. Corresponding pairs of

these nodes are constrained appropriately at the time

when the new elements are added to the model. Let Ibe a node on the part of the boundary of the existing

mesh where new material is to be added, and J be anode in the same place but on the new elements thatare to be added in an unstressed state. The require-

ment is that, after the elements have been added, thedisplacement of node J is de®ned by

uJ � uI ÿ uI j0 �11�

where uIv0 is the displacement of node I at the timewhen the unstressed element attached to node J areadded. If a third node, K, is de®ned, such thatuK=uIv0, this relation can be written in the form of

linear equations between three nodes I, J and K:

uI ÿ uJ ÿ uK � 0 �12�

The following approach provides this simulation:

1. Use separate nodes on each side of each interface inthe model where new, unstrained elements are to beadded. Let I be a node on the side of the interface

Fig. 9. Thermal vacuum chamber with optical windows.

J. Wang et al. / Computers and Structures 71 (1999) 457±468462

Page 7: Processing mechanics for flip-chip assemblies

that has already been strained, and J be the coinci-dent node on the side of the interface where new el-

ements are being added. Also introduce anadditional node, K, at this same point. K is notdirectly associated with any elements.

2. Introduce linear equations for all degrees of free-dom at each such set of three nodes:

uIi ÿ uJi ÿ uKi � 0 �13�

3. At the start of the analysis (step 1) remove all el-ements that will be added later. Constrain all displa-cement components at all nodes J to zero: uJi =0.

4. Load the structure as required, up to the time when

new elements are to be added:

5. Add in the elements. During this same step also

release all of the uJi , and ®x all of the uKi to theircurrent values. This imposes the necessary equationsto accomplish the simulation.

6. Subsequent steps can be used to load the newlyde®ned structure. Additional elements may be

added later by using the same procedure.

2.4. Experiment validation

In order to prove the soundness of the frameworkestablished in this paper, the results achieved from the

proposed numerical analysis vehicle are validated bycomparison of the test results obtained using the lasermoire interferometry technique. By selection of thesame dimension ¯ip-chip specimen, the experimental

work is conducted under a thermal load condition.Since a vacuum chamber can prevent the highly re¯ec-tive metal ®lm of the specimen grating from being oxi-

dized and can eliminate the interruption of the hot airaround the specimen, the test is undertaken in a vac-uum chamber with large optical windows which is

designed and built in Wayne State University (shownin Fig. 9) [13]. The conduction heating technique isapplied in the experiment, with which the thermal

grease is used. The temperature of the thermal plate iscontrolled by a temperature controller.

The high density laser moire interferometry is awhole-®eld in-plane displacement measurement tech-nique, featuring both high displacement sensitivity and

high spatial resolution. It is especially e�ective for thenon-uniform in-plane deformation measurements andhas been used in the research and development for

microelectronic packages [18±26]. The real-time moireÂ

interferometry is, therefore, adopted to monitor andmeasure the deformation of the ¯ip-chip package

during the test. The schematic drawing of the testsetup of the ¯ip-chip package specimen in conjunctionwith the high density laser moire interferometrymeasurement system is shown in Fig. 10.

The grating is replicated onto the surface of the ¯ip-chip package sample at room temperature. The ther-mal deformations of the ¯ip-chip package specimen in

relation to temperature are measured. A portablemoire interferometer is utilized to acquire in situ dis-placement fringe patterns as a function of temperature

(see Fig. 11) [27, 28]. The fringe patterns are recordedby a CCD camera and stored into a PC computer in adigital format. In addition, the computer image proces-

sing technique is used to analyze the fringe patterns.In the test, the ¯ip-chip specimen is gradually sub-

jected to a temperature rise thermal load from roomtemperature (238C) to 1158C. The thermal load is con-

stantly controlled at 1158C until the test is ®nished.

3. FE Results and discussions

3.1. Comparison of results between numerical work andtest

In order to compare the results between the numeri-

cal work predicted by the ®nite element analysis andthe test conducted by the real-time moire interferome-try in the current study, the steady state deformed con-

®guration of the ¯ip-chip package is selected duringthe test as the benchmark. The displacements at theprescribed locations, C and D, on the specimen (see

Fig. 2) obtained from the test and the ®nite elementanalysis are tabulated in Tables 2 and 3. It is foundthat the relative errors between the displacements atthe prescribed locations obtained from the element

®nite analysis and the test are generally less than 21%.It is shown that the displacements at the prescribed lo-cations on the specimen obtained from the ®nite el-

ement analysis are in agreement with those obtainedfrom the test.The displacement contours simulated by the ®nite el-

ement method and the fringe patterns captured by themoire interferometry technique in both in the x and ydirections are shown in Figs. 12 and 13. It is found

Fig. 10. Schematic drawing of the test setup.

J. Wang et al. / Computers and Structures 71 (1999) 457±468 463

Page 8: Processing mechanics for flip-chip assemblies

that these displacement contours on the ¯ip-chip pack-

age specimen obtained from the moire interferometry

show much of the same patterns compared with those

modeled by the ®nite element method. It is proven that

the results obtained from the ®nite element framework

established in this paper are reliable and could thereby

be used to more accurately predict the manufacturing

process-induced thermal stresses during the sequential

build-up of multi-layered electronic package structures

such as ¯ip-chip package.

3.2. Comparison of results between processing model

and non-processing model

Since the solder joints in ¯ip-chip packages play a

key role as important interconnects, the comparison

will focus on the results of the solder joints between

the processing model and the non-processing model.

Tables 4 and 5 list the shear creep strains and the

shear plastic strains at the right upper corner and left

lower corner of the outmost solder joint obtained by

using the processing model and the non-processing

Fig. 11. Macro±micro moire measurement interferometer.

Table 2

Comparison of steady-state U-displacements between FEA

and moire test (location O selected as reference point)

Location FEA result (mm) Test result (mm) Error (%)

D 7.024 5.838 20.4

Table 3

Comparison of steady state V-displacements between FEA

and moire test (location O selected as reference point)

Location FEA result (mm) Test result (mm) Error (%)

C 9.229 10.842 14.9

J. Wang et al. / Computers and Structures 71 (1999) 457±468464

Page 9: Processing mechanics for flip-chip assemblies

model. From the ®nite element study, it can be found

that the shear creep strains and the shear plastic strains

at the right upper corner and the left lower corner of

the outmost solder joint obtained from the non-proces-

sing model are much smaller than those obtained from

the processing model due to the negligence of the

bonding process-induced residual strains in the non-

processing model. In fact, the fatigue life of the solder

joints in ¯ip-chip packages is directly determined by

their inelastic shear strains [29±31]. Generally speaking,

the larger the inelastic shear strains, the shorter the

fatigue life. From the following discussion, it will be

noted that, since the inelastic shear strains of the out-

most solder joint obtained by the processing model are

much larger than those obtained by the non-processing

model, the fatigue life of the outmost solder joint pre-

dicted by the processing model is shorter than that pre-

dicted by the non-processing model.

The well-known Co�n±Manson equation has been

widely used for fatigue life prediction of many solders

subjected to shear strain-dominated situation. The

simple equation is given by

�Nf�bDgp � Cp �14�where b is called the fatigue ductility exponent; Cp thefatigue ductility coe�cient [30]; Dg p the applied plas-

tic/inelastic strain range; and Nf the fatigue life. Asrough reliability evaluation, the applied plastic/inelasticstrain range in Eq. (14) is replaced by the corner

inelastic shear strain in Tables 4 and 5. The fatigue lifeof the outmost solder ball predicted by Eq. (14) usingthe non-processing model is about 4180 cycles, whilethe fatigue life of the outmost solder ball predicted by

Eq. (14) using the processing model is only about 364cycles. The fatigue life of the outmost solder joint pre-dicted by the non-processing model is one order of

magnitude higher than that predicted by the processingmodel. It is obvious that the non-processing modelyields overly conservative fatigue life prediction for the

outmost solder ball.The variations of de¯ections at the given points

between processing model and non-processing model

Fig. 12. U-displacement fringe patterns and FEA simulation of ¯ip-chip package.

J. Wang et al. / Computers and Structures 71 (1999) 457±468 465

Page 10: Processing mechanics for flip-chip assemblies

versus time are drawn in Figs. 14 and 15. The FEresults also show that there are larger di�erences

between two models. The de¯ection values at the givenpoints obtained from the processing model are usually

25% higher than those obtained from the non-proces-sing model. It is, therefore, shown that the processing

model which is based on the FEM framework set upin this paper can more realistically simulate a series of

practical manufacturing processes in the ¯ip-chipassemblies, whereas a larger error could be caused byusing non-processing model in the analysis of process-

induced residual stress ®eld and warpage in the packa-

ging assemblies due to the negligence of the bondingprocess during cooling from temperature T1 to tem-

perature T2. In particular, even larger errors may becaused in predicting fatigue life of the outmost solderball.

4. Summary

An FEM based on the framework has been estab-

lished for processing mechanics modeling of electronicpackaging assemblies and layered manufacturing,

Fig. 13. V-displacement fringe patterns and FEA simulation of ¯ip-chip package.

Table 4

Comparison of shear creep strains and shear plastic strains at

the right upper corner of the outmost solder joint between the

processing model and the non-processing model

Location Creep strain (%) Plastic strain (%)

Processing model 0.1213 5.5118

Non-processing model 0.1167 1.2425

Table 5

Comparison of shear creep strains and shear plastic strains at

the left lower corner of the outmost solder joint between the

processing model and the non-processing model

Location Creep strain (%) Plastic strain (%)

Processing model 1.5876 3.6945

Non-processing model 0.9872 0.6351

J. Wang et al. / Computers and Structures 71 (1999) 457±468466

Page 11: Processing mechanics for flip-chip assemblies

which is critical for various manufacturing-related

industries.

In order to prove the soundness of the framework

established in this paper, the test results obtained using

the laser moire interferometry technique are compared

with the results achieved from the proposed numerical

analysis vehicle. It is shown that the deformation

values of the ¯ip-chip package predicted from the ®nite

element analysis are in a good agreement with those

obtained from the test. In addition, the displacement

contours in both x and y directions simulated by the

®nite element method show much the same patterns as

those captured by the moire interferometry technique.

By comparison of the FE results obtained from two

models, it is shown that the strains and de¯ections

obtained from the non-processing model are generally

smaller than those obtained from the processing model

due to the negligence of the bonding process-induced

residual strains and warpage. The fatigue life of the

outmost solder joint predicted by the non-processing

model is one order of magnitude higher than that pre-dicted by the processing model based on the Co�n±

Manson equation. The non-processing model yieldsoverly conservative fatigue life prediction for the out-most solder ball. Therefore, an error may be caused by

using non-processing model in the analysis of process-induced residual stress ®eld and warpage in the packa-ging assemblies. In particular, even larger errors may

be caused in predicting fatigue life of the outmostsolder ball.

Acknowledgements

NSF Support through Research Initiation Awardand Presidential Faculty Fellows Award to Dr Sheng

Liu are gratefully acknowledged. The authors alsowish to express their gratitude to the SRC for the par-tial support.

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