Process Variation of MOSFET and MESFET

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  • 8/10/2019 Process Variation of MOSFET and MESFET

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    Process Variation of FINFET and MOSFET

    Govarthanan V, Vashista V

    School of Electronics Engineering, VIT university, Vellore, India

    riation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs, 2011.

    te Sizing: FinFETs vs 32nm Bulk MOSFETsBrian Swahn and Soha Hassoun

    University Medford.

    cess-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices,Yiming Li, ,Chih-Hong Hwang, Hui-Wen CFET: A nanometer MOSFET structure, David John

    erences

    The impact of systematic variations of transistors

    was investigated for the FINFET and MOSFET.

    Comparison between the single gate devices tomulti gate devices.

    We investigate in this paper varying the oxide

    thickness, Doping concentration and threshold

    voltage of the MOSFET as well as FINFET using

    Silvaco TCAD.

    Abstract

    Introduction

    Silvaco TCAD simulations of the MOSFET is

    achieved by using the oxide thickness 0.02 and

    the p-well doping concentration is 8e12 and the p-

    well implanted using the boron material.

    The drain to source voltage always set to be zero

    because of the gate bias.

    For the planar MOSFET design, silicon stripe

    width WSTRIPE= Physical gate length and silicon

    oxide thickness 0.02. Stripe width is set to be

    0.6*LG is used to suppress the short channel

    effects and fin height HSTRIPE is used to achieve

    the effective channel as the same.

    The Discrete vs. continuous transistor sizing have

    been investigated and this optimization techniques

    ate faster.

    Modeling Parameter

    Comparison of FINFET and MOSFET is

    achieved by using the variation of the gate oxide

    thickness, gate length and doping concentration.

    As compared with the Metal Oxide Semiconductor

    Field Effect Transistor and FINFET of the

    performance is varied by using the Gate oxide

    Thickness, Doping Concentration and Threshold

    voltage.

    So the time of process variation the multi gate

    devices give higher performance than single gate

    devices.

    Conclusion

    FinFET devices are used to replace the traditional

    MOSFETs because of superior ability to control

    the leakage

    Minimizes the short channel effects while

    delivering the drive current. The transistor

    performance can be varied using two categories,

    i.e,. Systematic and Random variations.Systematic variation sources are include process

    induced variations in oxide thickness and Doping

    Concentration.

    Transistor scaling to its ultimate limit, the

    MOSFET and FINFET structures had been

    investigated. I

    In this paper the variations of transistor

    performance is investigated for each structures

    and finally concludes which one is most scalable

    devices.

    Silvaco TCAD simulations of the MOSFET is

    achieved by using the oxide thickness 0.02 and

    the p-well doping concentration is 8e12 and the p-

    well implanted using the boron material. The

    drain to source voltage always set to be zero

    because of the gate bias.

    MOSFET AND FINFET Structure

    Figure 2.3MOSFET Structure

    Objective

    Investigate issues in FINFET independent gate

    biasing as well as sizing of the transistor

    The effects of systematic variations

    LG,WSTRIPE and tox are discussed.

    The multi gate devices threshold voltage is

    dependent on the stripe width it is used to supress

    the short channel effects.

    Threshold voltage increases when increasing the

    oxide thickness

    RESULTS AND DISCUSSION

    Figure 2.1FINFET Structure

    The finFET device is mainly depends on the

    temperature and the gate voltage because

    this device is multi gate device.

    This multi gate device give high performancecompared to other single gate MOSFETs. The

    drain current improves gradually

    Figure 2.2FINFET Gate voltage vs Drain current

    The gate length reduces at that time theperformance increases and also sensitivity.

    http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.cse.iitd.ernet.in/~vls03016/website/courses/micro/finfet_vls03016.doc.pdfhttp://www.cse.iitd.ernet.in/~vls03016/website/courses/micro/finfet_vls03016.doc.pdfhttp://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214http://www.sciencedirect.com/science/article/pii/S0167931708001214