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2013 Master thesis
Process dependent Electrical characteristics of High-k gate
dielectrics on AlGaN/GaN devices
Supervisor
Professor Hiroshi Iwai
Department of Electronics and Applied Physics
Interdisciplinary Graduate School of Science and
Engineering
Tokyo Institute of Technology
11M55440
Jiangning Chen
2
CONTENTS
Chapter 1. Introduction and background
1.1 Gallium nitride-based electronic devices 6
1.2 AlGaN/GaN HEMT devices 7
1.3 Issues in AlGaN/GaN HEMT deivces 8
1.4 Selection of high-k materials 9
1.5 Purpose of this study 9
1.6 Outline of this thesis 10
References 12
Chapter 2. Fabrication and characterization method
2.1 AlGaN/GaN transistors fabrication procedure 15
2.1.1 Device structure 15
2.1.2 Mask layout 17
2.2 Detailed processes 19
2.2.1 AlGaN/GaN surface cleaning 19
2.2.2 Mesa isolation 19
2.2.2.1 Chemical vapor deposition of TEOS 19
2.2.2.2 Photolithography 21
2.2.2.3 Dry etching of AlGaN/GaN 23
2.2.3 Metallization 25
2.2.3.1 Contact metal deposition by RF sputtering 25
3
2.2.3.2 Ohmic contact formation 27
2.2.3.3 Gate electrode formation 29
2.2.4 Gate dielectrics 29
2.2.4.1 High-k materials deposition 29
2.3 Characterization method 30
2.3.1 Leakage current density-voltage (J-V) measurement 31
2.3.2 Capacitance-voltage (C-V) measurement 31
Reference 35
Chapter 3. Electrical characteristics of AlGaN/GaN
devices
3.1 Introduction 37
3.2 Thickness effects on leakage current 37
3.3 Threshold voltage dependence on thickness of High-k films 38
3.4 C-V characteristics 39
3.5 Extraction of effective mobility 40
3.6 Summary of this chapter 41
Chapter 4. Annealing effects on AlGaN/GaN devices
4.1 Introduction 43
4.2 Annealing effects on electrical characteristics 43
4.3 Proposed model for annealing dependent properties 49
4.4 Summary of this chapter 50
4
Chapter 5. Conclusion and future work
5.1 Conclusion 52
5.2 Future work 52
Acknowledgments
5
Chapter 1
Introduction and background
1.1 Gallium nitride-based electronic devices
1.2 AlGaN/GaN HEMT devices
1.3 Issues in AlGaN/GaN HEMT deivces
1.4 Selection of high-k materials
1.5 Purpose of this study
1.6 Outline of this thesis
References
6
1.1 Gallium nitride-based electronic devices
With the wide use of electric products, reduce energy consumption has become more
and more important. Efficient energy is the goal of efforts to reduce the amount of
energy required to provide products and services. Motors are the world’s single largest
consumer of electricity. Reduce energy waste from motors and Energy-efficient
products are necessary.
Power transistors are used as a switching element in power supply circuits such as
which in inverters. Inverters are able to control various types of electric motors by
converting the frequency of the AC power supply. Thus inverters are widely used for
energy-efficient motor control. Therefore, the research and development which enhance
the performance of power transistors for higher energy efficiency systems would bring
great commercial potential [1].
Currently, Si-based insulated gate bipolar transistors (IGBTs) as power transistors
have been the main power electronics for home appliances for several kilowatt regimes,
including fridges, air conditioners, washing machine and so on. But their performance
deteriorates significantly at high temperatures that largely attributable to the modest
banggap of Si (1.12 eV). A strong demand for further improvement in the converter
efficiency over 95 % has required new semiconductor materials with wide energy
bandgap.
7
Table 1.1 Advantages of GaN semiconductor
Among several wide bandgap semiconductors, Gallium nitride (GaN) is an attractive
material which a wide bandgap (3.4eV) for power electronics with high efficiency,
owing to large breakdown voltage, large electron mobility and high thermal
conductivity [2]. Advantages of GaN semiconductor are shown in Table1.1.
1.2 AlGaN/GaN HEMT devices
A main advantage of GaN which better than SiC is ability to form heterostructures
with other group Ⅲ－Ⅴcompounds. The most prevalent HEMT structure is the
AlGaN/GaN HEMT. AlGaN/GaN HEMT structures have lots of advantages over other
wide bandgap semiconductors, owing to high mobility nearly 1000. This high mobility
can be achieved by using two-dimensional electron gas by strains at AlGaN and GaN
8
interface. Of course AlGaN and GaN both have high breakdown voltage about 10 times
higher than that of silicon, so that AlGaN/GaN can be a strong candidate for future
power electronics.
Recently, AlGaN/GaN structures have been epitaxyally grown on Si substrates using
buffer layers. This enables mass production on a large size wafer over 12 inches, so that
high performance power electronics can be realized at low cost. This can be a strong
advantage over epitaxy on silicon carbide or sapphire substrates. In this work,
transistors were fabricated on undoped Al0.25Ga0.75N (26nm) with GaN (1.3m) layers
epitaxially grown on Si (111) wafers.
1.3 Issues in AlGaN/GaN HEMT deivces
There are some limitations associated with AlGaN/GaN structures. AlGaN/GaN
HEMTs intrinsically show a negative threshold voltage, resulting in normally-on
operation. Thus they need a drive circuit to control the gate bias, which can result in
increased circuit complexity and higher costs [1]. Especially in view of power device
applications, normally-off type transistor in which no current flows at no gate bias is
strongly desired for fail-safe operation as well as reduced power consumption [3].
Another issue for AlGaN/GaN is gate leakage current, which increases losses in the
devices and limits the performance of the devices. With the use of gate dielectrics gate
leakage can be suppressed when an insulator with wide bandgap is used. Also, it is
reported that reliability can be improved with the use of gate dielectrics owing to
suppression of nitrogen vacancies. High-k insulators/ oxides on the AlGaN/GaN HEMT
structures have been used to reduce gate leakage current. While the MISFET/MOSFET
structures do not benefit from enhanced electron mobility due to quantum confinement
9
in a 2DEG at low gate bias, it does provide the capability of fabricating normally-off
devices with low gate-leakage current [4].
1.4 Selection of high-k materials
The major factors that limit the performance and reliability of AlGaN/GaN
high-electron mobility transistors (HEMTs) are high gate leakage current [5]. To reduce
the gate leakage current, introduction of gate dielectrics, especially high-k materials, to
form MOSHFET has been shown to be effective [6].
For the selection of gate dielectric materials, mainly we need to consider dielectric
constant, bandgap and interface properties with AlGaN layer. Recently, using SiO2,
Si3N4 and other materials as gate dielectrics were reported [5]. Although SiO2 has
excellent insulating properties, due to low k-value and poor interface quality with
AlGaN layer, SiO2 cannot be used as gate dielectrics. If the interface quality is not good,
the transconductance degradation is expected. Another possibility is electron trapping at
the interface traps [7]. On the other hand, Si3N4 is known to have nice interface
properties, but still the dielectric constant is low. Recently, HfO2 is reported to have
middling interface properties, so that this material can be expected to be one of the
candidates. However, the requirements for selecting gate dielectric material are high
dielectric constant with wide bandgap and fairly nice interface properties.
1.5 Purpose of this study
AlGaN/GaN devices have been focused as candidates for power devices with low
power consumption, owing to its high electron mobility and large breakdown field. The
issue of AlGaN/GaN device is gate leakage current, which increases losses in the device
10
and limits the performance of devices. Recently, High-k gate dielectrics effective for
gate leakage current suppression have been reported owing to wide bandgap. But the
problems of gate dielectrics are reduction in gate controllability, negative threshold
voltage and reduction in transconductance due to this weak gate controllability.
We propose to use lanthanum oxide (La2O3) as gate dielectrics. La2O3 which is one of
the rare earth oxides has been tried as gate dielectric, because it has a wide bandgap of
5.5 eV and a k-value of 23.4. This material is known to react with substrates, including
Si, Ge and InGaAs. One of the features of this material is that reactively formed
interface layers show fairly nice interface properties, so that interface state density of
1010can be achieved for Si and 1011 can be achieved for both Ge and InGaAs.
In this thesis, we use La2O3 as a gate dielectric for AlGaN/GaN devices. Electrical
characterization on AlGaN/GaN devices was investigated in detail.
1.6 Outline of this thesis
The objective of this work is purpose to use La2O3 as a gate dielectric material and
see the electrical properties of AlGaN/GaN devices.
Following the introduction and background made in this chapter, chapter 2
presented the details of the fabrication along with an overview of the transistors
process. The electrical characterization systems used for evaluating the devices are
also described.
The results on electrical characterization of AlGaN/GaN devices are presented in
chapter 3 and chapter 4. The initial electrical characterization of AlGaN/GaN devices
is presented first in chapter 3 and followed by an annealing effects discussion on
electrical characterization in chapter 4.
11
A summary of the thesis work together with discussions on the observed results
and suggestion on future work are presented in Chapter 5.
12
References
[1] Rathnait D. Long and Paul C. McIntype, Materials 2012,5, 1297-1335
[2] W. Saito, et al., IEEE Trans. Electron Devices, Vol. 50, pp. 2528-2531 (2003).
[3] Niiyama, Y., Shinagawa, T. ; Ootomo, S. ; Kambayashi, H. ; Nomura T. ; Kato, S.
High-power operation of normally-off GaN MOSFETs. Furukawa Rev. 2009, 36, 1-5.
[4] Wu, Y. Q. ; Ye, P.D. ; Wilk, G.D. ; Yang, B. GaN metal-oxide-semiconductor
field-effect-transistor with atomic layer deposited Al2O3 as gate dielectric. Mater. Sci.
Eng. B 2006, 135, 282-284.
[5] Yuanzheng Yue, Yue Hao, et al.. IEEE electron device letters, Vol.29, pp 838-840
(2008).
[6] M. A. Khan, et al., IEEE Electron Device Lett., Vol. 21, pp. 63-65 (2000).
[7] Y.Hayashi, S.Sugiura, et al.. Solid-state electronics 54 (2010) 1367-1371.
13
Chapter 2
Fabrication and characterization
method
2.1 AlGaN/GaN transistors fabrication procedure
2.1.1 Device structure
2.1.2 Mask layout
2.2 Detailed processes
2.2.1 AlGaN/GaN surface cleaning
2.2.2 Mesa isolation
2.2.2.1 Chemical vapor deposition of TEOS
2.2.2.2 Photolithography
2.2.2.3 Dry etching of AlGaN/GaN
2.2.3 Metallization
2.2.3.1 Contact metal deposition by RF sputtering
2.2.3.2 Ohmic contact formation
14
2.2.3.3 Gate electrode formation
2.2.4 Gate dielectrics
2.2.4.1 High-k materials deposition
2.3 Characterization method
2.3.1 Leakage current density-voltage (J-V)
measurement
2.3.2 Capacitance-voltage (C-V) measurement
2.3.3 X-ray photoelectron spectroscopy (XPS)
Reference
15
2.1 AlGaN/GaN transistors fabrication procedure
2.1.1 Device structure
Transistors were fabricated on undoped AlGaN (26nm) with GaN (1.3m) layers
epitaxially grown on Si (111) wafers. The device structure is shown in Figure 2.1.
Figure 2.1 Fabrication process flow of AlGaN/GaN transistors.
Figure 2.2 shows the fabrication flow of AlGaN/GaN transistors. After chemical
cleaning of the substrate, a 100nm-thick SiO2 layer was deposited using
plasma-enhanced chemical vapor deposition (PECVD). Mesa isolation was formed by
inductively coupled plasma (ICP) etching with Cl2-based gas. Source and drain contacts
were formed by Ti-based metal and subsequently annealed in N2 ambient at 750oC for
GaN(1.3m)
Al0.25Ga0.75N (26nm)
2DEG
Buffer
W TiN/Ti
Si(111) Substrate
High-kTiN/Ti
GaN(1.3m)
Al0.25Ga0.75N (26nm)
2DEG
Buffer
W TiN/Ti
Si(111) Substrate
High-kTiN/Ti
16
1min. Afterwards, high-k gate materials were deposited by electron-beam evaporation in
an ultra high vacuum at a pressure of 10-6 Pa and at room temperature.
Figure 2.2 Fabrication process flow of AlGaN/GaN transistors.
AlGaN(26nm)/GaN(1.3m) epitaxially grown on Si(111)
SPM and HF cleaning
TEOS (100nm) deposition by CVD (device isolation)
High-k materials deposition by electron beam deposition
Tungsten (W,5nm) deposition by RF sputtering
Gate patterning by reactive ion etching (RIE)
Electrical characterization
Ti/TiN(50nm/50nm) deposition by RF sputtering,750oC(contact formation)
Contact holes formation
in-situ
Mesa isolation by RIE with Cl2
TEOS (100nm) deposition by CVD (passivation layer)
TEOS (100nm) deposition by CVD (contact protection)
17
After high-k deposition, a 50nm-thick tungsten (W) layer was in-situ deposited using
RF magnetron sputtering without exposing the wafers to air to minimize high-k layer
moisture absorption or contamination. The W layer was patterned by web etching using
H2O2 solution to form gate electrodes. Then contact holes to source and drain regions
were formed. An FET using W schottky gate without high-k materials was also
fabricated as a reference. Finally, devices were post-metallization annealed (PMA)
using a rapid thermal annealing (RTA) furnace in forming gas (F.G) (N2:H2=97%:3%)
ambient at various temperatures.
2.1.2 Mask layout
The photolithography mask design was performed using LASI version 6.3.2.4
software. The designed device mask is shown in Figure 2.3.
Figure 2.3 Designed device mask
18
Different size transistors, contact structures and two sets of alignment markers were
designed in every individual cell. In this study, five layers were designed using easy
modification of geometry. They are respectively mesa isolation layer, contact formation
layers, channel layer and gate layer. For transistor patterns, each permutations of gate
length LG was 2 & 5 & 10 & 20 & 25 m and gate width WG was 5 & 10 & 20 & 50 &
100 m. The layout of a single cell was showed in Figure 2.4.
Figure 2.4 Individual cell design for device fabrication.
19
2.2 Detailed processes
2.2.1 AlGaN/GaN surface cleaning
During device fabrication, surface treatment and cleaning conditions are important
and unavoidable. In this study, the wafers were treated by sulfuric-peroxide mixture
(SPM), which involves H2O2: H2SO4 mixture typically in 1:4 for 10min at 150oC.
Subsequent, the wafers were treated by 1%HF for 1 min. This process is effective in
removing surface oxygen and organic contamination.
2.2.2 Mesa isolation
In order to separate each adjacent device, mesa isolation was defined and formed.
After initial cleaning of the surface, the first level of device fabrication was the
formation of mesa isolation. In this study, mesa isolation of the devices was formed by
inductively coupled plasma etching with Cl2-based gas. For these samples, SiO2 was
used as a mask material to protect against plasma etching.
2.2.2.1 Chemical vapor deposition of TEOS
Chemical vapor deposition is a key process used to produce high purity films in the
semiconductor industry. In a typical CVD process, gaseous reactant or liquid reactant
vapor at a reasonable flow is introduced into the reaction chamber, which reacts on the
substrate surface and deposits on the surface [1]. In this work, a 100nm-thick SiO2 layer
was deposited utilizing a liquid TEOS (Tetra Ethyl Ortho Silicate) source at high speed
and low temperature ( Si(OC2H5)4 + 12O2 = SiO2 + 8CO2 + 10H2O ) [2].
20
Figure 2.5 Liquid source CVD system
Plasma-enhanced chemical vapor deposition (PECVD) was used, which is shown in
Figure 2.5. This SAMCO PD-270STP is a unique plasma-enhanced CVD system
utilizing a liquid TEOS source to deposit SiO2 films at high speed using a low
temperature process. The strong sheath electrical field surrounding the cathode-coupled
sample stage generates a high level of ion energy, which enables the deposition of
silicon oxide films with low internal stress, from thin films to thick films. Whose basic
21
Cathode
Anode
Gas
pump
RF
13.56 MHz
Plasma
working principle is shown in Figure 2.6.
Figure 2.6 Schematic illustration of chemical vapor deposition
2.2.2.2 Photolithography
The photolithography process during the device fabrication was utilized in this work.
In a lithographic process usually consists of three major steps, exposure, developing and
etching. First of all, a thin uniform layer of positive photo-resist was formed on the
22
surface of the wafers by high-speed spin coating. Then the samples were baked at a
temperature of 115oC for 5 minutes. Next, the samples were aligned and exposed
through e-beam patterned hard-mask with high-intensity ultraviolet (UV) light at 405
nm wavelength. For positive resists, the resist is exposed with UV light wherever the
underlying material is to be removed. In these resists, exposure to the UV light changes
the chemical structure of the resist so that it becomes more soluble in the developer. The
exposed resist is then washed away by the developer solution, leaving windows of the
bare underlying material. Therefore, contains an exact copy of the pattern which is to
remain on the wafer [3].
Figure 2.7 The photo of photolithography apparatus.
23
After developing process, post-baking process was completed at a temperature of
130oC for 10 minutes. This step is necessary in order to harden the photo-resist and
improve adhesion of the photo-resist to the wafer surface. The photolithography
apparatus used are shown in Figure 2.7.
2.2.2.3 Dry etching of AlGaN/GaN
The two fundamental types of etching methods are liquid-phase (wet etching) and
plasma-phase (dry etching). In this work, wet etching and dry etching were both used.
Buffered hydrofluoric acid (BHF) was used to etch silicon dioxide, which contains HF
and NH4F. Mesa isolation of the devices was formed by inductively coupled plasma
etching with Cl2-based gas. Plasma etching process has been widely used in the
semiconductor manufacturing industry [4]. Typical advantage of using inductively
coupled plasma (ICP) etching over standard reactive ion etching (RIE) is that it could
independently control ICP power and bias power. ICP power and bias power are used to
control the density source of ions which adjusts etching rate.
24
Figure 2.8 SAMCO’s RIE-101iPH system
In this work, SAMCO’s RIE-101iPH was used to perform the mesa etch for the
samples. SAMCO's RIE-101iPH is a manually load-locked type inductively coupled
plasma (ICP) etching system [5], which is shown in Figure 2.8.
The AlGaN/GaN substrates were etched by ICP power 80 W with bias 20 W under a
gas mixture of Cl2/Ar = 20/10 sccm for 2 min. After removing the isolation layer
photo-resist by sulfuric-peroxide mixture (SPM) treatment, mesa isolation of the
devices were formed.
25
2.2.3 Metallization
Metallization is the fabrication step in which proper interconnection of circuit
elements is made. In this work, ohmic metallization formation and gate metallization
formation were completed.
2.2.3.1 Contact metal deposition by RF sputtering
After device isolation was formed by inductively coupled plasma (ICP) etching with
Cl2-based gas, the next process of device fabrication was the formation of contacts.
Titanium and titanium nitride which are used as contact metal were deposited in this
work by radio frequency (RF) magnetron sputtering. Radio frequency (RF) magnetron
sputtering is a process that is used to deposit thin films. The sputtering process is
schematically shown in Figure 2.9.
Figure 2.9 Schematic illustration of RF magnetron sputtering [7]
26
In RF magnetron sputtering, a thin film is grown on a substrate that is placed in a
vacuum chamber. Once the substrate is placed in the vacuum chamber, argon gas is
released into the chamber, the air is removed and the target material, the material that
will comprise the thin film, is released into the chamber in the form of a gas. Particles of
the target material are ionized through the use of powerful magnets. Now in the form of
plasma, the negatively charged target material lines up on the substrate to form a thin
film. Thin films can range in thickness from a few to a few hundred atoms or molecules
[6]. The sputtering system used in this work is shown in Figure 2.10.
Figure 2.10 RF magnetron sputtering system
27
In this work, the ohmic metal stack that was used was Ti/TiN (50nm/50nm). TiN film
in this work was produced by reactive sputtering. N2 gas was also introduced into the
chamber in this case and reacts with Ti target to form nitride film.
2.2.3.2 Ohmic contact formation
Ohmic contact formation involved contact metal deposition by radio frequency (RF)
sputtering, lithographic pattern formation of a photo-resist layer, ICP-RIE etching and
photo-resist removal and rapid thermal annealing (RTA).
Ti/TiN (50nm/50nm) contacts deposition were formed by sputtering. After deposition
completion, source and drain pattern were formed by ICP power 80 W with bias 20 W
under a gas mixture of Cl2/Ar = 30/10 sccm for 2 min. Photo-resist layer was removed
by O2 based ashing method inside the same ICP-RIE system. After removing the contact
layer photo-resist, the annealing was performed in N2 ambient at 750oC for 1min.
Source and drain contacts required heat treatments to form ohmic contacts. So rapid
thermal annealing (RTA) of the ohmic contact layer was performed in this work. Rapid
thermal annealing system was shown in Figure 2.11.
28
Figure 2.11 Rapid thermal annealing system
Rapid thermal annealing is an important fabrication process for the ohmic contact
formation, which heats wafers to a high temperature in a short time of several seconds.
Samples were loaded on to a Si carrier wafer in the annealing chamber and purged with
N2 ambient. As a result of a cumulative annealing study, it was found that the optimal
temperature for annealing of ohmic metal stack was 750oC for 1min. Samples were
29
taken out of the chamber under 1000C. After annealing, ohmic contact was confirmed
using leakage current density – voltage (J-V) measurement.
2.2.3.3 Gate electrode formation
Gate contact formation also involved gate metal deposition by sputtering,
lithographic pattern formation, wet etching and photo-resist removal.
In this work, a 50 nm W film was deposited by radio frequency (RF) magnetron
sputtering to form gate electrode. The base pressure of the sputtering chamber was
maintained at 10-6 Pa during the substrate transfer. Ar gas flow was set to 7sccm and the
150 W RF current power used to produce plasma.
Metal etching is performed by H2O2 solution for 2min.
2.2.4 Gate dielectrics
In order to suppressed the gate leakage current of AlGaN/GaN HEMT structure,
High-k gate dielectrics were deposited in ultra high vacuum by electron-beam
evaporation method.
2.2.4.1 High-k materials deposition
Molecular beam epitaxy (MBE) is used extensively in the semiconductor industry to
deposit thin films. In this work La2O3 thin film was deposited by e-beam evaporation at
room temperature. Figure 2.12 shows the schematic illustration of MBE equipment used
in this investigation. The pressure in the MBE chamber during depositions was
10-7~10-5 Pa. Electron beam, which is accelerated by a 5 KV electric field, is generated
and bombard to the source under the control of a magnetic sweep controller. Film
30
thickness counter is used for physical film thickness in real time. The growth rate of the
thin film is controlled at 0.003 A/s to 0.005 A/s to ensure a relatively high quality.
Figure 2.12 Schematic illustration of MBE equipment
2.3 Characterization method
Electrical characteristics were determined by leakage current density-voltage (J-V)
measurement and capacitance-voltage (C-V) measurement.
31
2.3.1 Leakage current density-voltage (J-V) measurement
J-V measurement was performed using HP4156A semiconductor parameter analyzer.
In order to tracing the switching behaviors, a sweep voltage started at -5V and sweep
towards 0V, whose step is 0.05V.
2.3.2 Capacitance-voltage (C-V) measurement
C-V characteristic measurements were performed with various frequencies
(1KHz~1MHz) by precision LCR Meter (HP 4284A, Agilent).
VG
NA
0 tox tox+W x
Vox
φs
φF
Ec/q
Ei/q, φ
Ev/qEF/q, φF
Figure 2.13 Cross-section and potential band diagram of an MOS capacitor.
32
The energy band diagram of an MOS capacitor on a p-type substrate is shown in
Figure 2.13. The intrinsic energy level Ei or potential φin the neutral part of
device is taken as the zero reference potential. The surface potential φs is
measured from this reference level. The capacitance is defined as
dV
dQC (2.3.2.1)
It is the change of charge due to a change of voltage and is most commonly given
in units of farad/unit area. During capacitance measurements, a small-signal ac
voltage is applied to the device. The resulting charge variation gives rise to the
capacitance. Looking at an MOS-C from the gate, GG dVdQC / , where GQ and
GV are the gate charge and the gate voltage. Since the total charge in the device
must be zero, )( itsG QQQ assuming no oxide charge. The gate voltage is
partially dropped across the oxide and partially across the semiconductor. This
gives soxFBG VVV , where FBV is the flatband voltage, oxV the oxide
voltage, and s the surface potential, allowing Eq.(2.3.2.1) to be rewritten as
sox
its
ddV
dQdQC
(2.3.2.2)
The semiconductor charge density sQ , consists of hole charge density pQ ,
space-charge region bulk charge density bQ , and electron charge density nQ .
With nbps QQQQ , Eq. ( 2.3.2.2) becomes
itnbp
s
its
ox
dQdQdQdQ
d
dQdQ
dVC
1
(2.3.2.3)
Utilizing the general capacitance definition of Eq. ( 2.3.2.1), Eq. ( 2.3.2.3) becomes
33
itnbpox
itnbpox
itnbpox
CCCCC
CCCCC
CCCCC
C
)(
111
(2.3.2.4)
The positive accumulation charge pQ dominates for negative gate voltages for
p-substrate devices. For positive GV , the semiconductor charge are negative. The
minus sign in Eq.( 2.3.2.3) cancels in either case.
Equation (2.3.2.4) is represented by the equivalent circuit in Figure 2.14 (a). For
negative gate voltages, the surface is heavily accumulated and pQ dominates. pC
is very high approaching a short circuit. Hence, the four capacitances are shorted as
shown by the heavy line in Figure 2.14 (b) and the overall capacitance is oxC . For
small positive gate voltages, the surface is depleted and the space-charge region
charge density, WqNQ Ab , dominates. Trapped interface charge capacitance
also contributes. The total capacitance is the combination of oxC in series with
bC in parallel with itC as shown in Figure 2.14 (c). In weak inversion nC
begins to appear. For strong inversion, nC dominates because nQ is very high. If
nQ is able to follow the applied ac voltage, the low-frequency equivalent circuit
(Figure 2.14 (d)) becomes the oxide capacitance again. When the inversion charge
is unable to follow the ac voltage, the circuit in Figure 2.14 (e) applies in inversion,
with invsb WKC /0 with invW the inversion space-charge region width [8].
34
Cox
Cp CbCn Cit
Cox
Cp CbCn Cit
Cox
Accumulation
(b)
Cox
Cp CbCn Cit
Cox
CbCit
Depletion
(c)
Cox
Cp CbCn Cit
Cox
Inversion- Low Frequency
(d)
Cox
Cp CbCn Cit
Cox
Cb
Inversion- High Frequency
(e)
(a)
Figure 2.14 Capacitance of an MOS capacitor for various bias conditions.
35
Reference
[1] http://en.wikipedia.org/wiki/Chemical_vapor_deposition
[2] http://www.samcointl.com/
[3] http://www.ece.gatech.edu/research/labs/vc/theory/photolith.html
[4] M. A. Lieberman, A. J. Lichtenberg, Principles of Plasma Discharges and Materials
Processing, 2nd ed, Wiley-Inter science, New York, Wiley, 2005.
[5] http://www.samcointl.com/products/01_etching/02_icp/rie-101iph.php
[6] http://www.wisegeek.com/what-is-rf-magnetron-sputtering.htm
[7] http://upload.wikimedia.org/wikipedia/en/7/72/Sputtering.gif
[8] D. Schroder, Semiconductor material and device characterization, 3rd edition, p.
347-350, Willey Inter science, NJ (2006).
36
Chapter 3
Electrical characteristics of
AlGaN/GaN devices
3.1 Introduction
3.2 Thickness effects on leakage current
3.3 Threshold voltage dependence on thickness
of High-k films
3.4 C-V characteristics
3.5 Extraction of effective mobility
3.6 Summary of this chapter
References
37
3.1 Introduction
This chapter will introduce the measured results and discuss each type of electrical
characteristics that was used in this study.
3.2 Thickness effects on leakage current
Figure 3.1 shows gate leakage current with different La2O3 thickness at gate voltage
of 1 V. The thickness of the devices with La2O3 films was set 3nm, 6nm and 9nm. Gate
leakage current was suppressed when the thickness of La2O3 is over 6 nm. For
3nm-thick La2O3 a slight increase in gate leakage current was observed. This might be
due to change in the band offset from metal/AlGaN to metal/ La2O3.
Figure 3.1 Gate leakage current with different La2O3 thickness
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0 5 10 15
Thickness of La2O3 (nm)
J g(A
/cm
2) Vg=1V
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0 5 10 15
Thickness of La2O3 (nm)
J g(A
/cm
2) Vg=1V
38
3.3 Threshold voltage dependence on thickness of
High-k films
Threshold voltage with different La2O3 thickness is shown in Figure 3.2. Usually,
when the thickness of gate dielectric is increased, the threshold voltage shifts to
negative direction due to weak coupling to the channel. However, this result almost no
dependency in threshold voltage with La2O3 thickness.
Figure 3.2 Threshold voltage with different La2O3 thickness
-4-3.5
-3-2.5
-2-1.5
-1-0.5
0
0 5 10 15
Thickness of La2O3 (nm)
Vth
(V)
-4-3.5
-3-2.5
-2-1.5
-1-0.5
0
0 5 10 15
Thickness of La2O3 (nm)
Vth
(V)
39
3.4 C-V characteristics
Gate to channel capacitances were measured by split-CV measurement. Figure 3.3
shows initial C-V characteristics with different La2O3 thickness. The devices can be
operated in the range of voltage from -5 V to 0 V. Largest capacitance was obtained with
Schottky gate, but while increasing the thickness of La2O3, we see an irregular order for
capacitances.
Figure 3.3 C-V characteristics with different La2O3 thickness
Gate Voltage (V)
Cap
acita
nce
dens
ity (F
/cm
2)
-3-50
0.05
0.1
0.15
-4 0-6 -1-2
0.25
0.3
0.35
0.2
0.4
Schottky
9nm
3nm
6nm
Gate Voltage (V)
Cap
acita
nce
dens
ity (F
/cm
2)
-3-50
0.05
0.1
0.15
-4 0-6 -1-2
0.25
0.3
0.35
0.2
0.4
Schottky
9nm
3nm
6nm
40
3.5 Extraction of effective mobility
Gallium nitride (GaN) is generation semiconductor material candidate except which
has a wide bandgap (3.4eV) for power electronics, another important condition is large
electron mobility. AlGaN/GaN HEMT structures have lots of advantages over other
wide bandgap semiconductors, also owing to high mobility nearly 1000. Figure 3.4
shows the mobility of 6nm-thickness La2O3 gate dielectric. High effective electron
mobility is obtained with La2O3 gate dielectric.
Figure 3.4 Effective mobility dependency on sheet electron concentration
0
200
400
600
800
1000
1200
1400
0.0E+00 1.0E+12 2.0E+12 3.0E+12
Charge density (/cm2)
Eff
ectiv
e m
obili
ty (
cm2/V
s)
Lg=10m, Wg=50mtLa2O3(6nm)
0
200
400
600
800
1000
1200
1400
0.0E+00 1.0E+12 2.0E+12 3.0E+12
Charge density (/cm2)
Eff
ectiv
e m
obili
ty (
cm2/V
s)
Lg=10m, Wg=50mtLa2O3(6nm)
41
3.6 Summary of this chapter
In this chapter, thickness dependence of La2O3 gate dielectrics on electrical
characteristics for AlGaN/GaN MOSHEMT has been investigated. The reduction in gate
leakage current is suppressed when the thickness of La2O3 gate dielectric is over 6 nm.
With thicker gate dielectrics, usually threshold voltage shifts to negative direction but
this measured result almost no dependency in threshold voltage with La2O3 thickness.
High mobility about 1200 cm2/Vs is obtained. A nice FET operation with La2O3 gate
dielectric is confirmed.
42
Chapter 4
Annealing effects on AlGaN/GaN
devices
4.1 Introduction
4.2 Annealing effects on electrical characteristics
4.3 Proposed model for annealing dependent
properties
4.4 Summary of this chapter
References
43
4.1 Introduction
Annealing conditions such as annealing time and annealing temperature affects
strongly electrical characteristics of devices. This chapter will discuss annealing in
forming gas (H2:3%, N2:97%) effects on AlGaN/GaN device, which consist of threshold
voltage, capacitance and so on. The reaction on high-k gate dielectric and AlGaN layer
surface by annealing will be discussed. Finally, we propose a model to explain these
experimental results.
4.2 Annealing effects on electrical characteristics
Figure 4.1 shows output characteristics and transfer characteristics of AlGaN/GaN
device with La2O3 gate dielectrics.
Figure 4.1 (a) Output characteristics of AlGaN/GaN device
0
0.0002
0.0004
0.0006
0.0008
0.001
0.0012
0 0.5 1 1.5 2
Drain voltage (V)
Dra
in c
urre
nt (
A)
Vth+0.5V
Vth+1.0V
Vth+1.5V
Vg=Vth+2.0V
0
0.0002
0.0004
0.0006
0.0008
0.001
0.0012
0 0.5 1 1.5 2
Drain voltage (V)
Dra
in c
urre
nt (
A)
Vth+0.5V
Vth+1.0V
Vth+1.5V
Vg=Vth+2.0V
44
Figure 4.1 (b) Transfer characteristics of AlGaN/GaN device
For this case, 6-nm-thick La2O3 was used as gate dielectrics. A fairly nice
Subthreshold voltage swing value was obtained. The sample was annealed at 300oC for
10 min in forming gas ambience (H2:3%, N2:97%). Drain current-gate voltage
characteristics and transfer characteristics of AlGaN/GaN device shows a nice FET
operation with La2O3 MOS HEMT.
Figure 4.2 shows the C-V characteristics dependent on the temperature of annealing
for La2O3 gate dielectrics. The devices were annealed for 10 min in forming gas
ambience (H2:3%, N2:97%) and annealing temperature from 300oC to 725oC was
investigated. Gate to channel capacitance of the devices were measured at 1MHz by
split capacitance-voltage measurements. The figure shows the capacitance density at
Gate Voltage (V)
Dra
in c
urre
nt (
)
-2-4-6 2010-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
SS=65.1 mV/dec.
Vd=50mV
Vd=1V
Annealed at 300oC
Gate Voltage (V)
Dra
in c
urre
nt (
)
-2-4-6 2010-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
SS=65.1 mV/dec.
Vd=50mV
Vd=1V
Annealed at 300oC
45
gate voltage of 0V, increase in capacitance value can be observed while increasing the
annealing temperature. For Schottky gate only an increase of a few percent was
observed, however, for samples with La2O3 gate dielectrics, which have a huge increase
in capacitance, especially with thicker La2O3 film after 500oC.
Figure 4.2 C-V characteristics dependent on annealing temperature process
Figure 4.3 shows the CV curves with 300oC annealing. Gate to channel capacitance
Annealing temperature (oC)
Cap
acita
nce
den
sity
(F
/cm
2)
0 8006004002000.2
0.25
0.3
0.4
0.35
0.45
Annealing temperature (oC)
Cap
acita
nce
den
sity
(F
/cm
2)
0 8006004002000.2
0.25
0.3
0.4
0.35
0.45
Vg=0V
Schottky
9nm
3nm
6nm
FGA 10min
Annealing temperature (oC)
Cap
acita
nce
den
sity
(F
/cm
2)
0 8006004002000.2
0.25
0.3
0.4
0.35
0.45
Annealing temperature (oC)
Cap
acita
nce
den
sity
(F
/cm
2)
0 8006004002000.2
0.25
0.3
0.4
0.35
0.45
Vg=0V
Schottky
9nm
3nm
6nm
FGA 10min
46
of the devices were measured at 100 kHz by split capacitance-voltage measurements.
Largest capacitance was obtained with Schottky gate, the capacitance value decreases
with the thicker La2O3 film. Figure 4.4 shows the C-V characteristics dependent on
annealing time. Gate to channel capacitance were measured at 100 kHz and the samples
were annealed at 550 oC. The capacitance for all the samples only increases a few
percent on annealing time from 10 min to 30min. After annealing time of 60min, the
capacitance values almost were unchanged with increasing the annealing time.
Figure 4.3 C-V characteristics at 300oC annealing
Gate Voltage (V)
Cap
acita
nce
dens
ity (F
/cm
2)
-3-50
0.05
0.1
0.15
-4 0-6 -1-2
0.25
0.3
0.35
0.2
0.4
Schottky
9nm
3nm
6nm
annealed at 300oC
Gate Voltage (V)
Cap
acita
nce
dens
ity (F
/cm
2)
-3-50
0.05
0.1
0.15
-4 0-6 -1-2
0.25
0.3
0.35
0.2
0.4
Gate Voltage (V)
Cap
acita
nce
dens
ity (F
/cm
2)
-3-50
0.05
0.1
0.15
-4 0-6 -1-2
0.25
0.3
0.35
0.2
0.4
Schottky
9nm
3nm
6nm
annealed at 300oC
47
Figure 4.4 C-V characteristics dependent on annealing time at 550oC
Transfer characteristics of the device with La2O3 gate dielectrics are shown in Figure
4.5. In this case, 6nm-thick La2O3 was used as gate dielectrics. Threshold voltage shifts
to positive direction with high temperature annealing can be observed.
Figure 4.6 shows threshold voltage dependent on annealing temperature for
6nm-thick La2O3. The device was annealed for 10 min in forming gas ambience (H2:3%,
N2:97%) and annealing temperature from 300oC to 625oC was investigated. The
threshold voltage of -3.81V with annealed at 300oC was shifted to -3.09V at 625oC.
Annealing time (min)
Cap
acita
nce
den
sity
(F
/cm
2)
90300.2
0.25
0.3
0.4
0.35
0.45
60 1200
Annealing time (min)
Cap
acita
nce
den
sity
(F
/cm
2)
90300.2
0.25
0.3
0.4
0.35
0.45
60 1200
Vg=0VSchottky
9nm
3nm
6nm
FGA 550oC
Annealing time (min)
Cap
acita
nce
den
sity
(F
/cm
2)
90300.2
0.25
0.3
0.4
0.35
0.45
60 1200
Annealing time (min)
Cap
acita
nce
den
sity
(F
/cm
2)
90300.2
0.25
0.3
0.4
0.35
0.45
60 1200
Vg=0VSchottky
9nm
3nm
6nm
FGA 550oC
48
Figure 4.5 Transfer characteristics on annealing temperature
Figure 4.6 Threshold voltage dependency on annealing temperature
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
-6 -4 -2 010-8
10-7
10-6
10-5
10-4
675o
300o
500o
La2O3(6nm)Dra
in c
urre
nt
[A]
Gate voltage [V]
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
-6 -4 -2 010-8
10-7
10-6
10-5
10-4
675o
300o
500o
La2O3(6nm)
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
-6 -4 -2 010-8
10-7
10-6
10-5
10-4
675o
300o
500o
La2O3(6nm)Dra
in c
urre
nt
[A]
Gate voltage [V]
-4
-3.5
-3
-2.5
300 400 500 600 700
Annealing temperature (oC)
Thr
esho
ld v
olta
ge (
V) La2O3(6nm)
Vth
-4
-3.5
-3
-2.5
300 400 500 600 700
Annealing temperature (oC)
Thr
esho
ld v
olta
ge (
V) La2O3(6nm)
Vth
49
4.3 Proposed model for annealing dependent properties
Based on these experiment results, we propose a model to explain the stable threshold
voltage and capacitance increase with annealing, which is showed in Figure 4.7.
Figure 4.7 A model for annealing dependent properties
We propose that there are reactions at La2O3 and AlGaN layer to form LaGaO. As the
k-value of AlGaN is as low as 9, the reactively formed layer may have higher k-value
than that of AlGaN because of mixture with La2O3. With higher temperature annealing,
the thickness of LaGaO layer may increase and the thickness of AlGaN layer will be
consumed.
We illustrate the relation of threshold voltage with thickness of gate dielectrics.
Threshold voltage shifts to negative direction with thicker gate dielectrics. When we use
an epi-wafer with thick AlGaN layer, the threshold voltage also shifts to negative
direction. When La2O3 make reaction to consume AlGaN layer, the threshold voltage
will move to positive direction, but with the increase in gate dielectric, there is a balance
GaN
AlGaN
GaN
AlGaN
La2O3
GaN
AlGaN
La2O3
GaN
AlGaN
La2O3
annealing annealing
LaGaO LaGaOk=8.7
k=23.4Thickness of gate dielectrics
Vth
AlGaN
thin
thick
annealing
initial
50
to shift back the threshold voltage.
4.4 Summary of this chapter
In this chapter, electrical characteristics on AlGaN/GaN devices after annealing
process have been investigated. Capacitance increase with annealing suggests interface
reaction at La2O3/AlGaN layer. Threshold voltage shift to positive direction with
increasing annealing temperature. We proposed a model to explain these results.
51
Chapter 5
Conclusion and future work
5.1 Conclusion
5.2 Future work
52
5.1 Conclusion
In this thesis, we studied AlGaN/GaN devices with high-k gate dielectrics owing to
wide bandgap and high k-value. The fabrication of AlGaN/GaN HEMT devices were
presented in detail. Electrical characteristics of AlGaN/GaN devices with La2O3 gate
dielectrics have been investigated and annealing effects on electrical characteristics of
AlGaN/GaN devices also were discussed. Capacitance increase and threshold voltage
shift to positive direction with increasing annealing temperature were observed. We
proposed annealing process suggests interface reaction at La2O3/AlGaN layer to form a
new layer and make a model to explain these results.
5.2 Future work
In this work, we proposed a model for annealing dependent properties. In order to
examine the formation of interfacial layer, chemical bonding configuration analyzed
need to be clear. Electrical characteristics such as threshold voltage shift to positive
direction, gate leakage current, gate controllability and mobility should be focus for the
next step of this study.
53
Acknowledgments
I would like to express deep gratitude to my supervisor Prof. Hiroshi Iwai at Tokyo
Institute of Technology for the strong support on my research.
I also would like to sincerely thanks to Prof. Takeo Hattori, Prof. Kenji Natori, Prof.
Kazuo Tsutsui, Prof. Nobuyuki Sugii, Prof. Akira Nishiyama, Prof. Yoshinori Kataoka,
Prof. Parhat Ahmet for their useful advices and patient help.
Special thanks Prof. Kuniyuki Kakushima for kind guidance and discussion at
literally every step of the study.
I also want to appreciate all members of Professor Iwai’s laboratory, for the kind
friendship and help and advice at experimental procedures.
Finally, I would like to thanks my parents, and all of my family members, for their
always warm support.
Jiangning Chen
January 2013
