Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches

Probabilistic Design Methodology to Improve Run-time Stability and Performance

of STT-RAM CachesXiuyuan Bi(1), Zhenyu Sun(1), Hai Li(1)

and Wenqing Wu(2)

(1)University of Pittsburgh(2)Qualcomm Inc.

1

2

Introduction• Spin-transfer torque random access memory (STT-RAM):

• Challenges: Write errors.

• In this work:– Reduce write errors.– Improve write performance.

STT-RAM SRAMNon-VolatilityLow LeakageCell SizeAccess SpeedEndurance

3

Outline

• STT-RAM Basics

• Asymmetric Bit Error Rate

• Probabilistic Design Techniques

– WRAP and VOW

• Hybrid STT-RAM Cache Hierarchy

• CONCLUSION

4

Free Layer

Barrier

Reference Layer

STT-RAM Basics – Cell

• STT-RAM Cell:– Transistor and MTJ (Magnetic Tunnel Junction);

• MTJ:– Free Layer and Ref. Layer;– Read: Direction → Resistance;– Write: Current → Direction.

Parallel (RLow), 0

Anti-Parallel (RHigh), 1

Write-0

Write-1

5

STT-RAM Basics – Stochastic Switching

• Switching (writing) time of MTJ:– Random;

• Write errors:– Unsuccessful switching;

• To reduce error:– Longer write time;– Larger write current.

10 20 30 40 50

Switching time (ns)

6

Outline

• STT-RAM Basics



– WRAP and VOW


• CONCLUSION

7

Asymmetric Bit Error Rate

• Write-1 vs. Write-0:

• With same write time:– Write-1 has higher

bit error rate (BER)

VGS=VDD-IRL

I0→1

VGS=VDD

G(VDD)

VDD

0

RHI1→0

G(VDD)

VDD

0

RL

Write-‘0’ Write-‘1’

(a) (b)

MTJ

BiasingCondition

Write-1 Harder

8


• Temperature:

• Process Variations:– Larger impact on Write-1.

T Current BER

9


• Sub-Block:

• sub-BLock Error Rate (BLER):– Data pattern:

– Strength of ECC:None < Hamming < BCH

64b 64b …… 64b

Block (64 Byte)

Sub-Block (64 bit)

N0→1 BLER

10

Outline

• STT-RAM Basics



– WRAP and VOW


• CONCLUSION

11

Probabilistic Design

• How to reduce the write errors?• Conventional Design:

– Extend write time (Globally);– Use ECC;– Cons:

• High latency/energy.• Still high error rate.

• Proposed probabilistic design:– WRAP and VOW– High performance, low energy, low write error rate.

Error

Latency/energy

Conv.Design

ProposedDesign

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Probabilistic Design -- WRAP

• Write-verify-Rewrite with Adaptive Period (WRAP):

• Zero write error rate.• Total latency:

Write Read

Not Match

Compare Donematch

13


• Optimal write pulse width τopt exists.– τopt affected by N0->1 :

• Tracing N0->1 is costly.– Using Hamming Weight to estimate N0->1

Write Pulse (τ) BLER Niter

14

τ

...

Ham

min

g W

eigh

t

Temperature(K)325 335 ... 375

0

1

2-8

37-64

LUT

WriteDriver

Temp.Sensor

HammingWeigt

Calculator

STT-RAMArray

Read CircuitLocal FSM & Comprator

CacheController

Bank

Write Data

Done

(a) (b)

9-36

opt


• τopt configuration:– Stored in look up table;– 0, 1, 2~8, 9~36, 37~64;– Temperature influence included;

• Circuit Diagram:

τ

...

Ham

min

g W

eigh

t

Temperature(K)325 335 ... 375

0

1

2-8

37-64

LUT

WriteDriver

Temp.Sensor

HammingWeigt

Calculator

STT-RAMArray

Read CircuitLocal FSM & Comprator

CacheController

Bank

Write Data

Done

(a) (b)

9-36

opt

15


• Performance overhead:– Selecting τopt :

• No overhead.– Verify operation:

• Same location, only 1.47ns for each verify.• High performance.

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Probabilistic Design -- VOW

• For WRAP:– Verify stops the writes.

• Further improve performance:– Write & verify simultaneously.

• Major Challenge:– Total 4 possible voltages.– Frequently pre-charge.

Write Verify Write Verify

Write

Verify

Write current

SL

Ref

done

SA

Write Driver

RH/RL

Pre-Charge Sense SensePre-Charge

Write Verify Write Verify

Write

Verify

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• Solution:– Only verify write-1s.

• When Write-1s finishes:– BER0 extremely low.

• Verify One only:– Write-1s finish: stop;– Low sense complexity;– One-time precharge.

Write current

SL

Column Selection

Ref

WriteBit<X>

done<X> done<0>

done

...

... SA

Verify_En

BE

R

Verify_En=1Pulse Width

Write ‘1’ complete0%

BER0 < 1E-10

Write all bitsVerify write 1

Stop

18


• Asymmetric Sense Amplifier (ASA):– Track the 0->1 switch;– Pre-charged to a sub-stable state;– Once switched to 1, OUT goes high.

Ref

OUTOUT

IN

SAEN

PC

Strong PMOS

PC: Precharge

Strong NMOS

Verification

Write done PC

SAEN: Sense Enable

Cell 0->10.8

0.7

2

1

0

2

1

0

Precharge SAEN

Ctrl

INO

UT

0 2 4 6 8 10Time (ns)

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Probabilistic Design -- Evaluation

• Baselines:

– Other baseline: RWRV.• Error Rate:

20


• Write Latency:

• Write Energy:

21


• Evaluation summary (vs. Hamming):– WRAP:

• Zero Write Error; 40% less latency.– VOW:

• Reduce error by 1011; 52% less latency (vs. Hamming).

22

Outline

• STT-RAM Basics



– WRAP and VOW


• CONCLUSION

23

Hybrid Cache Hierarchy

• Using VOW as higher level cache:– Higher performance;– May contains errors, use parity check;

• WRAP as Lower level cache:– Provide golden copy.

Core1 Core2 Core3 Core8

L1 L1 L1 L1

L2 L2 L2 L2

SRAM

VOWSTT-RAM

(1 bit parity)

WRAPSTT-RAM

...

...

...

Write-back

Write-Through

16+16K

256K

8MB L3

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• Baselines: Base-B and Base-T:– Both use Hamming Code for write error protection;– Base-B : L2 write-back;– Base-T : L2 write-through.

• Evaluation Results:– Reduce write error rates by 10-18;– Higher performance (6.8%), Lower energy cost (15%).

25

Outline

• STT-RAM Basics



– WRAP and VOW


• CONCLUSION

26

Conclusion

• STT-RAM has random write errors;

• Write-1 has higher error rate than write-0;

• Two probabilistic design proposed to reduce write error while improve performance:– WRAP and VOW.

• A hybrid cache hierarchy is proposed to reduce error rate while improve system performance.

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Thanks. Question?

backup

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• Write failure probability (WFP):

• Performance:

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• Energy:

• Evaluation Results:– Reduce write error rates by 10-18;– Higher performance (6.8%) and Lower energy cost (15%).

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Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches