Principles OfDigital Design

Technology Mapping

Mapping Boolean Expressions to Gates

Mapping to NAND and NOR Gates Delay Minimization

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine2

Technology Mapping for Gates Some implementation technology usually have a

library with only one type of gate (such as 3-input NOR, or 3-input NAND)

Technology mapping is a transformation of Boolean expressions into a logic schematic containing only given type(s) of gate(s)

Technology mapping consist of three tasksConversion replaces each operator with an operator

representing the gate function given in the gate arrayOptimization eliminates unnecessary invertersDecomposition replaces a n-input gate with an m-input

gate available in the library

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine3

Conversion and OptimizationRule 1:

Rule 2:

Rule 3:

Rule 4:

Rule 5:

Conversion Procedure: Replace AND and OR gates with NAND or NOR gates by

using Rules 1 – 4, and eliminate double inverters whenever possible

Conversion Rules

Optimization Rules

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine4

Translation of Standard Terms to NAND and NOR Schematics

Form Type Standard Form Implementation NAND Implementation NOR

Implementation

Sum of products

Product of sums

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine5

Conversion to NAND (NOR) GatesExample: Conversion to NAND (NOR) gates

Problem: Derive the NAND and NOR implementations of thecarry function

ci + 1 = xiyi+ xici + yicici + 1 = (xi + yi)(xi + ci)(yi + ci)

0 1 3 2

4 5 7 6

10110100

1

0

xiyi

ci

Map Definition Carry Function ci + 1

1 1

1

1

Standard Forms

NAND Implementation

NOR Implementation

xi

yi

ci

xi

yi

ci

xi

yi

ci

xi

yi

ci

ci + 1 ci + 1

ci + 1 ci + 1

1.4

1.4

1.4

2.4

2.4

2.4

1.82.8

1.4

1.4

1.4

1.8

2.4

2.4

2.4

2.8

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine6

Decomposition of 10–input into 3–input Gates

Level Number

Numberof Inputs

Number of Gates

1 10 [10 / 3] = 3

2 3 + (10 – 3([10 / 3])) = 4 [4 / 3] = 1

3 1 + (4 – 3([4 / 3])) = 2 [2 / 3] = 1

Input and Gate Computation on Each Level

One Possible Decomposition Alternative Decomposition

2.4 2.4

2.4

2.4 2.4 2.4 2.4

2.4

2.4 2.4

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine7

xiyi

ci

Technology Mapping for Gates

0 1 3 2

4 5 7 6

10110100

1

0

Map for Sum Function si

1

1

1

Example: Technology mapping for gates

Problem: Implement the sum function with 3–input NAND gates

1AND–OR Implementation

OR Gate Decomposition

Conversion to NAND Network

Optimized NAND Network

xi yici

si

xi yici

si

xi yici

si

xi yici

si

[x + y = (x’ y’)’]

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine8

c4c4

c4

Design RetimingExample: Design retiming

Problem: Implement 4–bit carry-look-ahead functionusing 3–input NAND gates

g3

g2

g1

p3

c0

p1p2p0

p2p3

p3

p1

p2

g0

p3

c4

g3

g2

g1

p3

c0

p1p2

p0

p2p3

p3

p1

p2

g0

p3

c4

g3

g2

g1

p3

c0

p1p2

p0

p2p3

p3

p1

p2

g0

p3

g3

g2

g1

p3

c0

p1p2

p0

p2p3

p3

p1

p2

g0

p3

g3

g2

g1

p3

c0

p1p2

p0

p2p3

p3

p1

p2

g0

p3

Decomposition of AND-OR Implementation

AND-OR Implementation

Performance Optimized Decomposition

NAND Implementation of Above, Delay = 8.2ns Performance Optimized NAND Implementation, Delay = 6.4ns

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.81.8

1.8

1.8

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine9

Technology Mapping ProcedureStart

Convert

Decompose

Eliminate inverters

Retime

yes

no

I/O delay OK? Done

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine10

Technology Mapping for Custom Libraries

Libraries contain gates with different functions and different delays

Technology mapping means covering schematic with library gates

Primary goal: Minimize delay on critical paths

Secondary goal: Minimize cost on non-critical paths

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine11

Mapping for Custom LibrariesExample: Technology mapping for custom libraries

Problem: Implement the expression w′ z′ + z(w + y) with the logic gates defined earlier

y

wz

F

y

wz

F

AND–OR Implementation (Delay = 7.2ns, Cost = 28)

Cost Optimized Alternative B (Delay = 3.8ns, Cost = 18)

2.4

2.4

2.4

2.4

y

wz

F

NAND Implementation (Delay =5.2ns, Cost = 22)

1.4

1.4

1.4

1.4

y

wz

F

Two Possible Conversions

1.4

1.4

1.4

1.4

y

wz

F

Alternative A (Delay = 5.4ns, Cost = 20)

1.4

2.0

2.0

y

wz

F

Alternative B (Delay = 3.8ns, Cost = 20)

2.0

1.4

1.4

1.41.4

AB

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine12

Conversion Procedure for Custom Libraries

Start

Select a pathConvert to NAND schematic Select gate Select a library

componentRecord

replacement gain

Select maximum gain replacementRecompute Delay

All paths

considered?

Done

yesyes

no no

All gates

considered?

All components considered?

no

yes

Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE 31, University of California, Irvine13

Summary

Technology mapping for NAND/NOR gates

Decomposition Conversion Optimization Retiming

Technology mapping for custom libraries by schematic covering with complex gates with

Time optimization on circuit paths Cost optimization on non-critical paths