Principles and Practices of Digital Current Regulation for

AUPEC 2017Tutorial

Principles and Practices of Digital Current Regulation for AC Systems

Professor Grahame Holmes

Dr Brendan McGrath

RMIT Smart Energy Systems 2AUPEC 2017 Tutorial

Summary

• Power electronic AC conversion systems require precise current regulation with high bandwidth

• Conventional wisdom: Stationary Frame PI regulator gains can never be set high enough to

get acceptably small steady state error Synchronous Frame (P+Resonant) control is mandatory

• Unresolved question:What are the stationary frame PI gain limits? - simple theory says they can be arbitrarily large without regulator instability

• Answering this question allows best possible PI regulator performance to be determined for any particular application


Primary Objectives of a Current Regulation System

• Minimize steady state magnitude (and phase for an AC system) output variable error, preferably achieving zero steady state error.

• Accurately track the commanded reference variable during transient changes. This requires a regulation system to have as high a bandwidth as possible, to achieve the best possible dynamic response.

• Limit the peak value of the output variable, to avoid overload conditions.

• Minimize low order harmonics in the load variable, and compensate for DC-link voltage ripple, deadtime delays, semiconductor device voltage drops, load parameter variation and other practical second order effects associated with the operation of the electrical conversion system.

Introduction


Electrical Source Switched Power Converter

Introduction

General Arrangement of Current Regulation for an Electrical Motor Drive System

Load Motor

Current MeasurementTarget Current ReferenceController


Introduction

Electrical Schematic of AC Current Regulated Systems

Single Phase Current Regulated System

Three Phase Current Regulated System (L or LCL Filter)


Principle of Pulse Width Modulation

W.R. Bennett:1933 H.R. Black: 1953 S. Bowes: 1975

dcV

V0

1S

dcV

L

1D

2S2D

swv

oE+

-

R

0.1

0.1−0.1

0.1−

dcV

dcV−

( )tM oωcos


Analytical Solution is obtained by Double Fourier Analysis of the Switched Phase Leg Output Waveform:

Fundamental

Baseband Harmonics

Carrier

Carrier Sideband Harmonics

Frequency

Mag

nitu

de

The solution contains:• Fundamental component• Baseband Harmonics• Carrier Harmonics• Sideband Harmonics

Fundamental and Baseband Harmonics are the relevant harmonics for current regulation.

Pulse Width Modulation of Voltage Source Inverter


Sampled PWM of Inverter Phase Leg

NOTE: Sampled references are delayed wrt their sinusoidal sources.


Combining Phase Legs creates the well known single phase and three phase Voltage Source Inverters,

Three Phase VSI

Two Level Converter Topologies

dcV

V01S

dcV

L

1D

2S 2D

aswv oE3S 3D

4S 4D

bswv

R

dcV

V0 1S

dcV

L1D

4S 4D

aswvbE3S 3D

6S 6D

bswv5S 5D

2S 2D

cswv

L

L

aE

cE

R

R

R

Single Phase VSI

which cancel various harmonics between the phase legs depending on the modulation strategy, i.e.


PWM of Single Phase VSI

t

Fundamental for Phase Leg a

t

Switched l−lOutput Waveform

t

+Vdc

t

t

Triangular Carrier

Fundamental for Phase Leg b

Triangular Carrier

−Vdc

+Vdc

−Vdc

+2Vdc

−2Vdc

Switched Waveformfor Phase Leg b

Vactive

Vz VactiveVactiveVactive

Phase Leg b

Phase Leg a

l−l Output Voltage

ti−1

Vz Vz Vz

Vz Vz Vz Vz

Switched Waveformfor Phase Leg a

+Vdc

−Vdc

+Vdc

−Vdc+2Vdc

−2Vdc

ti ti+1 tj−1 tj tj+1

Single Phase Three level Continuous PWM - sampled

0 10 20 30 40 50 6010-4

10-3

10-2

10-1

100

Harmonic Number

0 10 20 30 40 50 6010-4

10-3

10-2

10-1

100

Harmonic Number


PWM of Three Phase VSI

t

t

Triangular CarrierFundamental for Phase Leg aFundamental for Phase Leg b

Switched Waveform for Phase Leg a

Switched Waveform for Phase Leg b

t

Fundamental for Phase Leg c

t

Switched Waveform for Phase Leg c

t

t

tSwitched l−l Output Waveform (vca)

+Vdc

−Vdc

+Vdc

−Vdc

+Vdc

−Vdc

+2Vdc

−2Vdc

+2Vdc

−2Vdc

+2Vdc

−2Vdc

Switched l−l Output Waveform (vbc)

Switched l−l Output Waveform(vab)

Phase Leg a

Phase Leg b

Phase Leg c

∆T/2

vab l−l Output Voltage

vbc l−l Output Voltage

vca l−l Output Voltage

+Vdc

−Vdc

+Vdc

−Vdc

+Vdc

−Vdc

+2Vdc

−2Vdc

+2Vdc

−2Vdc

+2Vdc

−2Vdc

∆T/2

VzVzVzVz

VzVzVzVz

VzVzVzVz

V1 V1

V2 V2

V1 + V2 V1 + V2

T1 − T3

T3 − T5

ti−1 ti

T5 − T1

ti+1

T3

T1

T5


Third harmonic injection and Space Vector modulation allow an increase in modulation index without reaching saturation limits.

0 50 100 150 200 250 300 350

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Third Harmonic Injection

Space Vector Modulation

0 50 100 150 200 250 300 350

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Third Harmonic Injection/Space Vector Modulation


Pulse Width Modulation

Common Myths about PWM:

• Must have odd carrier ratio to avoid even harmonics

• Must have triplen carrier ratio for three phase system

• Space Vector Modulation is superior to Sine-triangle Modulation

• Instantaneous Third Harmonic Injection is impossible

• Analog SV modulation is impossible


Analog Implementation of SV modulator

Pulse Width ModulationInstantaneous SV/3rd Harmonic Implementation

2),,min(),,max( cbacba

offvvvvvvv +

=

Digital Implementation of SV modulator


PWM of Three Phase Voltage Source Inverter

Phase Leg L-L Voltage

Phase Leg L-L Voltage

Sinusoidal Reference

Sine+ 3rd Harmonic

Experimental Confirmation of Theoretical PWM Harmonics


• Ideal “Average” Linear Model

• Transport and Sampling Delay Limitations

• Maximum Gain Determination – backemf compensation, Proportional-Resonant, d-q synchronous frame

• Three Phase Current Regulation

• Discrete Time Domain Models

• Current Regulation with LCL Filters

Linear Current Regulation


• Differential equation of system:

Ideal “Average” Model of Single Phase VSI

• Averaged model in Laplace form:

( ) ( ) ( ) ( )dt

tdILtRItEtV oooo +=−

( ) ( ) ( )sLR

sEsVsI ooo +

−=

( ) ( ) DCo VtMtV 2=

Vo(t) Eo(t)Io(t)2VDC


The ideal system reduces (in control terms) to the s-domain form of:

under the simplifications of

• The Modulator/VSI reduces to a linear gain (2VDC), ignoring switching harmonics (which cannot be controlled anyway)

• The input disturbance (Eo) represents the motor back-emf

• Plant block is defined by:

Ideal Linear AC Current Regulated System

( )psTRsLR

sG+

⋅=+

=1

111

RLTp =

H(s)∆I(s)Iref(s) G(s) Io(s)Vo(s)

2VDC

Eo(s)Controller Inverter

Gain Plant



• Analysis of the system block diagram:

• Solving for Io (s) gives:

• This is the closed loop transfer function of the system

( ) ( ) ( ) ( )( ) ( ) ( ) ( )

( ) ( )sGVsHsGsE

sGVsHsGVsHsIsI

DCo

DC

DCrefo 2121

2+

−+

=

( ) ( ) ( ) ( )[ ]( ) ( ) ( ) ( )[ ] ( ) ( )sEsGsIsIVsHsG

sEsVsGsI

oorefDC

ooo−−=

−=2

( ) ( ) ( )[ ] ( ) ( ) ( ) ( ) ( )sEsGsIVsHsGVsHsGsI orefDCDCo −=+ 221



• This transfer function includes two terms:–Reference tracking component

–Disturbance rejection:

• Primary performance objectives are:

( )( )

( )( ) ( )sGVsH

sGsEsI

DCo

o21+

−=

( )( )

( ) ( )( ) ( )sGVsH

sGVsHsI

sI

DC

DC

ref

o21

2+

=

( )( ) ε≤sEsI

o

o( )( ) 1≈sI

sI

ref

o Make H(s) as large as possible



• Try a simple PI regulator:

• Open Loop Forward Path Gain:

• Classical control theory states system is stable provided:

• Simple PI forward path phase response asymptotes to -90o

at high frequencies. Hence system is unconditionally stable irrespective of PI gain Kp and integrator time constant τi.

THIS CLEARLY DOES NOT MATCH REALITY ????

( )

+=

+=

i

iP

iP s

sKs

KsHτ

ττ

111

( ) ( )( )p

i

i

PDCDC

sTs

sR

KVsGVsH+

+⋅=

1

12 ττ

( ) ( ) ( ) ( ) 121802 =°−>∠ ccDCccDC jGjHVwhenjGjHV ωωωω



Simulated response of ideal average value model AC current regulator with

very high PI gains.

Circuit Parameter Value

Resistive load (R) (Ω) 2

Inductive load (L) (mH) 20

Switching Freq. (fs) (kHz) 5.0

DC Bus volt. (2VDC) (V) 400

Back EMF volt. (VEMF) (VRMS) 80

Back EMF freq. (Hz) 50

Sampling period (T) (sec) 10-4

Test circuit parameters


Practical Linear AC Current Regulated System

PSIM Current Regulator Simulation with PWM and Controller Delays




Resistive load (R) (Ω) 1.2

Inductive load (L) (mH) 10.0






Kp = 0.145Steady state error, damped transient

Kp = 0.218Reducing steady

state error, underdamped

transient

Kp = 0.247Less steady state

error, very underdamped

transient

• Clearly gain cannot be arbitrarily increased despite prediction of ideal theory.

• Need to identify the reason, so that PI gains can be set to maximum possible.

Ierr

Ierr

Ierr


• Average model must be extended to incorporate 2nd order effects which constrain practical controller gains.

• The two most likely candidates are:– Transport delay due to the PWM process– Sampling delay caused by digital controller



Sampling and Transport Delay

• Asymmetrical regular sampled PWM introduces a quarter carrier-period sampling delay (ZOH) into the control process.

• Computation delay and synchronous sampling cause a further half-carrier transport delay (z-1).

• Overall delay of 0.75 of the carrier period is introduced into the forward path of the control loop.

sd fTT /75.075.0 =∆=

Sampling and Transport Delay caused by PWM process and digital

controller sampling/computation.


Stationary frame PI Regulator with sampling and transport delay

Bode plot of open loop forward path gain for ideal and regulators with transport delay

The gain limitation is now clear – forward path phase goes below 1800 as frequency increases. Forward loop gain magnitude must fall less than 1.0 before this occurs.

Effect of Regulator Delay on Frequency Response

H(s) e-sTd

Sampling &Transport Delay

∆I(s)Iref(s) G(s) Io(s)Vo(s)

Eo(s)Controller Inverter

Gain Plant

2VDC


PI Regulator Response with Regulator Delay

Simulated stationary frame PI regulator with regulator delay(a) “ideal” high gains (b) gains reduced to maintain stability

WHICH RAISES THE QUESTION – WHAT ARE THE MAXIMUM POSSIBLE PRACTICAL GAINS?

(a)

(b)


Stationary Frame PI Regulator Maximum Gains

• Forward path transfer function with regulator delay Td

• Transfer function phase angle at cross over frequency s = jωc

Hence for a given regulator delay, ωc is the system bandwidth at φm = selected phase margin

( ) ( ) ( ) ( ) mpcdciccDCc TTjGVjH φπωωπτωωω +−=−−−=∠ −− 11 tan2/tan2

ωc =tan−1 ωcτ i( )−φm

Td

≈π 2−φm

Td

( ) ( )

+

+= −−

p

sT

i

iDCpDC

sTsT

es

sRVK

sGVesH dd1

1122

ττ

pc T

1>>ω ( ) 2tan 1 πω ≈−

pcT


Stationary Frame PI Regulator Maximum Gains

• Maximum possible Kp is for a given ωc is:

assuming

• Integral time constant τi can be determined by making

• These gains are independent of the plant time constant, and are determined only by φm Td VDC and L

For any given system with regulator delay Td , these are the maximum possible PI gains for a phase margin of φm

( )( )22

22

1

12

ic

pcicDC

pT

VRK

τω

ωτω

+

+=

( ) 2/tan 1 πτω ≈−ic

ci ω

τ 10≈

122 >>pc Tω

122 >>icτωDC

cp V

LK2ω

≈


Example Grid Inverter: Calculations & Results

Circuit parameters

krad/s81.55.1

698.056.124 =

−=

−= −eTd

mc

φπω

V/A145.0400

1081.52

33=

∗==

−eeV

LKDC

cp

ω

msec72.182.51010

3 ===ec

i ωτ

sec5.15/75.0 43 −== eeTd

rad698.040 == omφ



Inductive load (L) (mH) 10.0







Practical Linear AC Current Regulated SystemCircuit Parameter Value








Kp = 0.145φ = 40o

Steady state error, damped transient

Kp = 0.218φ = 15o

Reducing steady state error,

underdamped transient

Kp = 0.247φ = 5o

Less steady state error, very

underdamped transient

• Damping response of transient depends on designed gain margin.

• φ = 40o is a typical value that gives a good balanced response.

• But are these gains enough to get an acceptable AC regulator performance?

Ierr

Ierr

Ierr


Practical PI Regulator Performance Evaluation

• The current error ∆I(s) as a function of control inputs is :

• It has two elements: Closed Loop Tracking Error - the ability of regulation system to follow current reference:

• Closed Loop Disturbance Rejection Error – regulation system sensitivity to backemf disturbance:

( ) ( )( ) ( )

( ) ( )( ) ( )

( ) ( )sIsIsGVesH

sGsEsGVesH

sIsI DIDC

sToDC

sTref dd∆+∆=

++

+=∆ −− 2121

1

( ) ( )( ) ( ) ( )sGVesHsIsIsE

DCsT

ref

II d 21

1−+

=∆

=

( ) ( )( )

( )( ) ( )sGVesH

sGsEsIsE

DCsT

o

DD d 21 −+

=∆

=


Practical PI Regulator Performance Evaluation

• Both tracking error and disturbance rejection error increase with frequency (controller gain reduces)

• Disturbance error increases more slowly because of plant pole

• BUT, magnitude of disturbance injection (emf) is usually larger still creates more error

Irrespective of the contribution, the error at AC fundamental

frequency is often unacceptably large with PI controller even with

maximum possible gains.


• Maximised gains are often insufficient to achieve acceptable regulator performance, especially when error caused by back EMF is considered

• The following enhancements can be considered–Minimise regulator delay to achieve the maximum possible gains.

Use asymmetrical regulator sampled PWM and synchronous sampling as a matter of course.

–Reduce the back EMF disturbance effect with feed forward compensation

–Increase the regulator gain at the fundamental target frequency (Proportional-Resonant Controller)

• Lets see how these ideas work

Stationary Frame Regulator Enhancements


• Require to measure average load current (no switching harmonic components) without filter delay, to avoid increasing Td.

• Synchronously sample at top/bottom of (implied) carrier

• At this point VSI phase leg volt-second output equals commanded voltage minimum measured current ripple

Synchronously sampling the “average” current

Synchronous sampling of measured current


Synchronously sampling the “average” current

Calc.k

Calc.k+1

Calc.k+2

Calc.k+3

Sampled Current

Voltage Reference

Actual Current

i(k)i(k+1)

i(k+2) i(k+3)

m(k) m(k+1) m(k+2)m(k-1)

T

Carrier

m(k+3) m(k+4)

Calc.k+4

Calc.k+5

i(k+4) i(k+5)

• Ensures that the sampled currents correspond to the average currents

• Still has ½ carrier interval transport delay due to finite calculation time


Further Minimise Transport Delay

• At low switching frequencies, tracking error can still be too high

• Further reducing transport delay allows higher gains

• Achieved by pre sampling before each half carrier cycle and dynamically compensating for ripple current in sample

• Feasible using modern DSP with synchronous sampling

ADC1 ADC2 ADC3ADC4


• Back EMF is predictable, and so its effect can be reduced by feedforwarding the measured (or estimated) value

Feedforward Mitigation of Backemf Disturbance

Average model AC current regulation system with back EMF feedforward

H(s) e-sTd


∆I(s)Iref(s) G(s) Io(s)Vo(s)

F(s) e-sTd

EMF Feedforward

Eo(s)

Eo(s)

Controller InverterGain


EMFMismatch

Plant

2VDC


• The transfer function of system with feedforward becomes:

• With perfect feedforward (F(s)=1) influence of backemf is completely eliminated (ED(s)=0), and only ER(s) remain.

• The controller design process still maximises KP as before.


( ) ( )( ) ( )

( ) ( )( ) ( )( ) ( )

( ) ( )sIsIsGVesH

sGesFsEsGVesH

sIsI DIDC

sT

sT

oDC

sTref d

d

d∆+∆=

+

−+

+=∆ −

−

− 211

211

( ) ( ) ( ) ( )( ) ( )

( ) ( )( ) ( )( ) ( )sGVesH

sGesFsEsGVesH

sGVesHsIsIDC

sT

sT

oDC

sTDC

sT

refo d

d

d

d

211

212

−

−

−

−

+

−−

+=



Simulated and Experimental system response with 110Vrms backemf.

PI controller without backemf feed forward

PI controller with backemf feed forward


Accuracy of Back EMF Estimation

(a) Performance of PI regulator with backemf feedforward(b) Miss estimated back EMF estimation (80% magnitude, 40o phase lead)


• Key limitation of PI regulator is high ED(s) at fundamental reference frequency (ω0)

• An alternative approach is to increase controller gain at ω0without affecting high frequency gain determined by Kp

• This is the strategy of the P+Resonant (PR) controller, with a resonant gain peak at ω0 :

Increase Fundamental Gain with PR Regulator

( )

++= 22

11oi

pPRs

sKsHωτ


• Properties of the P+Resonant controller:–Low and high frequency behaviour approximates a proportional

controller–Controller provides near infinite gain at the target AC frequency–Reference tracking error and disturbance error are near zero at the

AC frequency–Hence zero steady magnitude and phase error

Note : PR regulator can be a little sensitive to mismatch between the resonant term and AC fundamental frequency.

Increase Fundamental Gain with PR Regulator


• Forward Path Gain:

• At the cross-over frequency:

• If , then:

• This is identical to the PI expression.

( ) ( )

+

++= −−

p

sT

oi

DCpDC

sTPR sT

es

sRVK

sGVesH dd1

1112

2 22 ωτ RLTp =

oc ωω >>

+

+=

+

+≈

−

−

pc

Tj

ic

icDCp

pc

Tj

ic

DCp

Tje

jj

RVK

Tje

jRVK

GAINPATHFORWARD

dc

dc

ωτωτω

ωτω

ω

ω

1112

1111

2

Maximum Gains with PR Regulator

cjs ω=

( ) ( )

+

−+= −−

pc

Tj

co

c

i

DCpcDC

TjcPR

Tjej

RVK

jGVejH dcdcωωω

ωτ

ωω ωω1

1112

2 22

( ) ( )

+

+= −−

p

sT

i

iDCpDC

sTsT

es

sRVK

sGVesH dd1

1122

ττ


• Therefore the maximum gains for the PR controller are the same as for the PI controller, and are defined by:

– Target Phase Margin φm

– DC link voltage 2VDC

– Load Inductance L– PWM/Current regulator transport delay Td

DC

cp V

LK2ω

=


ci ω

τ 10=

d

mc T

φπω −=

2



• Resonant gain peak improves backemf disturbance rejection at ω0

• Also reduce EI(s) at ω0, leading to better tracking

Bode plot of GH(s) for PI and PR regulators with transport delays

Closed Loop Disturbance Rejection Error ED(s) for PI and PR controllers











PI controller:Kp = 0.145

φ = 40o

Steady state error, damped transient

PR controller:Kp = 0.145

φ = 40o

Neligible steady state error,

damped transient

PI verses PR controller response with same gains.

Ierr

Ierr


Experimental Confirmation: PR Regulator

Simulated and Experimental system response with 110Vrms backemf

Same transient response for all three alternatives

PI controller without backemf feed forward

PI controller with backemf feed forward

PR controller


Three Phase AC Current Regulated VSI

Three phase Voltage Source Inverter (VSI) connected to a back EMF load through a series R-L impedance



• KVL loops:( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )sVsEsEsZsIsZsIsV bbabaa +−+−= 2

• For balanced system:

( ) ( ) ( ) 0=++ sVsVsV cba ( ) ( ) ( ) 0=++ sEsEsE cba

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )sVsEsEsZsIsZsIsV ccbabb +−+−= 2

( ) ( ) ( )sVsVsV bac −−= ( ) ( ) ( )sEsEsE bac −−=


• For an isolated three phase system

• Substituting voltage and current constraints into KVL loops gives

Thus only two currents need to be controlled for a three phase system, each regulated only by their individual phase

voltages using previous single phase theory

• Modulate third phase to achieve balanced system using:


( ) ( ) ( ) 0=++ sisisi cba

( ) ( ) ( )sLR

sEsVsi aaa +

−= ( ) ( ) ( )

sLRsEsVsi bb

b +−

= ( ) ( ) ( )sLR

sEsVsi ccc +

−=

( ) ( ) ( )sVsVsV bac −−=


Topology of a three phase AC current regulated voltage source inverter




Note - effective DC source voltage for Kp gain calculation changes from 2VDC for single phase system to VDC for three phase system

Single Phase Current Regulated System

Three Phase Current Regulated System (L or LCL Filter)











Circuit parameters

krad/s81.55.1

698.056.124 =

−=

−= −eTd

mc

φπω

V/A582.0200

2081.5 33=

∗==

−eeV

LKDC

cp

ω

msec73.182.51010

3 ===ec

i ωτ

sec5.15/75.0 43 −== eeTd

rad698.040 == omφ



No back EMF, PI maximised gains (fs = 5kHz)

Back EMF, PI maximised gains (fs = 5kHz)

3 phase simulation 3 phase experimental




Back EMF, PI maximised gains plus feedforward EMF compensation (fs = 5kHz)

Back EMF, PR regulator maximised gains (fs = 5kHz)





Comparison of Current Error – all regulator alternatives


Back EMF Estimation by Direct Measurement

• Synchronously measure scaled values of back EMF at inverter output terminals, if it has internal filter

• Back EMF given by :

• Sensitive to noise, particularly PWM switching ripple.

( )( )

( ) ( )sZsZsZ

Egridfilter

filtermeasa +

=

Circuit arrangement to allow measurement of back EMF


Back EMF Estimation by Predictive Calculation

• Back EMF estimation, as used in predictive current regulator

• Load inductance estimation constraints

ea i[ ]= Va i − 2[ ]− 2Va i − 3[ ]− ia i[ ]R'+ L'∆T /2

−3ia i −1[ ]+ 5ia i − 2[ ]− 2ia i − 3[ ]( )

Response with back EMF, estimated feedforward EMF (fs = 5kHz)

0.8L ≤ L'≤1.23L


Further Minimise PWM Transport Delay

• At low switching frequencies, tracking error can still be too high

• Further reducing transport delay allows higher gains

• Achieved by pre sampling before each half carrier cycle and dynamically compensating for ripple current in sample

• Feasible using modern DSP with synchronous sampling

ADC1 ADC2 ADC3ADC4


Further Minimise PWM Transport Delay

• Ideally reduce overall regulator delay to 0.25 carrier period

• Theoretically should increase ωc and gains by factor of 3

• Experimentally found to be susceptible to noise

• Only approx 2 times increase in gain was achievable

without back EMF, PI controller, reduced sampling time by measurement compensation (fs = 2.5 kHz)


• ABC frame : Three non-orthogonal variables with two degrees of freedom

• αβ frame: Two orthogonal variables

• Clarke (alpha-beta) transform:

• Inverse Clarke transform:

−−−=

=

β

α

β

ααβ i

iii

Tiii

T

c

b

a

23212321

01

32

Orthogonal Reference Frames: αβ stationary frame

−−−

=

=

c

b

a

c

b

a

iii

iii

Tii

2323021211

32

αββ

α


• The (αβ) quantities are sinusoidal

• Hence gain maximisation approach is identical to the (abc) frame current regulator

• The regulator output is compatible with a direct space vector modulator – no need to indirectly calculate the phase C PWM command for SV implementation (but still need to decode SV output to phase leg switching commands)

• References can be defined in either the (abc) or the (αβ) frames as suits application







Orthogonal Reference Frames: dq rotating frame

• Synchronous frame – AC quantities are transformed to equivalent DC quantities

• Park transform – (αβ) to (dq)

• Inverse Park transform:

−

=

=

β

α

β

α

θθθθ

ii

ii

Tii

dqq

d

cossinsincos

−=

=

q

d

q

dTdq i

iii

Tii

θθθθ

β

α

cossinsincos

tωθ =

tωθ =


Orthogonal Reference Frames: dq rotating frame


Reference Frames: regulator transformation

Stationary frame αβ controller Rotating frame DQ controller

+

+

iP

iP

sK

sK

τ

τ110

011

++

+−

+

++

2222

2222

111

111

oiP

o

o

i

o

o

ioiP

ssK

s

sssK

ωτωω

τ

ωω

τωτ

+

+

iP

iP

sK

sK

τ

τ110

011

++

+−

+

++

2222

2222

111

111

oiP

o

o

i

o

o

ioiP

ssK

s

sssK

ωτωω

τ

ωω

τωτ

Stationary Frame PI regulator transforms to Synchronous Frame Resonant

Synchronous Frame PI regulator transforms to Stationary Frame Resonant

Gains are the same in both frames of reference and hence can be calculated as before


Simulated and Experimental PR Current Responses


Simulated and Experimental PR Current Responses


( ) ( ) ( )( )sss

ksi rrr

pqs ωωτ ω

ω −

+= ** 11 ( ) ( ) ( )

m

drrds L

sssi

** 1

λτ+=

Torque Controller Flux Controller

Example: AC Induction Motor Variable Speed Drive



VSI IM

1/Lm

PI

Slip Est.

PIABC

DQ PI ABC

DQ

prτ+1

rωrω

*drλ

*rω

*di

*qi

*qv

*dv

esθ e

sθ

−

−=

*

*

*

*

cossin

sincos

23

21

01

q

d

es

es

es

es

b

a

v

v

v

v

θθ

θθ

Synchronous Frame PI Regulator

−=

b

a

es

es

es

es

q

d

i

i

i

i

32

31

01

cossin

sincos

θθ

θθ

( )( )

( ) ( )( ) ( )

−−

+=

sisisisi

sK

svsv

qq

dd

ip

q

d*

*

*

* 11τ



ABC

DQ PR

PR

VSI IM

1/Lm

PI

Slip Est.

rωrω

prτ+1*drλ

*rω

*di

*qi

*ai

*bi

*av

*bv

*cve

sθ

Stationary Frame PR Regulator

( )( )

( ) ( )( ) ( )

−−

++=

sisisisi

s

sKsvsv

bb

aa

eip

b

a*

*

22*

* 11ωτ



• Resonance was implemented using the Second Order Generalised Integrator:

• Provides the transfer function:

• Advantage of this form is that the integrators are unaffected by changes in resonance frequency, simplifying the implementation in a DSP.

Stationary Frame PR Regulator

1s

ωe2

1s

y(s)x(s) 1τi

( )( ) 22

1

ei s

ssxsy

ωτ +=



( )( )

( ) ( )( ) ( )

+

−−

+=

)(

)(*

*

*

* 11estb

esta

bb

aa

ip

b

asisisisi

sK

svsv

εε

τ

0)( 90+∠≈ e

snom

rnomesta V θ

ωωε

Stationary Frame PI Regulator with EMFest



ABC

DQ

VSI IM

1/Lm

PI

Slip Est.

rωrω

prτ+1*drλ

*rω

*di

*qi

*ai

*ci

*bi

esθ

hxx iii >−*DCx Vv −→

hxx iii −<−*DCx Vv +→

, (19a)

,

Implemented digitally for this example at 100 kHz update rate, average switching frequency of approx 5 kHz

Variable Band Hysteresis (digital implementation)


Gains matched for the three different strategies

Gains can be set to same maximum gains irrespective of current regulation strategy – sampling and transport delay

are the limiting factors



Example: AC Induction Motor Variable Speed DriveParameter Value

Induction Motor (4 pole) 3.2 kW, 415 Vl-l, 6.3 A, YIM - rs 3.24 Ω

- rr 2.6 Ω- Lls = Ls – Lm 19 mH- Llr = Lr – Lm 21.1 mH- Lm 504.4 mH

Inertia 0.65 kgm2

System Load Dynamics 1.2 + 0.0034ωr+70e-6ωr2

Controller - kpω 0.95- τrω 0.034 sec- kpi 0.7- τri 0.00192 sec- Calc. Freq. 10 kHz

PWM Frequency 5 kHzVSI DC Link Voltage 520 V

• 15 kW 4 phase leg inverter ( 3 phase VSIplus DC bus chopper)

• DSP Controller:Texas Instruments TMS320F2810 fixed point DSP

• 3 phase 5kW Induction Motor• Quadrature pulse

encoder to measure speed and direction

• Coupled DC motor and drive to provide variable loading

Experimental System


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

0

200

400

600

Time (s)

Spe

ed (R

PM

)

Stationary Frame PI

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-5

0

5

AB

C C

urre

nt (A

)

Time (s)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

5

10

Time (ms)

DQ

Cur

rent

(A)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-4

-2

0

2

Experimental Current Step Change: PIstationary



Experimental Current Step Change: PRstationary


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

0

200

400

600

Time (s)

Spe

ed (R

PM

)

Stationary Frame PR

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-5

0

5

AB

C C

urre

nt (A

)

Time (s)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

5

10

Time (ms)

DQ

Cur

rent

(A)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-4

-2

0

2


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

0

200

400

600

Time (s)

Spe

ed (R

PM

)

Synchronous Frame PI

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-5

0

5

AB

C C

urre

nt (A

)

Time (s)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

5

10

Time (ms)

DQ

Cur

rent

(A)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-4

-2

0

2

Experimental Current Step Change: PIsynchronous



Experimental Current Step Change: Hysteresis


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

0

200

400

600

Time (s)

Spee

d (R

PM)

Hysteresis

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-5

0

5

ABC

Curre

nt (A

)

Time (s)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-3

0

5

10

Time (s)

DQ C

urre

nt (A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-3

-4

-2

0

2


• LCL filter Third order line filter for grid connected inverters

• Benefits of LCL filters (over L filters)–Greater attenuation, less size, less cost

• Major design challenges–LC network resonance, low harmonic impedance

LCL Filters for AC Inverters


Comparable L and LCL Filters

• L filter impedance

• LCL filter impedance

• To meet IEEE519 impedance >100pu @ 10kHz

@ 50Hz @ 10kHzL = 55mH 0.5pu 100puL = 16.5mH 0.15pu 30pu

L1 = 3mH @ 50Hz @ 10kHzCf = 7.5uF 0.036pu 154puL2 = 1mH


L and LCL Filter Response

LCL filter with comparable switching frequency can never achieve comparable baseband filtering

LCL has greatest switching attenuation

L filters have greatest baseband attenuation

LCL dominated by series inductance in

baseband region


• LCL resonance damping:– Passively using series or shunt resistances– Actively using an additional state variable in the control law

• How to synthesise the current controller?– Analyse using discrete time models (i.e. state space or z-domain)– Sampling delay accounted for using a ZOH transformation of the

LCL filter s-domain transfer function(s)– Transport delay accounted for using a z-1 shift operator

• Active damping is proposed in multiple forms:– Capacitor current feedback is the most commonly accepted

• Damping may not be required under some circumstances

Control Loop Synthesis and Analysis


LCL Filter Controller Options

• Single loop –Difficult to manage LCL resonance

• Active damping (dual loop)–Commonly feedback of ic (or variant) for damping, through gain K

Which controller is suitable and when ? use Bode analysis

Plant (LCL)

Controller

Inverter


L and LCL Filter Equations

• L Filter

• LCL Filter

• NOTE : filter resistance neglected to model worst case undamped filter characteristic

( ) ( ) ( )[ ] ( ) ( ) ( )[ ]sEsVsYsEsVsL

si oLo −=−=1

2

( ) ( ) ( ) ( )( ) ( )

( ) ( ) ( ) ( )sEsYsVsY

sEs

sCLCLL

sVssCLL

si

Gov

res

f

fo

resf

+=+

+−

+=

22

21

2122212

1111

ωω

is the filter admittance seen by the grid and converter for an L filter( )sYL

are the filter admittances seen by the converter and grid for an LCL filter, where

( ) ( )sYsY Gv and( ) ( )2

1 2 1 2res fL L L L Cω = +


Discrete Time Model – Single Loop Controller

• Plant transfer function (grid current)

• where and

• using ZOH discretization (sampled system)

( ) ( )( ) ( )

22

2 2 21

1 LCi

o res

i sG s

V s sL s

γ

ω= =

+

( ) ( )( ) ( ) ( )

( )( ) ( )

22 2

1 2 1 2

sin 11 2 cos 1

resi

o res res

i z TT zG zV z L L z L L z z T

ωω ω

−= = − ×

+ − + − +

1 2

1 2res

f

L LL L C

ω +=

2

1LC

fL Cγ =


Discrete Time Model – Single Loop Controller

• PR fundamental controller

• Inverter model with PWM transport delay

• Open loop forward path equation (without active damping)( )( ) ( ) ( )2 1

22

DC c ie

i zz V G z G z

i z−=

( ) ( )( )( )

20

20 0

sin1 112 2 cos 1c p

r

T zG z KT z z T

ωω ω

− = + − +

( ) ( )1o DC oV z z V m z−=

( ) 2 20

11c pr

sG s KT s ω

= + +


Discrete Time Model – Dual Loop Controller

• Inner loop plant transfer function (capacitor current)– Active damping

• Using ZOH discretization (sampled system)

• Closed inner loop with gain K (including inverter model)

( ) ( )( )

( )( )2

1

sin 12 cos 1

c resic

o res res

i z T zG zV z L z z T

ωω ω

−= = ×

− +

( ) ( )( ) ( )

2

2 21

1cic

o res

i s sG sV s sL s ω

= =+

( )( )

( )( )

c DC ic

o DC ic

i z V G zm z z KV G z

=+


Discrete Time Model – Dual Loop Controller

• Equation relaying i2 to ic–Impulse invariant discretization (delay already in model)

• Overall open loop forward path equation with active damping

( )( )

( )( )

22 2

2i LC

c ic

i s G si s G s s

γ= =

( )( ) ( )

2 22

21LC

c

i z T zi z z

γ=

−Zimp

( )( ) ( ) ( )

( )( )( )

( ) ( ) ( ) ( )( )

2 2

2

2

cce

o c

DC ic cc

DC ic

i z i z i zG z

i z m z i z

V G z i z i zG z

z KV G z

= × ×

= ×+


LCL Filter Active Damping Regions

• Low LCL resonant frequency–-180º phase jump with

unbounded gain–Unstable without damping–Stabilised with active damping

• High LCL resonant frequency– -180º phase jump occurs after

phase crosses -180º due to delay roll-off

– Stable without damping

• Critical LCL frequency (ωcrit) forward path phase reaches -180º


Critical LCL Resonant Frequency

• To find ωcrit

• PR controller response well below crossover frequency–Phase contribution of controller is negligible:

• LCL resonance no phase contribution until the resonant frequency is reached

– Hence plant phase reduces to

• with substitution and manipulation

• Below ωcrit damping is required

• Above ωcrit single control loop is sufficient

( ) ( ) ( )22

2

j T j T j T j TDC c ie

i z e e V G e G ei

ω ω ω ω π−∠ = = ∠ = −

( ) 0j TcG e ω∠ ≈

( )21

1j T

i j TG ee

ωω∠ = ∠

−

( )2

2 2 2j T

e

i Tz e Ti

ω π ωω π∠ = = − − − = −3crit Tπω =


Exploring the Active Damping Regions

• Closed loop poles Required for root loci

• Using conventional 1+G(z)=0, from forward path G(z)–Single loop controller

–Inner loop of dual loop controller

–Overall dual loop controller

( )2 0DC p iz V K G z+ =

( ) 0DC icz V KG z+ =

( ) ( ) ( ) ( )2 0DC ic DC P ic cz V KG z V K G z i z i z+ + =


Single Loop (i2) Controller Root Loci

High frequencyCritical frequencyLow frequency

• No damping capability at critical or low frequencies

• Provides damping of poles at high frequency– No active damping required agree with Bode

• All systems have loci which track unstable through 0.5 3 2z j= ±


Single Loop Controller when Resonance Above ωcrit

• Single loop controller is suitable–Stable, active damping unnecessary

• Gain limitation Low frequency poles, not resonance–Same mechanism as L filters

Low frequency poles cause

instabilityResonant poles will be damped


Gain Selection when Resonance Above ωcrit

• Using the same method as for standard L filters [Holmes et. al. 2009]

–Resonance and controller minimal magnitude and phase contribution at crossover frequency

–Only low frequency model required series inductance plant

–Calculate crossover ωc frequency for a desired phase margin φm

( )( ) ( ) ( )

2 1

2 1 21DC pe

i z Tz V Ki z z L L

−=− +

( )( ) ( )

2

2 1 2

11

32 2 2 2

c

c c

DC pj Te j T j T

cc c

V K Ti z ei L L e e

T T T

ω

ω ω

ωπ πω ω

∠ = = ∠+ −

= − − − = − −

( )2

2

32 2

cj Tm ce

i z e Ti

ω πϕ π ω= + ∠ = = − 23 2

mc T

π ϕω −=

d

mc T

ϕπω −=

2


Gain Selection when Resonance Above ωcrit

• Proportional gain is set to achieve unity gain at desired crossover frequency ωc

• Design PR controller time constant (Tr)– Phase contribution minimal at ωc

( ) ( )1 2 1cj T

pDC

L L eK

V T

ω+ −=

( )1 2cp

DC

L LK

Vω +

≈

10r cT ω≈

High Frequency SystemL1 = 6mH L2 = 2mHCf = 1.5μF Leq = 1.5mH

2VDC = 650V fs = 5kHzωres = 21.1krads-1 Τ = 0.1msecωcrit=10.5krads-1 Τd = 0.15msec

φm = 45º ωc=5.24krads-1

Kp = 0.129A-1 Tr = 1.9msec

-135º

ωc

ωcrit

ωres


Inner Loop (ic) of Active Damping Root Loci

Low frequency

• Only low frequency region examined– High frequency not required– Critical frequency not effective (next slide)

• Provides damping of poles – Limited range of K

Critical frequency0.5 3 2z j= ±


Dual Loop Controller Root Loci

Critical frequencyLow frequency

• At low frequency – Poles are moved inside unit circle by active damping– Limitation to damping gain K before instability

• At critical frequency – never enter unit circle

Varying K(active damping)

Poles start unstable


Controller when Resonance Below ωcrit

• Dual loop controller (active damping) required–Capacitor current feedback selected

• Gain selection will ensure maximally damped poles

Poles originate outside unit

circle

Active damping draws poles into stability


Gain Selection when Resonance Below ωcrit

• Low frequency still dominated by series filter inductance

• Phase margin must consider phase contribution of resonance– Crossover frequency ratio of resonant frequency [Tang et. al. 2012]

• Proportional gain and PR time constant Same manner as earlier

• Best possible damping gain– Maximally damped poles

– Closed loop characteristic equation

– Bounded range for K

10r cT ω≈

0.3c resω ω≈

( )1 2cp

DC

L LK

Vω +

≈

Min K

Max K

( ) ( ) ( ) ( )2 0DC ic DC P ic cz V KG z V K G z i z i z+ + =


Bounded Range for K (Resonance Below ωcrit)

• Maximum value (Kmax)– Magnitude of characteristic equation adapted to equal 1

– Substitute in critical point

– Solve for Kmax

• Minimum value (Kmin)– Ratio of K to Kp identified using

– Routh’s Stability Criterion [Liu et. al. 2012]

– Rearranged as limitation

Kmin

Kmax

( ) ( )( ) ( )( )

2 2 2

21

1sin1

1 2 cos 1p LCDC res

res res

K z K T zV TL z z z z T

γωω ω

− +× =

− − +

( ) ( ) 221max cos21

sinTKT

TVLK LCpres

resDC

res γωω

ω+−=

0 0.5 3 2z j= +

1 2

1

pK L LK L

+≤ 1

min1 2

pK LK

L L=

+


Final Gain Selection (Resonance Below ωcrit)

• Bounded range Solid line– Kmin=0.044A-1

– Kmax=0.124A-1

• Maximum damping K=0.083A-1

Low Frequency SystemL1 = 6mH L2 = 2mHCf=15μF fs = 5kHz

ωres = 6.67krads-1 ωc=0.36ωres

ωcrit=10.5krads-1 ωc=2.4krads-1

Kp=0.059A-1 Tr=4.2msec K=0.083A-1

ωresωcrit


5kVA Experimental Setup

Other System ParametersL1=6mH L2=2mH 2VDC=650V E=415Vrms(l-l)

fsw=5kHz fsamp=10kHz T=100μs

IGBT Power Stage

ControllerTMS320F2810

LCL Filter


High Resonant Frequency System Results

• Simulation (PSIM) • Experimental

• No visible oscillation

• Rapid transient response maximised gains

• Similar to single L filter system

• High ripple poor filtering


Low Resonant Frequency System Results

• Simulation (PSIM) • Experimental

• Transient damped in 3 to 4 oscillations– Agreement with root locus design underdamped poles

• Minor dynamic performance reduction– Limited bandwidth despite maximised gains


Summary of Linear Regulation for LCL Systems

• Discrete time model of actively damped LCL system developed– Including sampling and PWM transport delay

• Two distinct regions of operation– High resonant frequency Single loop controller Simple gain selection based on L filter Dynamic performance and filtering capacity similar to L filter

– Low resonant frequency Actively damped controller (dual loop) Root locus gain selection for maximally damped poles Reduced dynamic performance

– Critical frequency dual loop active damping ineffective• Simulation and experimental results validate theoretical

models, controller selection and gain calculation

Documents

Principles and Practices of Digital Current Regulation for