Embed Size (px)
Citation preview
Appendix A
Primer on Graphs
A.1 Introduction
This appendix presents the graph notation and terminology used throughout this thesis.
It also presents some important definitions and theorems in graph theory. The definitions
and terminology follow those used by Tarjan [65].
A.2 Undirected Graphs
An undirected graph G(V,E) consists of a set of vertices (nodes) V and a set of edges (arcs)
E. Two nodes connected by an edge are said to be adjacent. A graph is represented by
the adjacency lists of its nodes. The number of edges attached to a node is known as node
degree.
A.3 Palm Thee, Thee Arcs and Fronds
A Depth First Search [27] applied to G results in a directed graph G' where 2 directions
have been imposed upon the edges during the search. These directions split the edges into
2 sets: arcs that define the spanning tree T of G' and "fronds" that connect every adjacent
pair of nodes (v,w) that are not connected by a tree arc [65]. A graph such as G has the
form of a palm tree.
A.4 Paths
A path in G is a sequence of vertices Vi and edges ei (i ::; N), where ei = (Vi, Vi+!). A path
between nodes v and w is denoted by: v ~* w. A simple path is a path where each node
118
has been traversed once. A cycle is a simple path where the extremity nodes are identical.
The number of edges in a cycle is known as cycle length.
A spanning of the graph G' by the procedure pathfinder presented by Tarjan [65] pro
duces a set of paths of the form s ::}* f. The first is a cycle and the others are simple. Each
path (except the first) has in common with the last generated path exactly two vertices s
and f.
A.5 Faces
When a planar graph is drawn on a plane, a face is defined by the inner area enclosed by
a cycle. In this drawing, any cycle that encloses another cycle may not be a face. The
number of edges in a face is known as face degree.
A.6 Connectivity
A graph is connected if for any pair of vertices there is at least one path joining them.
A.7 Biconnectivity, Articulation Points
Let G(V,E) be an undirected graph. Suppose that for each triplet of distinct vertices v, w,
a in V, there is a path p: v ::} * w such that a is not on the path p. Then G is biconnected.
If, on the other hand, there is a triplet of distinct vertices v, w, a in V such that a is on
any path p: v ::}* w, and there exists at least one such path, then a is called an articulation
point (cut vertex) of G.
A.8 Planarity
A graph is planar if it can be drawn on a plane with no edges crossing.
A.9 Short-Cuts, Corner Implying Paths, Block Neighbour
hood Graphs
Consider a planar graph G(N,E).
Definition A.I A block is a biconnected component. A plane block is a planar block. A
shortcut in a plane block G, is an edge that is incident to two vertices on the outermost
cycle of G that is not part of this cycle. A Corner Implying Path (CIP) in a plane block
119
G, is a segment VI, V2, ••• , Vk of the outermost cycle of G with the property that (VI, Vk) is a
shortcut and that V2, ••• , Vk-l are not endpoints of any shortcut. The Block Neighbourhood
Graph (BNG) of a planar graph G, is a graph in which fJertices represent the biconnected
components of G, and where an edge between two vertices in the BNG exists if the corre
sponding biconnected components have a vertex in common. A Critical Corner Implying
Path (CCIP) in a biconnected component G. of G is a CIP of Gi that does not contain cut
vertices of G.
A.I0 Rectangular Duals of a Graph
Definition A.2 The duality relationship between a graph and a rectangular topology is
defined by the following:
1. A node in G is a rectangle in the rectangular dual (RD).
2. The infinity node (representing the I/O) in G corresponds to the region enclosing the
rectangle containing the RD.
3. Two nodes joined by an edge in G are two adjacent rectangles in the RD.
4. An edge between a node and the infinity node represents a rectangle on the periphery
of the RD.
Theorem A.1 [35}. A planar graph G admits a rectangular dual iff:
1. Every face, except the external, has a degree of 3 (triangular).
2. All internal nodes have degree ~ 4.
3. All cycles that are not faces have length ~ 4.
4. One of the following is true:
(a) G is biconnected and has no more than four CIPs.
(b) G has n, n ~ 2, biconnected components; the BNG of G is a path; the biconnected
components that correspond to the ends of this path have at most two CCIPs;
and no other biconnected component contains CCIP.
Figure A.I shows examples of graphs that contradict Theorem A.I.
Ext~Ext
Ext~Ext (8)
(e)
120
c
Ext
Ext Ext
(II)
EE~Ext
E~Ext (b)
(d) Ext
Figure A.I: (a) A nonplanar graph. (b) Node E has a degree shortfall. (c) The face at the centre of the ring has a degree larger than 3. (d) The cycle oflength 3, (a,b,c,a) is not a face. (e) This graph has a BNG that is a unique path. The 3 biconnected components (where Ext connection is not included) are connected at node 4.
Appendix B
An FBD Example
We present in this appendix an example of an FBD input file which corresponds to the
top-level description of the Back Projection Computer chip.
block(7,[ s([att(design_tool),id([2])]),
s([att(name) ,value([bp])]) , s([att(edges),id([
[1,2], [1,3], [1,4], [1,5], [2,3], [2,4], [2,5], [3,4] ,[3,5], [3,6], [4,5], [4,6], [5,6], [1,8] , [2,8], [4,8], [5,8], [6,8] ])]),
s([att(children),id([l,2,3,4,5,6,8])]),
s([att(ext),id([8])])
]).
block(8,[ s([att(name) ,value([ext_l])]) ,
s([att(port),id([26,27,28,29,30,31,32])]), s([att(op_type),value([ext])]), s([att(adj_list),id([l,2,4,5,6])]),
s([att(parent),id([7])])
J).
port(26,[s([att(name),value([ext_port_l])]), s([att(ovner),id([8])]),
s([att(s_vidth),value([32])]),
s([att(is_a) ,value([ext_port])]) ,
s([att(ext_of),value([l])]) ]).
port(27,[s([att(name),value([ext_port_2])]), s([att(is_a) ,value([ext_port])]) , s([att(ovner),id([S])]), s([att(ext_of),value([6])]), s([att(s_vidth),value([6])]) ]).
port(2S, [s([att(name) ,value([ext_port_3])]) , s([att(is_a),value([ert_port])]),
s([att(ovner),id([S])]), s([att(s_vidth) ,value([16])]) , s([att(ert_of),value([S])]) ]).
port(29,[s([att(name) ,value([ext_port_4])]) , s([att(is_a) ,value([ext_port])]) , s([att(ovner),id([S])]), s([att(s_vidth) ,value([9])]) , s([att(ext_of),value([14])]) ]) .
port (30, [s([att(name) ,value([ext_port_6])]) , s([att(is_a) ,value([ext_port])]) , s([att(owner),id([S])]), s([att(s_vidth) ,value([l])]) , s([att(ext_of),value([16])]) ]).
port(31,[s([att(name),value([ext-port_6])]), s([att(is_a) ,value([ext_port])]) , s([att(ovner),id([S])]), s([att(s_vidth) ,value([16])]) , s([att(ext_of),value([20])]) ]).
port(32,[s([att(name) ,value([ext_port_7])]) , s([att(is_a) ,value([ext-port])]) , s([att(ovner),id([S])]), s([att(s_width) ,value([16])]) , s([att(ert_of),value([23])]) ]).
block(l,[ s([att(design_tool),id([2])]), s([att(port),id([l,2,3,4,6])]), s([att(parent),id([7])]), s([att(name),value([pc])]), s([att(adj_list),id([4,6,3,2,S])]), s([att(op_type),value([datapath])]),
122
123
s([att(children),id([9,10,ll,12,13,14,16])]), s([att(h_des),value([datapath(32,32,12,O,O,32,32)])]) ]) .
port(i,[s([att(name),value([datain])]), s([att(is_a) ,value([dpath_data_in])]) ,
s([att(ovner),id([i])]), s([att(s_vidth),value([32])]) ]).
port(2,[s([att(name),value([add_a_b])]),
s([att(is_a) ,value([dpath_ctl])]) ,
s([att(ovner),id([i])]), s([att(s_vidth),value([8])])
]) . port(3,[s([att(name),value([dpathctl])]),
s([att(is_a) ,value([dpath_ctl])]) ,
s([att(ovner),id([l])]), s([att(s_vidth),value([4])])
]) . port(4,[s([att(name) ,value([pcclks])]) ,
s([att(is_a),value([dpath_clk])]), s([att(ovner),id([l])]), s([att(s_vidth),value([2])]) ]) .
port(6,[s([att(name),value([dataout])]), s([att(is_a),value([dpath_data_out])]), s([att(ovner),id([l])]),
s([att(s_vidth),value([32])])
]).
block(2,[ s([att(design_tool),id([2])]),
s([att(op_type),value([memory])]), s([att(port),id([6,7,8,26])]), s([att(parent),id([7])]), s([att(name) ,value([mem])]) , s([att(adj_list),id([8,l,3,4,6])]), s([att(h_des),value([matrice(64,32) of memory(i,i)])]) ]) .
port(26,[s([att(name),value([memctl])]), s([att(is_a),value([rv_ctl])]),
s([att(ovner),id([2])]), s([att(s_vidth) ,value([2])]) ,
s([att(s_cat),value([sigin])])
]).
port(6,[s([att(name),value([aemad)]), s([att(is_a),value([rv_ctl])]),
s([att(owner),id([2])]), s([att(s_vidth),value([7])]), s([att(s_cat),value([sigin])]) ]).
port(7,[s([att(name),value([aeaclks])]), s([att(is_a),value([aea_clk])]), s([att(owner),id([2])]), s([att(s_width),value([2])]), s([att(s_cat),value([sigin])]) ]) .
port(8,[s([att(name),value([datamem])]), s([att(is_a) ,value([mem_data])]) ,
s([att(owner),id([2])]), s([att(s_width),value([16])]) ]) .
block(3,[
124
s([att(design_tool),id([2])]),
s([att(op_type) ,value([interpolator])]) ,
s([att(port),id([9,10,ll,12])]),
s([att(parent),id([7])]),
s([att(name),value([interpolator])]), s([att(adj_list),id([l,2,4,5,6])]),
s([att(h_des),
]) ]) .
value([aatrice(16,4) of adder(2,l),
array(16) of register(l,l) ])
port(9,[s([att(name),value([datainint])]), s([att(is_a) ,value([adder_in_l])]) , s([att(owner),id([3])]), s([att(s_width),value([16])]) ]) .
port(10,[s([att(name),value([ctlint])]), s([att(is_a),value([adder_ctl])]),
s([att(owner),id([3])]),
s([att(s_width),value([4])])
]).
port(ll,[s([att(name),value([intclks])]), s([att(is_a),value([adder_clk])]),
s([att(ovner),id([3])]),
s([att(s_vidth),value([2])])
]).
port(12,[s([att(naae) ,value([dataoutint])]) ,
s([att(is_a),value([adder_out])]),
s([att(ovner),id([3])]), s([att(s_vidth),value([16])]) ]).
block(4,[ s([att(design_tool),id([l])]), s([att(op_type) ,value([pla])]) ,
s([att(port),id([13,14,15])]),
s([att(parent),id([7])]),
s([att(name),value([pla])]), s([att(adj_list),id([8,6,5,3,2,l])]), s([att(h_des), value([pla(10,18)])])
]) .
port(13,[s([att(name),value([placlksin)]),
s([att(is_a),value([pla_clk])]), s([att(ovner),id([4])]),
s([att(s_vidth),value([2])])
]).
port(14,[s([att(name),value([codein])]), s([att(is_a) ,value([pla_ctl_in])]) ,
s([att(ovner),id([4])]),
s([att(s_vidth),value([9])]) ]) .
port(15,[s([att(name),value([codeout])]), s([att(is_a),value([pla_ctl_out])]),
s([att(ovner),id([4])]), s([att(s_vidth),value([18])])
).
block(5,[ s([att(design_tool),id([2])]),
125
s([att(op_type), value([clock,superbuffer])]),
s([att(port),id([16,18,19])]),
s([att(parent),id([7])]),
s([att(name),value([clks])]), s([att(adj_list),id([8,6,l,2,3,4])]), s([att(h_des),value([aatrice(2,6) of superbuffer(6,6)])])
]).
port(16.[s([att(name).value([phi_l_2])]).
s([att(is_a).value([superbuffer_in])]).
s([att(ovner).id([5])]). s([att(s_vidth).value([2])]). s([att(s_type).value([clock])]).
s([att(s_cat).value([sigin])]) ]).
port(18.[s([att(name).value([phil])]).
s([att(is_a).value([superbuffer_out])]).
s([att(ovner).id([5])]).
s([att(s_vidth).value([l])]). s([att(s_type).value([clock])]).
s([att(s_cat).value([sigout])]) ]) .
port(19.[s([att(name).value([phi2])]). s([att(is_a).value([superbuffer_out])]). s([att(ovner).id([5])]). s([att(s_vidth).value([l])]).
s([att(s_type).value([clock])]).
s([att(s_cat).value([sigout])]) J).
block(6.[
126
s([att(design_tool).id([2])]). s([att(op_type).value([adder])]).
s([att(port).id([20.21.22.23.24])]). s([att(parent).id([7])]). s([att(name).value([adder])]).
s([att(adj_list).id([8.3.4.5])]). s([att(h_des).value([array(32) of adder(2.1)])]) ]).
port (20. [s([att(name).value([adderinl])]).
s([att(is_a).value([adder_in_l])]). s([att(ovner).id([6])]).
s([att(s_vidth).value([16])])
]).
port(21.[s([att(name).value([adderin2])]). s([att(is_a).value([adder_in_2])]).
s([att(ovner).id([6])]).
s([att(s_vidth).value([16])]) ]) .
port (22. [s([att(name).value([adderclks])]).
s([att(is_a).value([adder_clk])]).
s([att(ovner),id([6])]), s([att(s_width),value([2])])
]).
port(23,[s([att(name),value([adderout])]), s([att(is_a),value([adder_out])]),
s([att(ovner),id([6])]), s([att(s_width),value([16])]) ]).
port(24,[s([att(name) ,value([adderctl])]) , a([att(is_a),value([adder_ctl])]),
B([att(owner),id([6])]), B([att(B_width),value([2])])
]).
link([1,2], [ B([att(c_deB),
127
value([[5: 20 upto 26, 25 o upto 7]])])
]).
link([1,3], [
B([att(c_deB),
value([[5: 16 upto 19, 10
]).
link ([1 ,4] ,[ B([att(c_deB),
value([
o upto 3]])])
[2 : 0 upto 7, 15 : 0 upto 7],
[3, 15 : 8 upto 11]
])
]).
])
link([1,5], [ B([att(c_des),
])
]).
value([ [4 0, 18],
[4 : 1, 19]
])
link([2,3], [
B([att(c_deB),
value([
[8, 9 : 0 upto 15]
]) ]).
])
link([2,4], [
s([att(c_des) ,
value([
])
]).
[25, 15 12 upto 13]
])
link([2,5], [
s([att(c_des),
value([
])
]).
])
[7 0, 18],
[7 : 1, 19]
link([3,4], [
s([att(c_des),
value ( [
]) ]).
]) [10, 15 14 upto 15]
link([3,5], [
s([att(c_des),
]) n.
value([
[11 0, 18],
[11 1, 19]
])
link([3,6], [
s([att(c_des) ,
value([
])
]).
[12 : 0 upto 15, 21 0 upto 15]
])
link([4,5], [
s([att(c_des),
value ( [
128
])
]) .
[13 O. 18],
[13 1. 19]
])
link ([4. 6] • [
s( [att(c_des) •
value([
]) ]).
])
[15 : 16 upto 17. 24]
link([5.6]. [
s([att(c_des).
value ( [
])
D.
])
link([1.8]. [
[18.22 0].
[19.22 1]
s ([att (c_des) •
value([
]).
]) ])
[1: 0 upto 31. 26].
[5: 27 upto 31. 27]
link ([2. 8] • [
s([att(c_des) •
value([[8. 28]])
])
]) . link([4.8]. [
s([att(c_des).
value([[14. 29]])
])
]) .
link([5.8]. [
s( [att(c_des).
value([[16. 30]])
])
]) .
129
link ([6 ,8] ,[
s([att(c_des) ,
value([[20, 31],
[23,32]])
]) ]) .
130
Appendix C
Rule Examples
C.l Some RACG Building Rules
The following are some rules used in the RACG building process.
If
fbd is an racg
then
set racg found
*1 rule (1, [racg],
) .
1* if
then
list (current_fbd_context , [Idfbdl_]) ,
\+(c_pr_(block ,Idfbd ,is_racg ,value , [true,_,_]»,
is_an_racg(Idfbd)
],
1.0,
0.0,
],
1.0,
0.0
c_pl_(block,Idfbd,is_racg,value, [true,l.0,O.0])
there are blocks which are complex nodes
and one of them is of a clock type
remove its position to last consideration
132
and update the context
*1 rule(2, [racg],
).
1* if
list (current_fbd_context, [Idl_]),
c_fetch_all_(block,Id,complex_nodes,id,L),
=(L, [Idblldl]),
c_fetch_(block,Idb,op_type,value,clock)
] , 0.5,
0.5,
c_del_all_(block,Id,complex_nodes,id,_),
append(Idl,[Idb] ,NidI) ,
c_pl_all_(block,Id,complex_nodes,id,Nidl)
],
0.5,
0.5
there is a complex block which communicates with at least two blocks
of a chain_block and with the master of the chain
and the block not being a member of the chain
then
*1
leave the com. with one block of the chain
and passthrough to this block to the others in the chain
and update the context
rule(4, [racg],
) .
list (current_fbd_context , [Idfbdl_]) ,
c_pr(block,Idfbd,chain_block,id,Idchain),
c_pr_(chain_block,Idchain,master,id,Id),
c_pr_(chain_block,Idchain,path,value,Path) ,
c_pr_all_(block,Idfbd,complex_nodes,id,Ln),
missing([IdIPath] ,Ln,Lmis) ,
member(Idb,Lmis),
c_fetch_all_(block,Idb,adj_list,id,Lad),
intersect(Path,Lad,[Vl,V2IT])
],
0.8,
0.2,
pass_all(Idb,[Vl,V2IT] ,Path,Ldeleted) ,
update_context (complex_edges ,Idfbd,Ldeleted),
c_del_(block,Idfbd,complex_nodes,id,Idb),
message('Edges ' and Ldeleted and ' have been deleted.')
],
0.8,
0.2
1* if
133
a block is member of the path of a chain
and the block is not the first nor the last in the path
and the block is corner
then
there is a big chance that it could not be a corner block.
*1 rule (5 , [racg],
) .
1* if
list (current_fbd_context , [1dfbdl_]) ,
c_pr_(block, Idfbd, chain_block, id,Idchain),
c_pr_(chain_block,Idchain, path, value,[FIT]),
last(X,T),
member(Id,T),
\+(1d=X),
c_fetch_(block,Id,corners,value,1) ,
\+(1=0)
] , 0.8,
0.2,
c_del_all_(block,Id,corners,value,_),
message('There is a big chance that block' and Id
and ' could not be a corner block.') ],
0.8,
0.2
Vi has a shortfall
and Vi is part of a chain block
and has three adjacency existing Lad
and there is a block V5 which is adjacent to two of Lad
and V5 is not a member of Lad
then
*1
Put a defacto adjacency between Vi and V5
and update the shortfall list
rule(6, [racg],
[ list(current_fbd_context,[1dfbdl_]),
c_fetch_all_(block,Idfbd,shortfall,id,Lsh),
c_pr(block,Idfbd,chain_block,id,1dchain),
c_pr(chain_block,Idchain,path,value,P),
member(Vi,Lsh),
) .
member_(V1,P),
project(L,R,P, [V1]),
c_fetch_all_(block,L,adj_list,id,Ladj),
c_fetch_all_(block,R,adj_list,id,Radj),
intersect(Ladj,Radj,[V2,V3,V4]),
c_pr(chain_block,Idchain,master,id,M),
missing([M, V1] ,[V2, V3, V4] ,[V])
],
0.8,
0.2,
[ defacto (V1, [V]) ,
ack_shortfall(Idfbd,V1),
message('A defacto adjacency between'
and V1 and ' and ' and V and
134
, has been created, due to a shortfall of ' and Vi and '.') ],
0.8,
0.2
Vi has a shortfall and
Lad(Vi) is adj_list of V1
there are two element of Lad(Vi) V2 and V3
V2 \= Idext and V3 \= Idext and V2 not adjacent to V3
and adj list of V2 is Ladj(V2)
and adj list of V3 is Ladj(V3)
and List is (intersect(Ladj(V2),Ladj(V3) - Vi)
and List is not empty
then
*/
pick V5 a member of List
Put a defacto adjacency between V1 and V5
and update shortfall list
rule (7 , [racg],
[ list (current_fbd_context, [Idfbdl_]),
c_fetch_all_(block,Idfbd,shortfall,id,Lsh),
c_fetch_all_(block,Idfbd,ext,id,Idext),
member(V1,Lsh),
c_fetch_all_(block,V1,adj_list,id,Lv1),
missing([Idext],Lvl,Nlvl),
two_members(V2,V3,Nlvl),
c_fetch_all_(block,V2,adj_list,id,Lv2),
\+(member(V3,Lv2»,
c_fetch_all_(block,V3,adj_list,id,Lv3),
) .
1* if
intersect (Lv2,Lv3,Ladj),
missing([V1ILv1] ,Ladj ,[HIT]) ],
0.75,
0.2,
[ member(V5,[HIT]),
defacto(V1,[V5]),
ack_shortfall(ldfbd,V1),
message('A defacto adjacency betveen '
and V1 and ' and ' and V5 and
135
, has been created, due to a shortfall of ' and V1 and '.')
],
0.8,
0.2
there is shortfall of corners
and V1 has a shortfall and
and V1 is adjacent to exterior
and V1 has at most one corner
and ve are not performing a constructive
building of RACG
then
*1
add to V1 another corner
and update shortfall list
rule (8, [racg],
[ list (current_fbd_context , [ldfbdl_]),
get_alI_corners (ldfbd,Lc),
length_lt(Lc,4) ,
c_fetch_(block,ldfbd,ext,id,ldext),
c_fetch_all_(block,ldfbd,shortfall,id,Lsh),
member(V1,Lsh),
c_fetch_(block,V1,adj_list,id,ldext),
c_fetch_(block,V1,corners,value,lcorner),
=<(Icorner, 1),
\+(c_pr_(block ,ldfbd ,cve_racg , value , [true,_,_]»
],
0.7,
0.2,
Hevc is (lcorner + 1),
c_repl_(block,V1,corners,value,lcorner,Hevc),
ack_shortfall(ldfbd,V1),
message('Another corner has been added to block' and V1)
],
) .
1* if
0.8,
0.2
number of corners more than 4
136
and there is a corner block with minmum density and not
in danger of shortfall
and we are not in a constructive RACG context
then
remove a corner attribute from the block
*1 rule(9, [racg],
) .
1* if
list (current_fbd_context, [Idfbdl_]),
get_alI_corners (Idfbd,Lcorners),
length_gt(Lcorners,4) ,
c_fetch_(block,Idfbd,ext,id,Idext),
get_min_density(Idext,Lcorners,Vd),
\+(c_pr_(block,Idfbd,cve_racg,value, [true,_,_]»
],
0.2,
0.8,
revoque_corners([Vd]),
message('A corner has been removed from block' and Vd and '.')
],
0.2,
0.8
block involved is to be designed with a tool having
limitations on the positions of its outputs
and the block is not the master of any existing chain
of the same type
and there is a path between the blocks connected
to the outputs
and the path is transparent
then
*1
form a block string of the blocks connected to its output
and update the current context
rule(11, [racg],
[ list (current_fbd_context , [Idfbdl_]) ,
c_fetch_(block,Idfbd,ext,id,Idext),
) .
1* If
137
c_fetch_all_(block,Idfbd,children,id,Lch),
missing([Idext] ,Lch,Lchl) ,
member(Id,Lchl),
c_fetch_(block,Id,design_tool,id,Idd),
fetch_(design_tool,Idd,io_limitations,value, [sigout,l]} ,
\+{c_pr(chain_block,Idchain,master,id,Id},
c_pr(chain_block,Idchain,master_lim ,value ,sigout},
c_pr_(block,Idfbd,chain_block,id,Idchain}},
c_fetch_all_(block,Id,adj_list,id,Lbbl},
c_fetch_(block,Idfbd,ext,id,Idext},
missing([Idext] ,Lbbl,Lbb} ,
filter(Lbb,Id,sigout,[HeadILb]},
m_e_p([HeadILb] ,Path,C} ,
transparent_chain(Path,W,A}
],
W, A, [ chain_blocks (Path,Ldeleted),
message('A block string' and Path and
, could be formed. The edges' and Ldeleted and ' would be deleted.'},
update_context (complex_edges ,Idfbd,Ldeleted},
new_id(chain_block,Idc},
c_pl_(chain_block,Idc,master_lim,value,sigout},
c_pl_(chain_block,Idc,master,id,Id},
c_pl_(chain_block,Idc,path,value,Path} ,
c_pl_(chain_block ,Idc ,transparent ,value, [W,A]} ,
c_pl_(block,Idfbd,chain_block,id,Idc}
],
W, A
constructive building
has not been tried
and communication are not solved
then
set up a contructive RACG building context
*1 rule (20 , [racg],
[ list (current_fbd_context , [Idfbdl_]} ,
\+(c_pr_(block,Idfbd,cve_racg,value, [true,_,_]}},
\+(is_an_racg(Idfbd})
],
0.2,
0.8,
message('Trying constructive building.'},
) .
1*
138
c_pl_(block,Idfbd,cve_racg,value, [true,1.0,0.0])
],
0.2,
0.8
If no corners blocks were assigned
and we have less than 4 corner blocks
then assigned at least 4 corners (to the Dingo principle)
*1 rule(23,[racg],
) .
[ list (current_fbd_context , [Idfbdl_]) ,
\+(c_pr_(block,Idfbd,corners_assigned,value, [true,_,_]»,
get_all_corners(Idfbd,Corners),
length (Corners ,Corners_count) ,
«Corners_count, 4) ] , 0.5,
0.5,
c_pl_(block ,Idfbd,corners_assigned,value , [true,l.0,O.0 ]),
c_pr_(block,Idfbd,ext, id,Idext),
succeed(assign_corners(Idfbd,Idext»,
message('Assigning corners attributes to blocks with lID.')
],
0.5,
0.5
If context is RACG building
then
and block shortfalls were not found
findall the blocks with sh~rtfall
and update context
*1 rule(24,[racg],
[ list (current_fbd_context, [Idfbdl_]),
\+(c_pr_(block,Idfbd,shortfall_found,value, [true,_,_]»
],
0.5,
0.5,
c_pl_(block,Idfbd,shortfall_found,value,[true,l.0,O.0]),
) .
139
find_adj_shortfall(Idfbd,Ls),
c_pl_all_(block,Idfbd,shortfall,id,Ls),
message('Blocks having shortfall (not enough adjacency) ],
0.5,
0.5
If contert is RACG building
then
and the complex edges vere not found
find all complex edges
a update context
*1 rule(25,[racg],
[ list (current_fbd_context , [Idfbdl_]) ,
\+(c_pr_(block,Idfbd,complex_edges_found,value, [true,_,_] » ],
0.5,
0.5,
, and Ls)
c_pl_(block ,Idfbd,complex_edges_found,value , [true,l.0,O .0]),
c_pr_all_(block,Idfbd,edges,id,Ledges),
) .
c_pr_(block,Idfbd,ext, id,Idext),
g_s_c_e(Ledges,Lce,Idfbd,Idext,Le),
c_pl_all_(block,Idfbd,complex_edges,id,Le),
message('complex edges: ' and Le) ],
0.5,
0.5
context RACG building
complex nodes vere not found
complex edges vere found
then
find all complex nodes
and update the context
*1 rule(26,[racg],
[ list(current_fbd_context,[Idfbdl_]),
\+(c_pr_(block ,Idfbd,complex_nodes_found,value , [true,_,_] », c_fetch_all_(block,Idfbd,complex_edges,id,Le)
) .
1* If
],
0.5,
0.5,
140
[ c_pl_(block,Idfbd,complex_nodes_found,value,[true,l.0,O.0]),
c_pr_(block,Idfbd,ext,id,Idext),
g_s_c_n(Le,Idext,Lsor),
c_pl_all_(block,Idfbd,complex_nodes,id,Lsor),
message('complex nodes: ' and Lsor) ],
0.5,
0.5
adjacency affinities were not found
complex nodes were found
then
*1
find all adjacency affinity lists
update context
rule (27 , [racg] ,
) .
list(current_fbd_context,[Idfbdl_]),
\+(c_pr_(block,Idfbd,c_n_a_a_found,value,[true,_,_]»,
c_fetch_all_(block,Idfbd,complex_nodes,id,Lsor)
],
0.3,
0.7, c_pl_(block,Idfbd,c_n_a_a_found,value,[true,l.0,O.0]),
get_c_n_a_a(Lsor,Lcnaa),
c_pl_all_(block,Idfbd,c_n_a_a,id,Lcnaa),
message('adjacency affinity list: ' and Lcnaa)
],
0.3,
0.7
C.2 Some Rectangular Topology Selection Rules
The following rules are used in the solution selection process.
1* If
context is block modelling
and the is no value available for the block op-type
and same-type as random is known
141
then
assign random model to the block
rule (103, [modelling],
) .
1* if
[ list(modelling,[Idl_]),
\+(c_fetch_(block, Id, op_type, value,_»,
fetch_(same_surrounds, Idps ,same_surrounds ,value ,random) ,
fetch_(same_surrounds,Idps,the_type,value,Op)
],
0.2,
O.S,
[ c_pl_(block,Id,model,value,Op),
message('! possible model for block' and Id and ' is ' and Op)
],
0.2,
O.S
context is eliminating redundant transformation
and transformations are not ready
and there is a transformation mirror in y and rotate 270 degrees
and there is a transformation mirror in x and rotate 90 degrees
then
remove the transformation mirror in y mirror in x
*1 rule (20S,
[block_configurations],
[
) .
1* if
stack (block_configurations , [Idtop,Idblock]) ,
\+(c_pr(rec_top,Idtop, model_transformations_ready,value,[true,_,_]»,
c_pr_(rec_top,Idtop, removing_transformations_redundancy,value,[true,_,_]),
c_pr_(rec_top,Idtop, model_transformations ,value , [my,270]),
c_pr_(rec_top,Idtop, model_transformations,value,[mx,90])
],
1.0,
0.0,
c_del_(rec_top , Idtop ,model_transformations ,value , [my,270] ),
message('Redundant transformation: my, 270 removed for block' and Idblock)
],
1.0,
0.0
142
block surrounds show two symetric sides (T = B)
then
eliminate redundant transformations
*1 rule(211,
[block_configurations],
) .
stack (block_configurations, [Idtop,Idblock]),
c_pr_(rec_top,Idtop,model_transformations_ready,value,[true,_,_]),
c_pr_(block,Idblock,model,value,Model),
fetch(Model,Model_id,surrounds,value,Lm),
\+(c_pr_(rec_top,Idtop,block_configurations,value,
[_,Idblock,Model,Model_id,my,O]»,
=(Lm,[Ll,L2,Ll,L4]),
\=(L2,L4),
c_pr_(rec_top,Idtop,model_transformations,value,[my,O]) ],
0.8,
0.2,
c_del_(rec_top,Idtop,model_transformations,value,[my,O]),
message('Redundant transformation: my, 0 removed for block' and Idblock)
],
1.0,
0.0
C.3 Examples of a Communication Border Evaluation Rule
The following rules are used in the communication border estimation process.
1* if
context estimating borders
block is a corner and has a model
then
find its surrounds from model
and adapt the model
and estimate border
of its communication according to corners possibilities
rule(301,
[border_estimation],
stack (border_estimation, [Idtop,V]),
c_fetch_(rec_top,Idtop,surrounds,id,[V,Lsol]) ,
) .
1* if
c_fetch_(block ,V ,corners , value ,C) ,
>(C,O),
143
c_fetch_(rec_top, Idtop ,best_conf ,value , [V,architecture,_ ,
Model,Model_id,Angle,Mir]) ,
present_(Model,Model_id,pitch_factor,value,LsurO)
] , 1.0,
0.0, [
c_fetch_(block,V,parent,id,Idfbd),
c_fetch_(block,Idfbd,ext,id,Idext),
mirror_ports (LsurO ,LsurOO ,Mir) ,
rotate_ports(LsurOO,Angle,Lmod) ,
estimate_corner_borders(Idext,Idtop,V,Lsol,Lmod),
c_pl_(rec_top, Idtop ,border_est imation_done ,value , [V,tr ue,l.0,O.0]),
message('Border_estimation done for block: ' and V)
],
1.0,
0.0
context is border estimation for communication
description
and the communication has not been processed
then evaluate the borders of all the descriptions
and eval the estimate
*1 rule (305,
[border_estimation],
stack (border_estimation , [Idtop,Side,V,Lc,Lpst]),
\+(c_pr_(rec_top,Idtop ,com_border ,value,_))
],
0.5,
0.2,
findall(Nl,
{member([Sn,Den],Lc),
ifthenelse(
member([Sn,Pitch_factor],Lpst),
Nl is Den * Pitch_factor,
{ifthenelse(iscornerside(Idtop,V,Side) ,true,
{c_pl_(rec_top,Idtop,rerouting,value,[V,Side,Sn,Den]) ,
message('Sig , and Sn and ' needs rerouting area
estimation for density s ,
) .
),
}
},
Le
144
and Den and ' on side ' and Side)}
) , fetch_(current_technology,_,name,value,Tech),
fetch_(Tech,_,com_sep,value,Pitch_factor),
Ni is Den * Pitch_factor
sum_list(Le,E),
c_pl_(rec_top,Idtop,com_border,value,E),
message('Estimate border according to description is done for block'
and V and ' and Description: ' and Lc and ' on side: ' and Side) ],
0.5,
0.2
Bibliography
[1] O. Akin. How do architects design? In IFIP, editor, Pmc. AI and PR in CAD,
pages 65-103, North-Holland, 1978.
[2] C. Alexander. Notes on the synthesis of form. Harvard University Press, 1964.
[3] Arity PROLOG. A compiler/interpreter PROLOG system, Arity Corporation, 358
Baker Av. Ma. 01742, USA. Runs on an IBM PC/XT/AT type machine.
[4] Cyrus S. Bamji, Charles E. Hauck, and Allen Jonathan. A design by example regular
structure generator. VLSI Memo N. 84-214, MIT, 1984.
[5] N. Bergmann. A case study of the F .I.R.S. T silicon compiler. In Computer Science
Press, editor, Proc. of 3rd Caltech Conference on VLSI, pages 379-394, 1983.
[6] J ayaram Bhasker and Sartaj Sahni. A linear algorithm to find a rectangular dual of a
planar triangulated graph. In Proc. IEEE/ACM 23rd Design Automation Conference,
pages 108-114, June 1986.
[7] J .R. Black. Electromigration and failure in electronics: An introduction. Proc. IEEE,
59(10):1409-1418,1971.
[8] J.A. Bondy and U.R.S Murty. Graph theory with application. MacMillan Press, 1976.
[9] M.A. Breuer. A class of min-cut placement algorithms. In Proc. 14th IEEE/ACM
Design Automation Conference, pages 284-290, 1977.
[10] Harold Brown, Christopher Tong, and Gordon Foyster. Palladio: an exploratory envi
ronment for circuit design. Computer, (IEEE Computer Society), 16(12):41-56, 1983.
[11] B.G. Buchanan and E. Shortliffe. Rule-Based Expert Systems. Addison-Wesley Read
ing, Mass., 1984.
[12] CADDS 2. CADDS 2/VLSI general reference. Computervision Corporation, 201
Burlington Rd, Massachusetts, U.S.A.
[13] W.F. Clocksin and C.S Mellish. Programming in Prolog. Springer-Verlag, Berlin Hei
delberg, 1981.
146
[14] D. Coggins, D.J. Skellern, A. Dunn, and P. Allworth. CAD tools for custom VLSI
assembly with applications. In Proc. Microelectronics Conference VLSI 87, pages 73-
78, Melbourne, Australia, April 1987.
[15] R.D. Coyne and J.S. Gero. Semantics and the organisation of knowledge in design.
Design Computing, 1(1):68-89, 1986.
[16] G.B. Dantzig. Linear Progmmming and Extensions. Princeton University Press, 1963.
[17] A.R Deas and I.M Nixon. Chromatic idioms for automated VLSI floorplanning. In
Proc. VLSI85 Conference, pages 55-64, Japan, 1985.
[18] C.M. Eastman. Automatic space planning. Artificial Intelligence, (4):41-64, 1973.
[19] A. Foz. Some observations of designer behaviour in the parti. In Polytechnic of Cen
tral London, editor, Proceedings of Design Activity International Conference, 1973.
[20] Aki Fujimura. VLSI Micro-Cell Layout Automation. VLSI Memo N. 82-107, MIT,
1982.
[21] P. Galle. An algorithm for exhaustive generation of building floor plans. Communica
tions of the ACM, 24(12):813-825, 1981.
[22] J.S. Gero and M. Balanchandran. A comparison of procedural and declarative pro
gramming languages for the compu tat ion of pareto optimal solutions. Eng. Opt., 9:131-
142,1985.
[23] J.S. Gero and R. Coyne. Logic programming as a means of representing semantics in
design languages. Environment and Planning B, 12:351-369, 1985.
[24] J. Grason. Approach to space planning using graph theory. In Pmc. of 8th Design
Automation Workshop, 1971.
[25] W. Heller, G. Sorkin, and K. Maling. The planar package planner for system designers.
In Proc. 19th IEEE/ACM Design Automation Conference, pages 253-259, 1982.
[26] Max Henrion. Automatic space planning: A postmortem? In IFIP, editor, Pmc. AI
and PR in CAD, pages 175-191, North-Holland, 1978.
[27] J. Hopcroft and R. Tarjan. Efficient planarity testing. ACM, 21(4):549-568, October
1974.
[28] M.A. Jabri and D.J. Skellern. Implementation of a knowledge base for interpreting and
driving integrated circuit floorplanning algorithms. International Journal for Artificial
Intelligence in Engineering, 2(2):82-92, April 1987.
147
[29] D. Johannsen. Bristle blocks: A silicon compiler. In ACM, editor, Proc. IEEE/ACM
16th Design Automation Conference, pages 310-313,1979.
[30] B.W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs.
The Bell System Tech. J., 49(2):291-301, Feb. 1970.
[31] S. Kirkpatrick, C.D. Gelatt, and M.P. Vecchio Optimization by simulated annealing.
Science, 12(220):671-680, May 1983.
[32] P.W. Kollaritsch and N.H.E. Weste. A rule based symbolic layout expert. VLSI design,
62-66, August 1984.
[33] James Joseph Koschella. A Placement/Interconnect Channel Router: Cutting Your PI
into Slices. VLSI Memo N. 82-73, MIT, 1982.
[34] T.J. Kowalski and D.E. Thomas. The VLSI design and automation assistant: proto
type system. In Proc. IEEE/ ACM 20th Design Automation Conference, pages 479-483,
1983.
[35] K. Kozminski and E. Kinnen. An algorithm for finding a rectangular dual of a planar
graph for use in area planning for VLSI integrated circuits. In Proc. IEEE/ACM 21th
Design Automation Conference, pages 655-656, June 1984.
[36] David P. Lapotin and Stephen W. Director. Mason: a global floor-planning tool. In
Proc. ICCAD-85 Conference, pages 143-145, Santa Clara, California, USA, 1985.
[37] U Lauther. A min-cut placement algorithm for general cell assemblies based on a graph
representation. In Proc. IEEE/ACM 16th Design Automation Conference, pages 1-10,
1979.
[38] Andre Leblond. CAF: a computer-assisted floorplanning tool. In Proc. 20th
IEEE/ACM Design Automation Conference, pages 747-753, 1983.
[39] S.M. Leinwand and Y. Lai. An algorithm for building rectangular floorplans. In Proc.
21st IEEE/ACM Design Automation Conference, pages 663-664,1984.
[40] C.E. Leiserson and R.Y Pinter. Optimal Placement For River Routing. Memo N.
81-66, MIT, Cambridge, Massachusetts 02139, USA, 1981.
[41] K. Maling, S. Mueller, and W. Heller. On finding the most optimal rectangular package
plans. In Proc. 19th IEEE/ACM Design Automation Conference, pages 663-670,1982.
[42] Z. Markusz. Design in logic. Computer-Aided Design, 14(6):335-343, Nov 1982.
[43] C. Mead and L. Conway. Introduction to VLSI Systems. Addison-Wesley Publishing
Company, 1980.
148
[44] G.E. Moore. Are we really ready for VLSI? In Caltech Conference on VLSI, 1979.
[45] G.E. Moore. VLSI: Some Fundamental Challenges. Library of Congress N. 79-93146,
IEEE Catalog N. ECHO 158-6, 1980.
[46] K. Morris and A. Taylor. Basser Prolog User's Manual. Technical Report, Basser
Department of Computer Science, University of Sydney, Australia, 1984.
[47] R.C. Mosteller. An experimental composition tool. In Proc. Microelectronics Confer
ence 1982, pages 130-135, 1982.
[48] J .C. Mudge. VLSI Chip Design at the Crossroads. Gray J.P. editor, Academic Press,
1981.
[49] J .C. Mudge and R.J. Clarke. Australia's first multi-project chip implementation sys
tem. In Proc. Microelectronics Conference 1982, pages 72-77, 1982.
[50] L. Nagel. Spice 2- A computer program to simulate semiconductor circuits. UCB
ERL-M250, Electronic research laboratory, University of California, Berkeley, 1975.
[51] NAG-H02BAF. An Integer Simplex Algorithm, H- Operation Research,
NAGFLIB:1137/762:M[{5. NAG, 1975.
[52] Tak-Kwong Ng and Lennart Johnsson. Generation of layouts from MOS circuit
schematics: a graph theoretic approach. In Proc. 22nd IEEE/ A CM Design Automation
Conference, pages 39-45, 1985.
[53] R. Otten. Automatic floorplan design. In Proc. 19th IEEE/ACM Design Automation
Conference, pages 261-267, 1982.
[54] L. M. Pereira. Artificial intelligence techniques in automatic layout design. In IFIP,
editor, Proc. AI and PR in CAD, pages 159-173, North-Holland, 1978.
[55] POPLOG. A prolog interpreter written in popl1. Runs on a variety of machines
including VAX/VMS.
[56] Quintus Prolog. A compiler/interpreter PROLOG system, Quintus Computer Sys
tems, inc. Mountain View, California, USA. Runs on VAXs and SUN stations.
[57] M.C. Revett. Custom CMOS design using hierarchical floor planning and symbolic
cell layout. In Proc. ICCAD-85 Conference, pages 146-148, Santa Clara, California,
USA,1985.
[58] Ronald L. Rivest. The" PI" (Placement and Interconnect) System. VLSI Memo N.
82-74, MIT, 1982.
149
[59] James Allely Rowson. Understanding Hierarchical Design. PhD thesis, California
Institute of Technology, 1980.
[60] C. Sechen and A. Sangiovanni-Vincentelli. The timberwolf placement and routing
package. In Proc. IEEE Custom Integrated Circuits Conference, 1984.
[61] D.J. Skellern, M.A. Jabri, D.J. Coggins, J.J. McKirdy, and A. Dunn. VLSI systems for
image formation - a case study. In Proc. Microelectronics 86 Conference, pages 99-107,
Adelaide, Australia, May 1986.
[62] W.S. Song and L.A Glasser. Power distribution techniques for VLSI circuits. In Proc.
MIT Conference on Advanced Research in VLSI, pages 45-52, January 1984.
[63] J. F. Sowa. Conceptual Structures. Addison-Wesley Publishing Company, Mass., 1984.
[64] I.E Sutherland and C.A. Mead. Microelectronics and computer science. Scientific
American, 237(3):210-228, 1977.
[65] R. E. Tarjan. An Efficient Planarity Algorithm. Stan-CS-244-71, Computer Science
Department, School of Humanities and Sciences, Stanford University, 1971.
[66] L.M. Terman. Some directions in VLSI technology. In Australia Institute of Engineers,
editor, Proc. Microelectronics Conference VLSI 1987, pages 1-5, Melbourne, 1987.
[67] C.L Wardle, C.R. Watson, C.A. Wilson, J.C Mudge, and B.J Nelson. A declara
tive design approach for combining macrocells by directed placement and constructive
routing. In Proc. 21st IEEE/ ACM Design Automation Conference, 1984.
[68] C.R. Watson. A Floorplan Algeb7'a and Composition Paradigm for VLSI Design.
CSIRO VLSI Program Technical Report VLSI-TR-83-3-1, Commonwealth Scientific
and Industrial Research Organisation, Australia, 1983.
[69] N. Weste. Virtual grid symbolic layout. In Proc. 18th IEEE/ ACM Design Automation
Conference, pages 225-233, Nashville,TN, June 1981.
[70] N. Weste and B. Ackland. A pragmatic approach to topological symbolic IC design.
In Proc. 1st international conference on VLSI, pages 117-129, Edinburgh, Scotland,
U.K., August 1981.
Lecture Notes in Engineering
Edited by C.A. Brebbia and S.A. Orszag
Vol. 40: R. Borghi, S. N. B. Murhty (Eds.) Turbulent Reactive Flows VIII, 950 pages. 1989
Vol. 41: W. J. Lick Difference Equations from Differential Equations X, 282 pages. 1989
Vol. 42: H. A. Eschenauer, G. Thierauf (Eds.) Discretization Methods and Structural Optimization -Procedures and Applications Proceedings of a GAMM-Seminar October 5-7,1988, Siegen, FRG XV, 360 pages. 1989
Vol. 43: C. C. Chao, S. A. Orszag, W. Shyy (Eds.) Recent Advances in Computational Fluid Dynamics Proceedings of the US/ROC (Taiwan) Joint Workshop in Recent Advances in Computational Fluid Dynamics V, 529 pages. 1989
Vol. 44: R. S. Edgar Field Analysis and Potential Theory XII, 696 pages. 1989
Vol. 45: M. Gad-el-Hak (Ed.) Advances in Fluid Mechanics Measurements VII, 606 pages. 1989
Vol. 46: M. Gad-el-Hak (Ed.) Frontiers in Experimental Fluid Mechanics VI, 532 pages. 1989
Vol. 47: H. W. Bergmann (Ed.) Optimization: Methods and Applications, Possibilities and Limitations Proceedings of an International Seminar Organized by Deutsche Forschungsanstalt fUr Luft- und Raumfahrt (DLR), Bonn, June 1989 IV, 155 pages. 1989
Vol. 48: P. Thoft-Christensen (Ed.) Reliability and Optimization of Structural Systems '88 Proceedings of the 2nd IFIP WG 7.5 Conference London, UK, September 26-28, 1988 VII, 434 pages. 1989
Vol. 49: J. P. Boyd Chebyshev & Fourier Spectral Methods XVI, 798 pages. 1989
Vol. 50: L. Chibani Optimum Design of Structures VIII, 154 pages. 1989
Vol. 51: G. Karami A Boundary Element Method for Two-Dimensional Contact Problems VII, 243 pages. 1989
Vol. 52: Y. S. Jiang Slope Analysis Using Boundary Elements IV, 176 pages. 1989
Vol. 53: A. S. Jovanovic, K. F. Kussmaul, A. C. Lucia, P. P. Bonissone (Eds.) Expert Systems in Structural Safety Assessment X, 493 pages. 1989
Vol. 54: T. J. Mueller (Ed.) Low Reynolds Number Aerodynamics V, 446 pages. 1989
Vol. 55: K. Kitagawa Boundary Element Analysis of Viscous Flow VII, 136 pages. 1990
Vol. 56: A. A. Aldama Filtering Techniques for Turbulent Flow Simulation VIII, 397 pages. 1990
Vol. 57: M. G. Donley, P. D. Spanos Dynamic Analysis of Non-Linear Structures by the Method of Statistical Quadratization VII, 186 pages. 1990
Vol. 58: S. Naomis, P. C. M. Lau Computational Tensor Analysis of Shell Structures XII, 304 pages. 1990
For information about Vols. '·39 please contact your bookseller or Springer·Verlag.
