Presentation Title Arial 28pt Bold - Keysight · Overview Beyond GaAs vs. CMOS: Finding the right technology mix for a handset PA Module There has been much debate recently about

Welcome

Matthew Ozalas

Senior RF Module Designer

Agilent EEsof EDA

© 2013 Agilent Technologies, Inc.

Overview

Beyond GaAs vs. CMOS: Finding the right technology mix for a

handset PA Module

There has been much debate recently about whether GaAs HBT or Silicon-based CMOS is the better device technology to

use for handset Power Amplifier and Front End Modules. While the choice of active device is a key consideration, companies

who are developing the best products in the market are doing so because they have the most effective mix of technology

which is integrated seamlessly into a single functioning module. This seminar will explore two very different technology mixes

for a handset PA Module, one is built around a CMOS PA core, while another is built around a GaAs PA core. Technology

implications and design techniques will be discussed, and tradeoffs will be illustrated using unique aspects of the multi-

technology flow in ADS.

Matthew Ozalas

RF Power Amplifier and

Front End Module Design Engineer

Focus on the end product, not just the technology


2

What I Hope You’ll Learn …

1. Tips and Techniques for designing an RF Power Amplifier

Module, from device to product

2. Framework for developing a Multi-Technology product

3. How to approach difficult product level integration problems

4. How to apply the design tools efficiently and effectively


3

Agenda

• A Typical Handset PA Module

What it does / Block level diagram

• How to choose what goes into a module

• Efficient ways to go about designing a module

- Mix #1: GaAs core (GaAs PA, Laminate/SMT Match, CMOS Control)

- Mix #2: CMOS core (CMOS PA & Control, IPD Match, QFN Package)

• Common themes and conclusions


4

What Does a Handset Module Do?

•Provides a power amplifier which addresses at least one standard and one

band, with complete output matching and harmonic filtering

•Provides some mechanism by which the power level can be sensed and/or

controlled

•Meets or well exceeds 3GPP specs for the relevant band in question

Can be as simple as a single die in a QFN package or

can have many different IC’s, components, filters, etc.

Source: Microwave Journal

“The III-V vs. Silicon Battle”

Darcy Poulin, SiGe Semiconductor

April, 2009


5

A Typical Handset Front End Module

Multiple technology options exist for implementing any of these functions Each technology choice leads to … more choices! (ie which process?)

Common Features

• Power Amplifier

• Output Matching

• Harmonic Filtering

• Multi Function Controller

• (Switch & ESD Filter)

Other Features

• Power Sense

• T/R Filtering for FDD

• Linearity Enhancement

• Backed off

efficiency enhancement


6

How do you choose the right technology mix?

• Start with a clear target:

– Frequency Bands and Modulation Standards

– Desired size, cost, performance and time to market

• Evaluate internal capabilities

– Existing products ,Manufacturing, Sourcing, Engineering

• Come up with multiple possibilities and brainstorm

– First order estimate: how well target can be met based on experience

– Proposed technology mix should be complete (ie don’t say “we’ll figure

out the packaging later”)

• Mock up and evaluate the proposed architecture

• Iterate


7

Mock Up the Proposed Architecture

Product

Circuit

Interface

Device

Flexibility to reconfigure

“Rapidly Added Complexity”

• Move from a device level to

product level quickly and

efficiently

• Maintain flexibility while moving

upward to understand product

level viability

Interconnects,

Pin-out

Matching, Filtering,

Physical Realization

Topology, Class, Bias, Control

Process, Reliability, Modeling, Size, Loading


8

TECHNOLOGY MIX: GAAS PA

CORE


9

Design Strategy

Product Interconnects,

Pin-out

Circuit Topology, Class, Bias, Control

Interface Matching, Filtering,


Device Process, Reliability, Modeling, Size


10

Understand the Devices and Models

GaAs HBT Devices • High Voltage Handling Capability

• Vbe strongly CTAT

• Reliability dominated by Tj, Jmax often bounds device size

1

http://www.winfoundry.com/

AHBT Model

• Robust convergence

• Accurate fit of III-V device characteristics

High Base Doping, Low Emitter Doping


11

This exercise will arbitrarily assume a maximum current per area as 0.2 mA/um2, and a maximum junction temperature of 145 C, to illustrate technique

Note: Don’t use these! -- always check the specs from the foundry!

Design for Reliability: Preventing Thermal Runaway

BVceoRthIq

kTL

LBVceoRthRbb

***

12

)1(****

max

mAumum

mAax 48120*

2.0*2Im 2

2

6.333)495.01(*17*00109.*3.475*75finger

Rbb

Extract ϕ (T sweep @ 3.5V)

Extract Rth* (T,Vc Sweep)

Start with a current source sweep of a single finger…

1

Liu (see references)

Marsh (see references)


12

Design the RF Output Cell

Starting Point (Vpp, Ipp from Class E)

pktoDCIIdcRLVppIpp

collIppVppPout

*/

**8

1

4224/990

99070.0*)*(*35.10*8

18.2

*

*1.3

mAmAFingersMin

mAIdcIdcW

conductionBClassIdcIpp

VkneeVdcVpp

CTrise

IdcVdcPPRthFingers

SFRthTrise

TTTTj

colldissdissextmutualdev

yreliabilitriseAmb

8.11)7.01(*47.3*42

475

)1(****

max.

Simplified Thermal Analysis*

*Does not include all sources of dissipation, mutual heating, external Rth, or

duty cycle. Scans or thermal simulations highly recommended

Conduction Angle = 180; Imax=Idc*π

Use procedure and equations

Found in Cripps, “RF Power

Amplifiers for Wireless Communications”

2

Rbb / Fingers

Pdc

Poutcoll


13

Choose a Control Scheme

Use a static simulation to validate control

…Use Symbolically Defined Devices to refine control

2

2*Vbe Stack

Emitter

Follower


14

Design the Output Match

OUTPAZZZmid

Typically for high BW,

the middle transform

point is picked to be

the geometric mean

But Parasitics can cause

this to be difficult,

especially if harmonic

filtering is desired …About 0.27 nH for an 0201 Cap

Parasitic Resonance below

2fo (about 1.66G)

Geometric

Mean

More favorable cap value

SMT cap kit : www.murata.com

Parasitic Extraction: SMT Cap Standard LC Matching

3


15

Design the Physical Laminate

Schematic and Optimizer

Parameterized Layout Based Model

Less than 1 second…

3


16

Integrate the Output Match

Optimize Small Signal Impedance at Modular Block Level

…Then do a LS PA simulation

Keep track of Performance degradation

Optimize for

Impedance and

Max Gain

3


17

Perform a Product Level EM …

• First, ensure that the block level sizes and shapes are realistic

at the full laminate level (that is, do an initial layout)

• If continuing with Advanced Model Composer, consolidate and simplify

parameters based on what was learned in previous simulations

Die size estimate based on rule of thumb Ae*X

HBT CMOS

4


18

Simulate Mutual Bondwires

Starting with a multilayer package stack up… (in this case a generic FR-4 based 4L laminate substrate)

1. Split top level dielectric material into two layers bottom layer= IC thickness, top layer = top dielectric thickness – IC thickness

2. Map a dielectric VIA based on the IC substrate material in this case, dielectric VIA is GaAs material

3. Nest IC top metal in the package process Options Technology Nested technology tab

4. Map IC top metal in the layer above the dielectic VIA

5. Add bondwire (recommend using Jedec Bond)

6. Do a 3D FEM simulation of all or part of the package

FR4 Based 4L Laminate

Step 1

Step 2

Step 3

Step 4

Step 5 GaAs

Laminate

SMT “Jbond”

A good starting point is to just

consider the wires by themselves

Step 6

4


19

Simulate the PA at the Product Level

Connect Backside Grounds to Laminate, Re-optimize…

4


20

Put it all together… Add regulator loss

Add loss for stability

(more on this later…)

Optimize across frequency…

4

Maintain Flexible EM Space

Good Balance of Viability and Flexibility


21

HBT, Laminate Based Technology Mix

• Pros:

– Control scheme is simple

– Components provide tunablility,

– Laminate is flexible and high Q

• Cons

– Regulator loses PAE, makes for a larger

control IC

– Components limit size and might cost more

– We don’t make complete use all the layers in

the laminate


22

Agenda









23

TECHNOLOGY MIX #2


24

Understand the Devices and Models

• Maximum Device Voltage vs. High Frequency Performance – Higher Voltage devices (3.3V, 5.0V) realized by increasing gate oxide

thickness (and length)

– fT is inversely proportional to gate length

• Standard CMOS model BSIM, with additional extraction for

“RF Model”

• Process: Tower TS018 process using ADS PDK

1


25

Bulk CMOS: Integration and Reliability

• Reliability Considerations - Drain Source Punchthrough - Hot Carrier Injection - Zener Breakdown / Gate Oxide Rupture - Maximum device operating temperature • From a PA design perspective, watt level powers in standard bulk CMOS can be challenging due to voltage limitations • Significant potential of enhancement to PA or reconfiguration of PA when control is tightly integrated (much in literature) (This advantage can be hard to see with a single PA chain)

1


26

Reliability Considerations at Multiple Levels

•Circuit Approaches to High Power + Reliability • Cascode configuration: Divides VDS across multiple devices

• Differential configuration: Divides the drive voltage swing in half

• Integration/Matching Approaches to Overcoming Limitations • Power Combining Transformer: Allows for impedance transformation AND power combination (parallel

primary to series secondary)

1

•Higher Power +

•Larger Voltage Swing per device -

•NMOS Devices only +

•Need to use Higher V devices -

•Lower Power -

•Smaller Voltage Swing +

•NMOS + PMOS -

•Can probably use Low V devices

+ (at least in part of the cascode)

Approach A Approach B

Implementations assuming discrete, off die transformer

Son, Park, Hong (See Ref) Lee, Park, Hong (See Ref)


27

Select the Device Sizes

CMOS Device: Larger size = Lower Ron, but higher Cin, Cout

Bottom Cascode: Large device Higher PAE, harder to match

Top Cascode: Large device is better for PAE, and lessens Vds across the device

(reliability), but can limit BW (typically kept to around 1-2x bottom device)

This plot shows the input

resistance and capacitance of

the CS device as the device size

is increased, for a CG/CS scale

factor of 1 and 2 (Actually 0.35

or 0.5*8u*128)

This plot shows the DC voltage

drop across the top device as

the CG/CS scale factor is

increased

1


28


29

2

Power Control Voltage

Design the RF Output Cell

Select Technology: IPD Based Transformer

Increase Ls

http://www.onsemi.com/ Basic Operation of Transformer

3

Pout(>33) = 29 dBm / section + 6 dB 4 pairs


30

Layout of the IPD Transformer

S

Pwindings

T

TP

Ip

Is

S

P

S

P

T

TN

V

V2

*1

)/(

)/(

S

Pwindings

T

S

Pwindings

S

P

S

P

P

S

PP

SST

P

S

T

T

N

PZ

T

TP

T

T

NI

I

V

V

IV

IVZ

Z

Z

Layout in ADS Series Secondary (output)

Ts=3

N=2

Pwindings is the number of primary windings

Ts, Tp are number of turns

N is the number of coupled edges in the secondary

(N=integer, 1 or 2)

Impedance Transformation Ratio Current and Voltage Ratios

Differentially Driven Primaries

Tp=1

Pw=4 Inputs

Output

Virtual GND

Based on excellent papers “Power Combining Transformer Techniques for Fully Integrated CMOS Power Amplifiers”

And “A Quasi Four Pair Class-E CMOS RF Power Amplifier with an Integrated Passive Device Transformer”

3

Traces consist of the top two metals combined, routing done on the lower layer

(Lee, Park, Hong, IEEE)


31

Evaluate Transformer using realistic sizes

Parameterize Size using Advanced Model Composer (Momentum Simulation)

Increase Size

Increase Parasitic L

P2

P1

Increase Size,

retune Cload

Output Impedance

Max Gain

Input Drive and Virtual Ground

Input Impedance

Key Small Signal Simulation Results

Key Large Signal Simulation Results

3


32

Optimize Transformer Impedance

Impedance

of 1000u

transformer

Add ~1.4 nH to TF input

dBZRs

RsLoss 62.0

752.

52.1log201log20

0

Parameterize using AMC

3

Evaluate impedances Synthesize Inductor in IPD Process


33

Combine PA Cell and Transformer 3

Power Control Mechanism

With Ideal Prematch Inductor

With IPD Based Prematch Inductor

Top Level Results

Power Cell (From Loadpull)

Parameterized Transformer Ideal 2:1 Transformer

or, to realize on test IC: Lead/Lag Balun

+ Shunt input matching inductor


34

Simulate the QFN Package

Start with

“drop

in” IPD

1000u

www.amkor.com (4x4 Standard QFN)

Keep top

pads, add

ports

CMOS

(rule of

thumb)

Map IC’s as simple

dielectric VIAs

4

Just bonds at first,

then entire package


35

Bondwire Block

IPD Chokes

IPD Output Series

Match Inductor

In addition to optimizing

for Pout, PAE @ 3.5V,

also optimize for max

Vds at 4.0 V (or max Vcc)

Optimize IPD Size

Optimize output L and C

Optimize Choke

Inductors

Optimize

prematch

inductors Optimize bias point,

Device size, Pin

Optimize

Class E Cap

4.0V

3.5V

4

Optimize at the Product Level


36

Experiment with Functional Blocks…

Confidentiality Label

June 13, 2013 37

ADS

Behavioral

Log Amp

Circuit Level Design

of Opamp in TS018

process

Monitor voltage

at ground bond

(α Pout)

Attenuate/Filter

Convert RF power

to DC current

Buffer (VtoI)

Error

Amp

gnd Control

Mirror

Power Control

Output

Coupled Input

Signal from TF

Analog Power

Control Voltage

ADS

VCCS

Top

Level

Integrated

Closed loop

power control

system…

4

Put it all together… 4

At max Vcc…

Added RC Feedback

to improve stability


38

CMOS, IPD Based Technology Mix

• Pros

– Compact

– All matching realized on IPD

– Integrated power control

– Flat bandwidth

• Cons

– Voltages close to reliability limits

– Too much PAE lost in prematch inductor

– Discrete tunability in TF


39

What kinds of things might be worth comparing?

GaAs PA CMOS PA

Noise in Adjacent Bands

Modulated Output Spectrum

(Envelope simulation)

Load Pull

GaAs PA CMOS PA

CMOS PA GaAs PA

Design Sensitivity (DOE – 2kmp)

GaAs PA

SMT Cap

Variation Pareto

CMOS PA

IPD Cap

Variation Pareto

50 ohm side

shunt C


40

Agenda









41

Common Themes

So, how do you choose the right technology mix?

• Iterative design approach where product level complexity is sequentially added before the designs are fully complete

– Key: Iterate quickly to find the right mix, then focus on in-depth design

• Key Capabilities Needed:

– Access to many different technologies and PDK’s

– EM tools (2.5D or 3D) which are integrated in the flow

– Ability to parameterize structures using EM and optimize physical layout together with device level

– Behavioral and system level modeling capability

WIN HBT PDK MuRata SMT FR4 4L Laminate Jedec Bonds Tower TS018 PDK ONsemi IPD Amkor QFN Pkg


42

Designing with stacked complexity

Product Interconnects,

Pin-out

Circuit Topology, Class, Bias, Control

Interface Matching, Filtering,


Device Process, Reliability, Modeling, Size

Utilize the

underlying

design

layers

GaAs PA: Initial Backside GND connect

showed substantial performance drop

Extract ground

inductance

(small signal)

Troubleshoot

problem

Gain Dropped due to degeneration

(Need to increase Pin, change load

and source match)

Make the

Adjustment

Not sure of

the cause

so not easy

to adjust…


Re-

optimize

Match

?

Solution

?


43

Applying this approach to Envelope Tracking

I.E. Recent GaAs/CMOS debate regarding the application of Envelope Tracking

• (ET can be applied to both core technologies and should be considered at the product level)

Apply similar design approach to a linear PA – Both PA topologies shown here can be adjusted for linear operation

Perform linear loadpull

Optimize Transformer Match

Pop up to the product level

Fine tune the load/bias

Add ports, make a symbol PAE curves using

CMOS PA -- Product

Level

“Applying ET to the CMOS PA” Modify to Linear Topology

add 2fo trap to input transformer to

improve distortion *(See references)

Drop into ADS ET Bench Applying an

LTE Signal

Contours of

•P1dB

•PAE 1dB

•SS Gain

•Gain Expansion

Analyze, Learn, Readjust

(control top device with battery)

Memory effects pose new design challenges

1


44

References


45

Questions?


46

Acknowledgement

Thanks to Dr. Peter Zampardi and Dr. Hongxiao Shao


47

Closing

Product

Circuit

Interface

Device


Interconnects,

Pin-out

Matching, Filtering,


Topology, Class, Bias, Control

Process, Reliability, Modeling, Size, Loading

[email protected]


48

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Documents

Presentation Title Arial 28pt Bold - Keysight · Overview Beyond GaAs vs. CMOS: Finding the right technology mix for a handset PA Module There has been much debate recently about