Presentation on ADS for Wireline and High Speed Analog Designliterature.cdn.keysight.com/litweb/pdf/5989-8988EN.pdf · 2008-11-05 · circuits • Time Domain (using High Frequency

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Presentation on ADS for Wireline and High Speed Analog Design

Tuesday, May 21, 2002Title of Presentation1 M h 2001

Page 1

Advanced Design Systemfor Wireline and High Speed Analog Design

21 May 2002Title of Presentation1 M h 2001

Page 2

•TRENDS AND CHALLENGES

•ADS VALUE

•ADS DESIGN FLOW SOLUTIONS

•PRODUCT OFFERINGS

•CONCLUSIONS


Page 3

The need for ADS in Wireline

“Most optical systems contain 80% electronics.”Waguih IshakTechnology directorAgilent Communications and Optics Networks Lab


Page 4

High-speed Lightwave Transmission

Modulator

Modulator Driver

ClockTransmitter10 Gbit/s

16 @ 622 MB/s 10 GB/s16:1 Mux

Fiber Optic Channel

Laser Driver

CMOS Data

Source

Photo Detector

Laser

TIA

Limiting Amp

Receiver

1:16 DMuxCPU

10 GB/s16 @ 622 MB/s

Re-timing circuit

Det

1310 - 1550 nm (long haul)850 nm (short haul, board level)

Optical Components (OC)Optical Transport Semiconductors (OTS)

Switching and Routing Semiconductors (SRS)


Page 5

TRENDS AND CHALLENGES

Laser

Modulator

Clock

16 @ 622 MB/s 10 GB/s16:1 Mux

Laser Driver

CMOS Data

Source

Photo Detector

TIA1:16

DMuxCPU10 GB/s16 @ 622 MB/s

Det

Power ControlEye QualityRZ Modulation for Long Haul

Sensitivity, Dynamic RangeSignal Detect AccuracyOptical-Electrical IntegrationJitter (VCO Phase Noise)

Multi-Rate Support (FEC)

Multi-Rate Support (FEC)Power DissipationBlock Diagram Integration

6-7Vpp drive level at high freqPower DissipationWaveform distortion / dispersionActive Device Model

FEC Coding Gain improves BER

Tunable Laser

Optical Signal SeparationDynamic range of modulatorElectrical / Optical interface

Fiber AttenuationChromatic Dispersion (CD)Polarization Mode DispersionOptical Non-linearities

High-SpeedIntegrationPower Dissipation

FEC = Forward Error Correction

BiCMOSGaAs HBTSiGe - infrastructureInP - instrumentation


Page 6


•ADS VALUE

•Applications

•Simulations



•CONCLUSIONS


Page 7

Benefits of ADS / IC-CAP for Wireline

Leading edge simulation technologiesTime Domain / Frequency Domain / EM / Optimization under one

environment• IC package analysis• Board analysis• Foundry partners for latest models• Design Flow - Cadence Dynamic Link• Active Device Model capability (IC-CAP)


Page 8

Application ExamplesReference design examples


Page 9

MUX 2:1

MUX 2:1

MUX 2:1

MUX 2:1

MUX 2:1

MUX 2:1

MUX 2:1

MUX 2:1

DataSelector

DataSelector

DataSelector

DataSelector

DataSelector

DataSelector

DataSelector Amplifier

Design Challenges:•Signal Timing•Jitter•Eye diagram•Good Impedance match

ADS can be used to design complete MUX/DEMUX

Multiplexer 16:1


Page 10

Design Challenges:•CPW•Bond Wire model•Optical Measured Data•Good Impedance match

ADS can be used to design electrical portions of the Laser Modulator

Laser Modulator


Page 11

Mod.Driver

OpticalModulator

LaserDriver

Laser

Design Challenge:• High Speed Signal and Large Output Signal Requirements• Short rise time and Fall time requirements for good eye Opening• Minimal Jitter ( Phase Noise)• Good impedance match• Wide Bandwidth design

ADS can be used to design complete MUX/DEMUX

Modulator Driver


Page 12

LimitingAmplifier

Limiting Amplifier is the main amplifier in OC-192 & OC768Limiting Amplifier is used to reshape NRZ dataDesign Challenges:

Ultra wide bandwidth with High gain Minimum Phase shift deviation to achieve small timing jitterOutput Power must be constant over a wide dynamic range

ADS can be used to design Limiting Amplifier for 10 GB/s and 40 GB/s system

Limiting Amplifier


Page 13

VariableAmplifier

Design Challenges:Linear channel flat response over very wide bandwidth Constant group delay throughout bandGood input and output return lossWide gain control dynamic rangeLow noise figure design

ADS can be used to design Variable Gain Amplifier

Amplifier with Gain Control


Page 14

Design Challenges:• High Gain over wide Bandwidth• High Speed with wide Dynamic Range• To achieve lowest possible noise while retaining Bandwidth performance• Good Input/Output Return Loss• Low Power Consumption• Effects of distributed models• Include measured S-Parameters from Network analysers or EM simulators• Include E/O measurements of laser, detector from Agilent Lightwave analysers.• Create and use a behavioral model from simulation or from Data Sheet• Create and use an Encoded Model of the TIA

Trans-Imp.Amplifier

ADS can be used to design Trans-Impedance Amplifier

Trans-Impedance Amplifier


Page 15

On chip signal distribution, Vias, Coplanar waveguide, Multilayerstructures, Spiral Inductors, Bond Wires BGA and other packages

Uses ADS Capability

OEIC Package Design


Page 16


•ADS VALUE

•Applications

•Simulations



•CONCLUSIONS


Page 17

High Frequency Spice with Convolution AnalysisIn standard Spice all the frequency-dependent components are approximated with

lumped element equivalents• High frequency effects such as dispersion and loss at higher frequencies

are not taken into account

• The Convolution engine in ADS High Frequency Spice models accurately all frequency-dependent components (microstrip, S-parameter blocks etc.)

• Impulse response for all distributed components is calculated, then • convolved with input signal to yield output

)()()( sHsXsY � � ��

t

dthtxty0

)()()( ��

Unique in ADS


Page 18

ADS Simulation of Transimpedance Amplifier (TIA) or Laser Driver

• Time Domain (using High Frequency Spice and Convolution Simulator)

• Jitter, Gain, Skew, delay, Eye diagram, Eye Closure

• Rise time, overshoot, ringing etc.• Effects of distributed models of on

chip transmission lines and Packages such as BGA


Page 19

ADS Simulation of Transimpedance Amplifier (TIA), or Laser Driver


• Differential circuits and LVDS• Include measured S-Parameters from

Network analysers or other sources such as EM simulators

• Include E/O measurements of laser, detector from Agilent Lightwave analysers.

• Use a behavioral model of TIA from simulation or from Data Sheet

• Create and use an Encoded Model of the TIA


Page 20

ADS Simulation of Oscillator and Clock Recovery circuits


• Jitter, Oscillator start up time, Waveform,

• Rise time, overshoot, ringing etc.• Effects of distributed models of on chip

transmission lines and Package such as BGA

• Include measured S-Parameters from Network analysers or other sources such as EM simulators

• Create and use an Encoded Model of the Oscillator


Page 21

ADS Simulation of Oscillator and Clock Recovery circuits• Frequency Domain (Linear and Non-Linear

Harmonic Balance, and Circuit Envelope Simulator)

• Loop gain and phase in Oscillator circuit, Oscillating frequency, level, waveform and spectrum. Ring Oscillators.

• Phase Noise VS frequency offset• Jitter Calculated from Phase Noise• PLL circuits , Lock time, Frequency vs Time• Effects of distributed models (transmission lines, vias

etc) of on chip transmission lines and Package such as BGA

• Include measured S-Parameters from Networkanalysers or other sources such as EM simulators

• Create and use a behavioral model of Oscillator from simulation or from Data Sheet

• Create and use an Encoded Model of the Oscillator


Page 22

� The circuit is described by deriving Kirchoff’s current law in the frequency domain at each node

� The system of nonlinear equations so obtained is solved using the Newton-Raphson method

� Since most nonlinear devices are described by time domain (Spice) models, the simulator has to transform (inverse FFT) the voltage spectrum into the time domain, evaluate the response of the device then transform it back to the frequency domain (FFT)

0�� VCjRV �

�

�

V

)....,( 21 kVVVV �

�

Harmonic Balance Operation


Page 23

FM Flicker noise 1/f3

FM white noise 1/f2

PM Flicker noise 1/f

Start

Pts/decade

Stop

PM White noise

HB Oscillator Analysis Phase Noise Simulation


Page 24

Transient-Assisted Harmonic BalanceHow it works:• Runs transient to generate an initial guess• Initial guess is transformed from time to frequency domain• Use the initial guess with harmonic balance

Applications:• Highly nonlinear analog/RF circuits• Digital circuits (i.e. dividers, phase detectors)

Available in ADS

Unique in ADS


Page 25

TAHB Example

• Divide by 8 chain of three flip-flops• CMOS, 76 MOSFETs• examine phase noise after division

• Run times, P3-500• transient: 96 sec• HB signal: 21 sec• HB noise: 122 sec for 4 phase noise

analyses


Page 26

ADS Simulation of IC and PC Board structures

• Distributed Models and EM simulation In Time or Frequency Domain.

• PC Board transmission lines and traces, multilayer vias and routing

• LVDS traces and signals• Creating lumped element equivalent models of

all of the above.MULTI-COUPLED LINES

COUPLED CORNERS

COUPLED CROSSOVER

TAPEREDLINES


Page 27

Agilent Ptolemy

• Based on the Ptolemy code from UC Berkeley

• Simulation environment that supports multiple domains

• ADS Ptolemy uses the Synchronous Dataflow (SDF) domain for Digital Signal Processing analysis

• We have added:• Timed Synchronous Dataflow (TSDF)

domain for co-simulation• Large library of behavioral and time-

domain models• I/O Interfaces

Unique in ADS


Page 28


•ADS VALUE



•CONCLUSIONS


Page 29

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-100

-80

-60

-40

-20

0

20

freq, GHz

dB(S

(1,2

))dB

(S(2

,1))

Electronic Design Tools ADS, IC-CAP

laser driver with transmission lines

time domain view of data and crosstalk

frequency domain view(S11, S22 etc.), Non-linear response

modelledinterconnect. LVDS

Simulation of Clock Phase noise and Jitter


Page 30

Linear

Harmonic BalanceKrylov Solver

Transient Assisted HB

Circuit Envelope

ConvolutionHigh Frequency SPICE

RF System Simulator

PtolemyPtolemy Fixed Point

Digital FilterE-Syn

Planar EM

HFSPICE

AC /S-Parameters

Convolution

NewHarmonic Balance

Advancing Capabilities

Dom

ain

Freq

uenc

yTi

me

Num

eric

PtolemyTimed

Synchronous Dataflow (TSDF)

Circuit Envelope

Ptolemy Synchronous

Dataflow

Momentum

Phys

ical

Model Composer

High Speed Interconnect

Library

A World Class Integrated Simulation Tools


Page 31

ADS Foundry Support

Clock

10 GB/s16:1 Mux

Laser Driver

TIA1:16

DMux10 GB/s

Re-timing circuit

Det

BiCMOSSiGe HBTGaAs HBT

SiGe - infrastructureInP - instrumentation

BiCMOSSiGe HBTGaAs HBT

SiGe - infrastructureInP - instrumentation

Optical Transport Semiconductors (OTS)

5AM, 5HP, 6HP & 7HP SiGe

SiGe

GaAs HBT

0.18um & 0.25um CMOS

0.18um & 0.25um CMOS

0.8u BYX SiGe

GaAs HBT

Maxim GST2 & MBIC-1

QBIC3 & QBIC4

HCMOS7 0.25um & HCMOS8 0.13umBICMOS 6M & SiGe 6G 0.35um

TQTRx


Page 32

ADS Design Flow with Cadence Dynamic Link

CadenceDynamic

LinkSimulations

Design Kit

Post Processing

ADS

schematic layout

DesignGuides

Design KitHarmonic Balance

Transient

Convolution

Ptolemy

Planar EM

Interconnect Models

DRC / LVS

Parasitic extraction


Page 33

IC-CAP Parameter Extraction Methodology for Accurate Device Models• Support extraction of industry standard and customized simulation models • Open environment customizable to each process• Characterize process variations with statistical modeling

Integrated Circuit Characterization and Analysis Program

Modeling System

ModelLibraries

MeasuredData

TestSetups

IC-CAP

ModelParameters

Circuit Design Device Design

Process Control

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

XXXXXXX


Page 34


•ADS VALUE



•CONCLUSIONS


Page 35

PRODUCT SOLUTIONSHIGH SPEED ANALOG DESIGNER PRODUCT BUNDLES

HSAD HSAD Pro HSAD PremierDesign Environment X X XData Display X X XLinear Simulator X X XHigh Frequency Spice X X XSpice Netlist Translator X X XPassive Circuit DesignGuide X X XConvolution Simulator X XMulti-Layer interonnect Models X XStatistical Design X XRF Passive Circuit Models X XLayout X XLayout Translators X XMomentum X XMomentum Visualization X XMomentum Optimization XHarmonic Balance XRF System Models XPtolemy XPtolemy Matrix Models XAnalog Model Development XE-Syn X


Page 36

Simulation Technology• Accurate devices and distributed transmission line models for 40 GB/s design.• Linear Simulators to evaluate small signal Performance.• Harmonic Balance Simulator for accurate output power characterization and Optimization.• Spice and Convolution time domain simulators for accurate time domain simulation for 10 GB/s and 40 GB/s designs.• EM simulation capability in integrated environment for package characterization and interconnect modeling.• Interconnect Model library.• Ptolemy Simulator and Matrix Models

Design Flow• Design kits support from many commercial foundry.• Powerful data processing capabilities for circuit performance characterization.• Integrated environment for system and circuit design .

E9008A - Agilent High Speed Analog Design


Page 37


•ADS VALUE



•CONCLUSIONS


Page 38

Model 10 & 40 Gb/s with ADS

• Trans-Impedance Amplifier• Distributed Travelling Wave Amplifier• Limiting Amplifier• Multiplexer/Demultiplexer Design• Laser Driver• Modulator Driver (large voltage swings)• Variable gain Amplifier• Variable Attenuators• Ring Oscillator (jitter)• Clock Recovery Circuit (jitter)• Error correction encoders & decoders• Interconnect & Package Design• Semiconductor Parameters

and More …..

Accurate and Efficient High Speed Analog Design


Page 39

ADS Simulation Capabilites for Optical Wireline SummaryFrequency and time domain simulators:

• Pick the right tool for the job at hand• Can do much more than Spice

Distributed models and EM simulation• Account for high frequency effects that can no longer be ignored

Do System, on board, and IC all in one tool• Combine everything for end to end simulation with all physical effects

Complete Simulation of Transmit and Receive sections• Eye Diagram/Eye Closure• Jitter Measurements/Transfer Functions

ADS Capabilities

Additional Slides


Page 41

Sum of DC currents must be zero

DC Analysis Operation

• Capacitors, inductors eliminated• Topology checked for circuits with no unique DC solution• Iteratively find solution such that sum of all DC currents into each

circuit node is zero• Uses Newton-Raphson convergence algorithm to find solution for

nonlinear devices (BJTs, FETs, diodes)


Page 42

AC/S-Parameter Analysis

• DC analysis is performed to find the bias point• Nonlinear devices linearized at the bias point

• Assumes signal does not perturb the bias• Components characterized by their small-signal [S] or [Y]• Finds solution such that sum of all AC currents into each circuit node is

zero (not iterative)• Computes [S] and [Y] of the overall circuit at external ports• Calculates response to small sinusoidal signals


Page 43

(1) 0)()(��

dttdvC

Rtvv(t)

Transient Analysis (SPICE) - Simple RC Circuit

• Kirchoff’s current equations are derived at each node in differential form

• The time derivatives are replaced with discrete-time approximations (integration)

• The solution in the case of a complex circuit will consist of a system of nonlinear equations which is solved using the Newton-Raphson method


Page 44

• Large signals at harmonics• Small signals on either side harmonics• large signals and non-linearities causes mixing• Noise from translates to IF• Noise from all components translates

to output

nf fLO IF�

LO 2LO0 3LOIF RF

HB Nonlinear Noise Analysis


Page 45

100 Hz 10 kHz 1 MHz

-80

-120

-160

-20 dB/dec

Phase Noise as Frequency Modulation

• All oscillators exhibit sensitivity of oscillation frequency to voltage (VCO)

• Noise acts to randomly modulate the oscillator frequency


Page 46

fosc 2fosc0 3fosc 100 Hz 10 kHz 1 MHz

-80

-120

-160

Phase Noise Mixing

• Noise mixes with oscillator harmonics


Page 47

TAHB example (2)

• Transceiver-on-chip: includes RF, analog and digital circuitry• Total # of Devices = 14,000+

• 13,000+ linear devices • including interconnect and substrate parasitics

• 1200+ non-linear devices• 400 BJT’s, 60 MOSFET’s, 800 diodes

• Single-tone analysis with 56 harmonics• 4.5 hours on an HP J210 workstation with 1GB of RAM


Page 48

Spice Vs Harmonic Balance:ADS has them BOTH• Standard Spice

• Solves KCL by Newton Raphson• Time Steps determine rise time

resolution• Error Residuals determine

Accuracy• Frequencies determined by Fourrier

transform-needs long sim. period• Standard Spice Models Used• Used for decades by Analog and

Digital designers• Can’t simulate non-linear noise

such as phase noise• ADS HFSPICE CAN SIMULATE

JITTER!

• Harmonic Balance• Solves KCL by Newton Raphson• # of Harmonics determine rise

time resolution• Error Residuals Determine

Accuracy• Frequencies solved for explicitly.• Standard Spice Models used• Used for decades by RF and

Microwave designer. • Excellent for non-linear noise and

phase noise.


Page 49

What ADS can Simulate in Transimpedance Amplifier (TIA) or Laser Driver• Frequency Domain (Linear and Non-Linear Harmonic Balance Simulator)

• Effects of distributed models (transmission lines, vias etc) of on chip transmission lines and Package such as BGA, Crosstalk, Bounce

• Include measured S-Parameters from Network analysers or other sources such as EM simulators

• Include E/O measurements of laser, detector from Agilent Lightwave analysers.

• Create and use a behavioral model of TIA from simulation or from Data Sheet• Create and use an Encoded Model of the TIA


Page 50

What ADS can Simulate in Mux/Demux and SerDes circuits


• Jitter, Rise time, overshoot, ringing etc.• Skew, delay• Effects of distributed models of on chip transmission lines and

Package such as BGA• Include measured S-Parameters from Network analysers or other

sources such as EM simulators• Create and use an Encoded Model of the circuit

• Create and use behavioral digital model using Ptolemy (instead of transistor level circuit)


Page 51

What ADS can Simulate in Mux/Demux and SerDes circuits

• Frequency Domain Using Harmonic balance (TAHB)• Additive Phase noise• Additive Jitter calculated from Phase noise


Page 52

What ADS can Simulate in Data Source, Encoding and Error Correction circuits• Ptolemy Data flow Simulator

• Develop and create algorithms

• Implement as high level functional circuits and gates

• Generate and output HDL• Use in end to end simulation

of physical layer by co-simulating with analog circuits


Page 53

What ADS can Simulate in IC and PC Board structures: EVAL, DUT, and Demo boards• Simulate IC on Board

• Isolate IC and Board effects• Correlate simulation with

measurements• On Evaluation Boards in R&D• On DUT boards in

Manufacturing Test• On customer DEMO boards

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Printed in USA, May 21, 2002 5989-8988EN

Documents

Presentation on ADS for Wireline and High Speed Analog Designliterature.cdn.keysight.com/litweb/pdf/5989-8988EN.pdf · 2008-11-05 · circuits • Time Domain (using High Frequency