PRELIMINARY INFORMATION – Nov 05, 2015 Elektronik Service/produkt... · 27 M2 HV_A_I Motor phase, half bridge 2 28 GL2 HV_A_O Low side gate driver output, half bridge 2 29 GH1 HV_A_O

BLDC-Motor Driver with Cold-Crank Capability E523.10 PRELIMINARY INFORMATION – Nov 05, 2015

Features• Voltage range 4.5 to 28V (42V peak) for start-stop

systems• Sleep mode current 20µA typically• QFN package -40°C ... 150°C junction (170°C peak)• Microcontroller supply 3.3V or 5V, up to 70mA,

>70mA with external boost transistor• Adjustable watchdog and reset generation• Smart wake-up via BUS interface or KL15• High side charge pump driver• Self-controlled dead time generation• Motor current measurement amplifier• Over current switch-off (dynamical change)• FET short circuit protections (dynamical change)• Configurable voltage monitoring• PWM interface, bidirectional with error feedback• AEC-Q100 Qualification

Applications• This IC is developed for automotive applications• BLDC (EC) motor control, multiple DC motor control• Fuel, hydraulic, oil and water pumps• Cooling fans, HVAC fans, positioning systems• Turbo charger adjustment• Block commutation

Brief Functional DescriptionThe IC is a system base chip for driving BLDC and DC motors in B6, full bridge or half bridge applica-tions.

The IC ensures a safe, autonomous start-up and wake-up. It is suitable for high temperature applica-tions. An integrated linear regulator supplies an external microcontroller. The supply output current can be "boosted" with an external transistor.

For controlling the motor, six power FET gate drivers with automated dead time generation are implemented.Measurement functions for motor current, battery voltage and temperature are implemented.

The IC has integrated programmable safety func-tions on motor over current, battery over and under voltage, over temperature and short circuits at all sixpower FETs.

Ordering InformationOrdering-No.: TempJunc Range Package

E52310A39B -40°C to 150°C QFN44L7

Typical Application

Figure 1: Typical Application

This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.

Elmos Semiconductor AG Data Sheet QM-No.: 25DS0131E.00


1 Package and Pinout

1.1 Pin Description

Table 1: Pin Description

No Name Type Description

1 PWMH3 D_I High side control signal, half bridge 3



4 TXD D_I Bus interface transmit signal

5 RXD D_O Bus interface receive signal

6 PWML3 D_I Low side control signal, half bridge 3



9 SCLK D_I SPI clock input

10 CSB D_I SPI select (low active)

11 SI D_I SPI data input

12 SO D_O SPI data output

13 VSEL D_IO VCC voltage selection, interrupt output

14 NRES D_O External microcontroller reset (open drain)

15 T D_I debug and test mode activation

16 VIN HV_A_I Analogue input voltage, emergency shut-off

17 BUS HV_A_IO Bus interface (PWM)

18 VBATS HV_A_I Motor bridge supply sense

19 S HV_A_I KL15 wake-up

20 VG HV_S Power FET gate driver supply voltage

21 PGND2 S Power ground

22 GNDSNS A_I Low side short circuit reference

23 GH3 HV_A_O High side gate driver output, half bridge 3

24 M3 HV_A_I Motor phase, half bridge 3

25 GL3 HV_A_O Low side gate driver output, half bridge 3







32 VCP S Bonded to pin 33 internallyCharge pump voltage

33 VCP S Bonded to pin 32 internallyCharge pump voltage

34 PGND1 S Power ground

35 CPO HV_D_O Charge pump driver

36 VBAT HV_S Main power supply (battery)

37 n. c.


Elmos Semiconductor AG Data Sheet QM-No.: 25DS0131E.002 / 54


No Name Type Description

38 VDD S Internal 3.3V voltage regulator

39 VCCP A_O VCC regulator driver output

40 VCC A_I Microcontroller - IC interface voltage and feedback for VCC regulator

41 IP A_I Positive input terminal of motor current measurement amplifier

42 IM A_I Negative input terminal of motor current measurement amplifier

43 IO A_O Output of motor current measurement amplifier

44 GND S Ground

Explanation of Types:A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage

ESD:More details according this topic are described in the "ESD" chapter.

Figure 2: IC pin clamping diagram




1.2 Package Reference

The device is assembled in a QFN44L7 package according to JEDEC standard MO-220 VKKD-3.

1.3 Package Pinout

Figure 3: QFN44L7 pin configuration, transparent top view, not to scale




2 Typical Application

Figure 4: Typical application

Note: Do not insert filter capacitors between battery and the positive terminal of shunt resistor.




Table 2: External components

No. Description Condition Symbol Min Typ Max Unit

1 VBAT capacitance1) CVBAT 33 47 - μF2 1) Ceramic CVBAT 80 100 - nF

3 Battery input capacitance, close to battery and ground PCB input1)

CVBAT,EMC - 10 - μF

4 Bridge supply storage capacitance2) CVBAT,storage - - mF

5 VG capacitance RESR Ω > 0.8 CVG 8 10 50 μF6 Ceramic CVG 80 100 120 nF

7 VCC capacitance3) RESR Ω > 0.8 CVCC 8 50 μF8 Ceramic CVCC 80 100 120 nF

9 VDD capacitance4) Ceramic CVDD 80 330 500 nF

10 VSEL pull resistance RVSEL - 5.6 - Ωk11 NRES pull-up resistance RNRES - 33 - Ωk12 Interrupt series resistance VSEL used as

interrupt outputRINT - 56 - Ωk

13 Power FET gate-source pull resistance RGS - 100 - Ωk14 Power FETs total gate charge fPWM = 20kHz,

@10VQFET - 100 150 nC

15 High side short circuit reference protection series resistance, comparator threshold is increased by ISC,HS RSC,HS

Case no reverse polarity protec-tion at power FET stage

RSC,HS 80 - - Ω

16 Low side short circuit reference protection and filter series resistance, comparator threshold is increased by ISC,LS RSC,LS

Case GNDSNS connected to positive shunt terminal

RSC,LS 80 100 - Ω

17 Current measurement amplifier resist-ances5)

RSH, RFP, RFN,RPP, RG

- - - -

18 T pull down resistance, short distance to ground

RT 0 - 1.2 Ωk

1) For ISO pulse and load dump >50V required2) Depending on application3) Depending on load transients4) No other components than buffer capacitors allowed5) Amplifier to be designed by customer

The external charge pumps have to be designed by the customer. The electrical parameters of the power FETs (total gate charge and threshold voltage) and the minimum operating battery voltage determine the topology of the charge pump.

Figure 5: Proposal of 1-stage charge pump






Table 3: External components proposal of charge pump


1 Charge pump storage capacitance CVCP - 2.2 - μF2 Pump capacitance CPUMP - 100 - nF




3 Block Diagram

Figure 8: Block Diagram




4 Operating Conditions

4.1 Absolute Maximum Ratings

• Operating the device at or beyond these limits may cause permanent damage.• All voltages are referred to ground (0V).• Currents flowing into the circuit have positive values.

Table 4: Absolute maximum ratings

No. Description Condition Symbol Min Max Unit

1 Storage temperature TS -40 150 °C

2 Junction temperature TJ -40 150 °C

3 Ambient temperature TA -40 150 °C

4 Junction temperature profile1) TJ < 110°C tT,J + 10002)

- h

5 TJ < 130°C tT,J + 30002)

- h

6 TJ < 150°C tT,J + 60002)

- h

7 TJ < 150°C tT,J + 10002)

- h

8 TJ < 150°C tT,J + 1202)

- h

9 IC total power dissipation2) Ptot - W

10 VBAT, VBATS, VCP(2), VG, S, BUS, M1-3, GH1-3, GL1-3, CPO voltage

VVBAT -0.3 40 V

11 t < 500ms VVBAT - 42 V

12 VCC voltage VVCC -0.3 5.5 V

13 VCCP voltage VVCCP -0.3 8 V

14 VCP voltage VVCP -0.3 50 V

15 t < 500ms VVCP -0.3 52 V

16 VDD voltage VVDD -0.3 3.6 V

17 TXD, RXD, PWMH1-3, PWML1-3, IP, IM, CSB, SCLK, SI, SO, VSEL, NRES, T voltage

VIO,VCC -0.3V VVCC +0.3V

-

18 RXD,SO, RESN, IO current IO,VCC -5 5 mA

19 GH1-3 voltage VGH1-3 - VVCP +0.3V

-

20 VGH1-3 VM1-3 -20V

VM1-3 +20V

-

21 GL1-3 voltage VGL1-3 - VVG +0.3V

-

22 M1-3 voltage VM1-3 -3V VVBATS

+ 3V-

23 GNDSNS voltage VGNDSNS -0.3 0.3 V

24 GH1-3, GL1-3 current t < 10µs IO,DRV -600 600 mA

25 IO voltage VIO,VDD -0.3V VVDD +0.3V

-

26 VIN voltage VVIN -0.3 40 V




No. Description Condition Symbol Min Max Unit

27 |IVIN| < 3mA (series resistance Ω>1k required)

VVIN -3 - V

28 Load capacity at pin SO CSO - 1 nF1) According to various automotive conform medium- and high-temperature profiles, refer to figure below2) To be calculated by the customer for the application: Ptot < (TJ,max - TA,max) / Rth,J-A. For calculation refer to table below.

Table 5: Power loss estimation

Block Symbol Calculation

VCC regulator PVCC

VG regulator PVG

Charge pump driver PCP

Internal Pint

Power FET gate driver PDRV

IC Ptot

Note: For power loss estimation use maximum operating voltage of VBAT.

4.2 Recommended Operating Conditions

• Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.• All voltages are referred to ground (0V).• Currents flowing into the circuit have positive values.• The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of elec-

trical contacts.)

Table 6: Recommended operating conditions


1 Junction temperature Continuous, pro-duction test at TA

= -40°C ... 125°C

TJ -40 - 150 °C

2 VBAT voltage1) VVBAT 6.2 13 28 V

3 1) VCC 3.3V only VVBAT 4.5 - - V

4 VCC regulator load current -IVCCP 0 - 70 mA

5 VCP voltage (referred to VBATS) VVCP,VBATS 6.5 - - V

6 TXD, PWMH1-3, PWML1-3, CSB, SCLK, SI, VSEL input level

VDI,VCC 0 - 0.2 VVCC

7 TXD, PWMH1-3, PWML1-3, CSB, SCLK, SI, VSEL input level

VDI,VCC 0.8 - 1 VVCC

8 RXD, SO, NRES output current IDO,VCC -1 - 1 mA

9 Number of simultaneously clocked half bridges (block commutation only)

nhb,clk - - 1 -

10 VBATS voltage VVBATS 7 13 28 V

11 VBATS voltage at cold crank2) VVBATS 4.5 - - V

12 GNDSNS voltage VGNDSNS -0.3 - 0.3 V





13 IP, IM voltage VA,I 0 - 1.5 V

14 Current measurement amplifier output range

VIO 0V - VVDD -

15 AMUX = 0 only:case VIO < Vth,RAIL-

DET or VIO > VVDD -Vth,RAILDET for more than tRAIL-

DET, AMUX = 0

VIO 400mV

- VVDD -400m

V

-

16 Motor current measurement amplification ACM 10 - 100 -

17 IO load capacitance CIO,load - - 100 pF

18 VIN voltage VVIN 0 - 3 V

19 T voltage VT -0.3 0.3 V

20 SCLK clock frequency fSCLK - - 4 MHz

21 SPI data setup time tspi,ds 62 - - ns

22 SPI data hold time tspi,dh 62 - - ns

23 SPI clock setup time tspi,cs 62 - - ns

24 SPI clock hold time tspi,ch 62 - - ns

25 SPI access gap tspi,gap 3 - - μs1) If a VCC boost transistor is used, the minimal VBAT voltage is increased by the individual base-emitter voltage of the external boost-transistor (VBE,boost,VCC).2) Depending on charge pump design, short circuit protection thresholds limited

Figure 9: VBAT recommended operating condition functional overview (not to scale)




5 Detailed Electrical Specification

5.1 Power Supply and Management

Table 7: Power supply electrical parameters


1 Current consumption in sleep mode TA < 50°C, VVBAT = VVBATS = VVCP = VBUS = 12V

(IVBAT + IVBATS +IVCP)SLEEP

- 20 50(tbd)

μA

2 Current consumption in run mode,power FET gate switching and microcon-troller current consumption not included

Modulated motor, fPWM = 25kHz

(IVBAT +IVBATS)ACT

- 5 8 mA

5.1.1 VCC Microcontroller Supply

Table 8: VCC Supply Electrical Parameters


1 VCC regulator output voltage 3.3V mode, charge pump enabled1)

VVSEL = 'L', -IVCC <70mA, VREGC-TRL[4] = 1

VVCC3 3.2 3.3 3.4 V

2 VCC regulator output voltage 5V mode, charge pump enabled1)

VVSEL = 'H', VVBAT > 6.2V, -IVCC < 70mA, VREGC-TRL[4] = 1

VVCC5 4.85 5 5.15 V

3 VCC internal current limitation VVCC = 0.5V IVCC,lim -180 -120 -80 mA1) No external boost transistor

5.1.2 VG Power FET Gate Driver Supply

Table 9: VG supply electrical parameters


1 VG regulator output voltage -IVG < 3mA VVG 9.4 10.2 11 V

2 VG current limitation VVG = 8V IVG,lim -80 -64 -50 mA

5.1.3 Charge Pump Driver

Table 10: Charge pump driver electrical parameters


1 CPO peak current Rising Ion,CP 65 105 145 mA

2 CPO peak current Falling Ioff,CP 65 95 145 mA

3 Charge pump frequency VREGCTRL[7:6]= 1VREGCTRL[5] =1

fCP - 125 - kHz

4 Charge pump switch-off threshold (referredto VBATS)

Rising VVCP,OV - VVBATSr 7.9 10.3 13.1 V

5 Falling VVCP,OV - VVBATSf 7.6 10 12.8 V

6 Charge pump switch-off detection time1) td,VCP,OV 1 2 3 μs1) Scan tested




5.1.4 Internal Supply

Table 11: Internal supply electrical parameters


1 Internal supply voltage VDD IVDD = 0A VVDD 3.0 3.3 3.6 V

2 Internal oscillator frequency fOSC 0.9 1 1.1 MHz

Table 12: Digital pins electrical parameters


1 VSEL, CSB, SCLK, SI, TXD, PWMH1-3, PWML1-3 input threshold

Rising Vth,i 0.22 - 0.79 VVCC

2 Falling Vth,i 0.21 - 0.78 VVCC

3 CSB, TXD pull-up current VVCC = 3.3V, Vi = 0V

IPU -75 -50 -25 μA

4 SCLK, SI, PWMH1-3, PWML1-3 pull-down current

VVCC = 3.3V, Vi = 3.3V

IPD 25 50 75 μA

5 VSEL pull-down current VVCC = 3.3V, 0.3V < Vi < 3.3V

IPD,VSEL 10 30 50 μA

6 VIN input threshold SECURCTRL[3] = 1, rising

Vth,VIN 0.21 - 0.78 VVDD

7 SECURCTRL[3] = 1, falling

Vth,VIN 0.22 - 0.79 VVDD

8 VIN pull-down resistance SECURCTRL[3] = 1

RPD,VIN - 125 - Ωk

9 SO, VSEL, RXD output voltage -Io < 1mA Vo,HIGH 0.82 - 1 VVCC

10 SO, VSEL, RXD, NRES output voltage Io < 1mA Vo,LOW 0 - 0.18 VVCC

11 T input threshold Falling Vth,T 0.85 1.2 1.6 V

12 T pull-down current 0.85V < VT < 3.3V

IT,pd 10 30 50 μA

5.1.5 Reset

Table 13: Reset electrical parameter


1 VCC reset threshold 3.3V mode Rising VVCC3,UV 2.7 2.85 3.0 V

2 Falling VVCC3,UV 2.6 2.75 2.9 V

3 VCC reset threshold 5V mode Rising VVCC5,UV 4.15 4.35 4.5 V

4 Falling VVCC5,UV 4.05 4.25 4.4 V

5 VCC reset detection time1) td,VCC,UV 2 6 10 μs1) Scan tested

5.1.6 Chip Control

Table 14: Wake-up and shut-down electrical parameters


1 S (KL15) threshold voltage VVBAT > 7V Vth,S 1.7 3.4 5 V





2 VBAT wake-up threshold during power-up (BUS = 'H' or S = 'H')

VS = VVBAT - 0.4V VVBAT,wake,startup - 4.8 6 V

3 S (KL15) filter delay1) VVBAT > 7V td,S 2 5 50 μs4 Over all wake-up delay until controller is

released (VG not switched on yet)*)

Typical capacit-ies

tWU,up - 0.25 10 ms

5 S pull down current VS > 1.7V Ipd,S 2 10 20 μA6 Charge pump discharging time, (VBAT

over voltage or sleep mode )1)

td,sleep 3 - 4 ms

*) Not tested in production1) Scan-tested

5.2 Power FET Gate Driver

Table 15: Power FET gate driver electrical parameters


1 Minimum gate charge current of high side and low side drivers

VVCP - VGH1-3 > 5.5V (high side), VVG - VGL1-3 > 5.5V (low side), SRxSON = 0, rising edge

IG,on,min 2.2 3.9 6 mA

2 Minimum gate discharge current of high side and low side drivers

VGx1-3 > 5.5V, SRxSOFF = 0, falling edge

IG,off,min 6.6 10.0 15.0 mA

3 Maximum gate charge current of high side and low side drivers

VVCP - VGH1-3 > 5.5V (high side), VVG - VGL1-3 > 5.5V (low side), SRxSON = 63, rising edge

IG,on,max 180 250 320 mA

4 Maximum gate discharge current of high side and low side drivers

VGL1-3 = 4.8V, VGH1-3 = 5.5V, SRxSOFF = 63, falling edge, VVBAT > 5.5V

IG,off,max 450 600 775 mA

5 Maximum gate discharge current of high side and low side drivers at low VBAT

VGx1-3 = 3.5V, SRxSOFF = 63, falling edge,4.5V < VBAT < 5.5V

IG,off,max,4V5 380 500 750 mA

6 On-resistance of high side and low side drivers

Switched on ron,G - 8 20 Ω

7 On-resistance of high side and low side drivers

Switched off roff,G - 4 10 Ω

8 Emergency shut-off debounce time1) tVIN,deb - 50 - μs1) Scan-tested




Table 16: Power FET gate driver comparators electrical parameters


1 HS power FET on-state threshold (VVCP - VGH1-3)

VVGSON,HS 0.8 1.3 1.8 V

2 HS power FET off-state threshold (VGH1-3 - VM1-3)

VVGSOFF,HS 0.8 1.3 1.8 V

3 LS power FET on-state threshold (VVG - VGL1-3)

VVGSON,LS 0.8 1.3 1.9 V

4 LS power FET off-state threshold (VGL1-3 - VPGND1-2)

VVGSOFF,LS 0.8 1.3 1.8 V

5.2.1 Short Circuit Protection

Table 17: Power FET short circuit protection electrical parameters


1 Minimum high side and low side short cir-cuit threshold

SCTH_xS = 3, VGNDSNS = 0V

Vth,SC,xS,3 47.5 78 108.5 mV

2 Maximum high side and low side short cir-cuit threshold1)

SCTH_xS = 80, VGNDSNS = 0V

Vth,SC,xS,80 1.87 2.07 2.27 V

3 Short circuit detection filter time2) td,SC - 5 - μs1) VVBAT > 5V, VVBATS > 5V2) Scan-tested

5.3 Measurement Functions

5.3.1 Motor Current Measurement Amplifier

Table 18: Measurement amplifier electrical parameters


1 Input offset AMUX = 0 or 8, 0V < VIP < 1.5V, tested at VIP = 300mV and VIP =1.5V

Voffset,in -1 0 1 mV

2 0 < AMUX < 8, tested at VIP = 300mV and VIP =1.5V

Voffset,in -10 0 10 mV

3 Input leakage current 0V < VIP < 0.3V, 0V < VIP < 0.3V, TEMPj < 85°C, tested at 25°C

Ileak,in -1 0 1 μA

4 Amplifier output resistance to rails (open loop)

AMUX = 0 or 8, |IIO| = 1mA

rIO - 100 180 Ω

5 Amplifier settling time*)

A = 20, RG= Ω18k , VIO =

300mV ... 2.7V

tAMP - 300 500 ns

6 Amplifier output rail detection comparator threshold

To GND, AMUX = 0

Vth,RAILDET,GND 0 50 100 mV





7 To VDD, AMUX = 0

Vth,RAILDET,VDD 0 100 200 mV

8 Amplifier output rail detection time-out1) AMUX = 0 tRAILDET - 100 - µs

9 Amplifier output rail shift To GND and VDD, AMUX = 0,FORCE_CALIB = 1

VFORCE_CALIB 0 - 420 mV


5.3.2 Analogue Signal Measurement

Table 19: Analogue signal measurement electrical parameters


1 VBAT measurement divisor RDVBAT 11.5 12 12.5 -

2 VG measurement divisor RDVG 4.5 5 5.5 -

3 VIN measurement tolerance 0.3V < VVIN < 2V VERR,VIN -10 0 10 mV

4 Temperature measurement tolerance*) TJ > 125°C Terr,HT -11 0 11 K*) Not tested in production

5.4 Monitoring Functions

Table 20: VBAT over voltage electrical parameters


1 VBAT over voltage threshold Rising VVBAT,OV,on 29 30 31 V

2 Falling VVBAT,OV,off 28 29 30 V

3 VBAT over voltage detection time1) td,VBAT,OV 50 70 100 μs1) Scan-tested

Table 21: VG over and under voltage electrical parameters


1 VG over voltage threshold Rising VVG,OV 13 14 15 V

2 Falling VVG,OV 12 13 14 V

3 VG under voltage threshold for VVBAT > 7V SAFECTRL[5] = 0, rising

VVG,UV 6.0 6.4 6.8 V

4 SAFECTRL[5] = 0, falling

VVG,UV 5.8 6.2 6.6 V

5 VG under voltage threshold for VVBAT > 6V SAFECTRL[5] = 1, risingSAFEC-TRL[5] = 1

VVG,UV,6V 5.0 5.4 5.8 V

6 SAFECTRL[5] = 1, falling

VVG,UV,6V 4.8 5.2 5.6 V

7 VG over and under voltage detection time1) td,VG 50 70 100 μs1) Scan-tested




Table 22: Over temperature electrical parameters


1 Over temperature threshold1) Rising Totemp,on 170 185 200 °C

2 1) Falling Totemp,off 150 170 190 °C

3 Over temperature detection time2) td,otemp 50 70 100 μs1) Production test is based on calculation2) Scan-tested

5.4.1 Motor Over Current

Table 23: Motor over current electrical parameters


1 Motor over current comparator offset 1V < VIO < 2.7V Voffset,IO -20 0 20 mV

2 Motor over current reference IOCOMPTHR = 0

VDAC,0 - 0 - VVDD

3 DAC output voltage IOCOMPTHR = 8

VDAC,8 0 8/64 - VVDD


VDAC,32 0.45 0.5 0.55 VVDD


VDAC,55 - 55/64 1 VVDD


VDAC,63 - 63/64 - VVDD

7 Motor over current accuracy after calibra-tion by microcontroller with external ADC1)

F32 -3 0 3 %/VVDD

8 Motor over current detection time2) ta,OC 5 13 20 μs1) Calibration done at IOCOMPTHR = 8 and IOCOMPTHR = 55, measured at IOCOMPTHR = 322) Scan-tested

5.4.2 Watchdog

Table 24: Watchdog electrical parameters


1 Watchdog first open window time1) WDT,FOW 230 256 282 ms

2 Watchdog closed window time1) WDCTRL[7] = 1 WDT,CW 5,4 8 8.8 ms

3 Watchdog open window time1) WDCTRL[5:4] = 3

WDT,OW 115 128 143 ms

4 1) WDCTRL[5:4] = 2

WDT,OW 57 64 73 ms

5 1) WDCTRL[5:4] = 1

WDT,OW 28 32 38 ms

6 1) WDCTRL[5:4] = 0

WDT,OW 14 16 20 ms

7 Watchdog reset active time1) WDT,RES 200 400 1000 μs1) Scan-tested




5.5 Communication Interfaces

5.5.1 Bus Interface (PWM)

Table 25: BUS electrical parameters


1 BUS dominant output voltage TXD = 'L', RPWM =Ω1.5k to VBAT

VBUS,DOM - 0.7 1.2 V

2 BUS receiver dominant threshold VBUS,THDOM 0.4 - 0.6 VVBAT

3 BUS receiver recessive threshold VBUS,THREC 0.4 - 0.6 VVBAT

4 BUS receiver hysteresis VPWM,THREC- VPWM,THDOM

VBUS,HYS 0.02 0.05 0.175 VVBAT

5 BUS output current limitation VBUS > 2.5V IBUS,LIMIT 20 - 300 mA

6 BUS pull up resistance RBUS,SLAVE - 50 - Ωk7 BUS leakage current Transmitter

passive, VBUS >= VVBAT

IBUS,BUSREC - - 100 μA

8 BUS leakage current, supply disconnected VVBAT = 0V, 0V < VBUS < 28V

IBUS - - 200 μA

9 BUS receive propagation delay tBUS,PDR - - 8 μs10 BUS receiver debounce time*) tBUS,DB 0.3 - 6 μs11 BUS wake-up debounce time1) tBUS,WU 70 - 150 μs





6 Functional Description

6.1 Power Supply and Management

The power supply contains:• VCC linear voltage regulator for external microcontroller supply (3.3V or 5V, 70mA)• VG linear voltage regulator for power FET switching (10V)• Driver for external charge pump (VVBAT + 10V)• Power-on reset and microcontroller reset generation• Power-up, sleep mode and wake-up sequencing

Figure 10: Power supply block diagram

Table 26: Register VREGCTRL (0x07) Supply control

MSB LSB

Content CP_CLK_DIV[1:0] CP_TD_EN

CP_EN VCC_SON VSEL VGON VCCON

Reset value 1 0 1 0 0 1 1

Internal access R R R R R R R

External access R/W R/W R/W R/W R/W R/W R/W

Bit Description CP_CLK_DIV[1:0] : To be set to 1, charge pump frequency selection (0: 250kHz, 1: 125kHz, 2: 63kHz, 3: 32kHz)CP_TD_EN : To be set to 1, enable internal charge pump driver dead time (500ns)CP_EN : Enable charge pump driverVCC_SON : 1: VCC is connected to VDD in sleep mode internally, if VSEL = 'L'0: VCC is off in sleep modeVSEL : Confirmation of VSEL level, 1: µC supply VCC is 5V, 0: µC supply VCC is 3.3VVGON : Enable VG supplyVCCON : Enable VCC supply

6.1.1 VCC Microcontroller Supply

The VCC regulator is a linear NMOS regulator with current limitation. The level at VSEL pin sets the microcontrollersupply voltage to 3.3V or 5V during power-up and initial configuration. The voltage selection has to be confirmed bysetting VSEL bit in VREGCTRL register accordingly.




Figure 11: VCC regulator block diagram, case microcontroller supply is 3.3V, VREGCTRL[2] to be set to 0

Figure 12: VCC regulator block diagram, case microcontroller supply is 5V, VREGCTRL[2] to be set to 1

To increase the available output current or to reduce power dissipation within the IC to allow higher ambient tem-peratures, an external NPN bipolar boost transistor may be inserted.

Figure 13: VCC block diagram, case external VCC boost transistor

Security warning: If using an external boost transistor an external current limitation must be inserted.




Figure 14: Proposal of short circuit protection at microcontroller supply, when using an external boost transistor

Note: The stability of the implemented circuitry has to be ensured by the customer.

In sleep mode, the VCC regulator is switched off. If setting VCC_SON bit in VREGCTRL register, VCC pin is con-nected to the internal 3.3V supply VDD (VCC in 3.3V mode only). Then the output current is limited to 300µA. An overload leads to IC and microcontroller reset and restart.

Note: If VCC is supplied in sleep mode, all input pins should have pull resistances externally to avoid increased current consumption.

6.1.2 VG Power FET Gate Driver Supply

The VG regulator is used to supply the low side gate drivers. It is a linear low drop PMOS regulator with current lim-itation.

Figure 15: VG regulator block diagram

The chip internal divided VG voltage can be switched to pin IO by setting AMUX register via SPI.

6.1.3 Charge Pump Driver

The VBAT level clock signals at CPO pin drives the PCB charge pump, which is used for high side power FET gatedriving and high side reverse polarity protection.

If the VCP voltage is higher than VCP,OV, VBAT over voltage or sleep mode, the charge pumpe driver CPO is switched to ground.

In case of VBAT over voltage (load dump) or sleep mode, the charge pump voltage VCP is discharged against ground with (1 ... 3) 31mA (IG,on @SRHSOFF=1) for td,sleep.




Figure 16: Charge pump driver block diagram

6.1.4 Internal Supply

A linear 3.3V voltage regulator with current limitation supplies the internal digital and analogue components of the IC. External loads at VDD pin are not allowed.

6.1.5 Reset

The internal supply VDD and the microcontroller supply VCC are monitored by the IC. After power-up or in case of low voltage at VCC or VDD, the IC is reset and the signal at NRES pin for the external microcontroller is set to L. The reset is set to H, if VDD and VCC is powered up successfully.

NRES pin is an open drain output.

Note: The VCC regulator is switched off, when NRES is 'L'.

6.1.6 Chip Control

The IC is clocked by an integrated oscillator with fOSC frequency.

Figure 17: IC states diagram

Table 27: IC states description

Block POR (Deep-) Sleep Power-up Initial configura-tion

Run

Internal supply on on on on on




Block POR (Deep-) Sleep Power-up Initial configura-tion

Run

Oscillator off off on on on

VCC supply off off on on on 2)

VG supply off off off off on 2)

Charge pump off off off on on 2)

Power FET gate driver

disabled 1) disabled 1) disabled 1) disabled 1) enabled

Monitoring off off on on on

Measurement off off off off on

BUS interface disabled disabled disabled enabled enabled1) High side and low side power FETs switched off2) Depending on configuration

6.1.6.1 Power-upAfter applying battery voltage, the IC ensures a save power-up of microcontroller and B6 bridge. All high side and low side driver outputs are off (clamped to ground or to motor phase) to prevent the external B6 bridge from cross current.

Sleep mode activation after power-up is level sensitive to S pin. If S pin is low, the IC enters sleep mode. If S pin is 'H', the IC is in active mode.

Figure 18: Power up timing diagram, typical scenario

6.1.6.2 Shut-down and Sleep ModeSleep mode (deep-sleep mode) is entered via SPI command written to SLEEPCTRL register. In sleep mode, all registers are cleared except the IRQSTAT1 and IRQSTAT2 interrupt status registers. All regulators and monitoring are off except VDD and power-on reset (POR) generation.




Table 28: Register SLEEPCTRL (0x03) Sleep mode control

MSB LSB

Content - - - - - - - SLEEP

Reset value 0 0 0 0 0 0 0 0

Internal access R R R R R R R R/W

External access R R R R R R R W

Bit Description SLEEP : Enter sleep mode

Figure 19: Shut-down timing diagram

6.1.6.3 Wake-upWake-up from sleep mode can be done by two independent wake-up sources:• BUS pin: A falling edge at BUS pin followed by a dominant bus level maintained for a time period tBUS,WU res-

ults in a remote wake up request. If BUSWAKEEDGE bit in CHIPCTRL register is 0, the IC wakes up immedi-ately. Else the IC wakes up at the next rising edge at BUS pin.

• S pin: A rising edge or high level at S pin wakes up the IC. The sensitivity can be configured by SSENS bit in CHIPCTRL register.

Warning: Wake-up from sleep mode via S pin with SSENS = 0 requires a rising edge at S pin after writing the SPI sleep command plus td,sleep. In several applications it cannot be ensured under all circumstances. Then wake-up events may not be recognized and the system remains in sleep mode (dead lock). To avoid this situation, SSENS bit in CHIPCTRL register has to be set to 1.




Table 29: Register CHIPCTRL (0x02) Chip control

MSB LSB

Content - - - - - SSENS BUSWA-KEEDGE

BUSWA-KEEN

Reset value 0 0 0 0 0 0 1 1

Internal access R R R R R R R R

External access R R R R R R/W R/W R/W

Bit Description SSENS : 1: Wake up at S is level sensitive (high level leads to wake up), 0: Wake up at S is edge sensitive (rising edge leads to wake up)BUSWAKEEDGE : 1: BUS wake up at rising edge, 0: BUS wake up at falling edgeBUSWAKEEN : BUS wake up enable

Table 30: BUS wake-up typical scenarios

Goto sleep with recessive BUS Goto sleep with dominant BUS

CHIPCTRL[1] = 1 (wake-up at rising edge)

CHIPCTRL[1] = 0 (wake-up at falling edge)

Table 31: S wake-up typical scenarios

Goto sleep with 'L' level S Goto sleep with 'H' level S

CHIPCTRL[2] = 1 (level sensitive)




Goto sleep with 'L' level S Goto sleep with 'H' level S

CHIPCTRL[2] = 0 (edge sensitive)

6.1.7 Board Level Protection

VBAT (VBATS), S and GND must be protected against reverse polarity and ISO pulses on PCB level. At VBAT (VBATS) filtering is necessary to prevent the IC from malfunction and destruction caused by EME and EMI.

6.2 Initial Configuration and Security

Some registers of the IC are only writeable within the initial configuration state (refer to restricted register table).

After power-up or wake-up an initial IC configuration via SPI needs to be done. The initial configuration ends with setting ESECURE bit in SECURCTRL register. Once ESECURE bit is set, any writing of restricted registers is ignored.The ESECURE bit can only be set, if all other bits in SECURCTRL register are left unchanged. So the register has to be written twice, if special IC features want to be selected.

Example 1: SECURCTRL = 0x01, only 1 SPI access to the register necessary (no special features selected)

Example 2: SECURCTRL = 0x18 (1st SPI access), SECURCTRL = 0x19 (2nd SPI access), analogue signal multi-plexing and emergency shut-off selected

Reset conditions of ESECURE bit are:• Watchdog event (register watchdog or CLK watchdog)• Under voltage at VDD or VCC (at low battery voltage or short circuit)• Sleep state

If EMERGENCY bit in SECURCTRL register is set, VIN pin is used as digital input to enable / disable the power FET gate driver. If VIN pin is 'L', the power FET gate driver outputs are switched off.




Figure 20: IC states diagram, case VIN used for emergency shut-off

Note: To reset the IC after finishing the initial configuration, just write a false watchdog trigger command to the IC.

Note: It is recommended to check the configuration every few milliseconds. In case of bit failure detection, the registers must be rewritten immediately. Therefore it is necessary to force an IC reset (e. g. a false watchdog trig-ger), since register writing is blocked by ESECURE bit in SECURCTRL register in run and fail save mode.

Note: In final application, the use of a fuse is recommended to prevent the system from damage caused by acci-dental bit changes in the IC or aging of PCB elements, e. g. power FETs.

Table 32: Register SECURCTRL (0x04) Security configuration

MSB LSB

Content - ESAFEC-TRL

EDMUX EACMUX EMER-GENCY

- - ESECURE

Reset value 0 0 0 0 0 0 0 0


External access R R R/W R/W R/W R R R/W

Bit Description ESAFECTRL : Enable write access to SAFECTRL register in run modeEDMUX : Enable write access to DMUX register in run modeEACMUX : Enable write access to AMUX and CMUX registers in run modeEMERGENCY : Enable emergency shut-off functionality of power FET gate driver at VIN pinESECURE : Disables write access to all restricted registers (including ESECURE bit itself)

6.3 Power FET Gate Driver

The power FET gate driver contains 3 independent half bridge gate drivers with short circuit protection. Each half bridge consists of a high side and a low side driver controlled by PWMH1-3 and PWML1-3 input pins.




Low side supply is VG regulator output voltage, high side supply is VCP charge pump voltage.

The gates are charged and discharged with current sources. The current value can be adjusted via SPI for on- and off-switching and high side and low side separately in SRHS and SRLS registers during run mode:

If the power FET charging / discharging is done, the driver switches to low impedance automatically via VGSON,xSand VGSOFF,xS comparators.

Figure 21: Power FET gate driver block diagram




Figure 22: Power FET gate driver transfer characteristic timing diagram

Emergency shut-off functionality: If EMERGENCY bit in SECURCTRL register is set and VIN pin is L, the power FET gate driver outputs are switched off.

Table 33: Power FET gate driver registers

Register Name Address Description

SRHSON 0x24 High side gate on-current selection

SRLSON 0x25 Low side gate on-current selection

SRHSOFF 0x26 High side gate off-current selection

SRLSOFF 0x27 Low side gate off-current selection

Table 34: Register SRHSON (0x24) High side gate on-current selection

MSB LSB

Content - - SRHSON[5:0]

Reset value 0 0 0

Internal access R R R/W

External access R R R/W

Bit Description SRHSON[5:0] : On-switching gate current value




Table 35: Register SRLSON (0x25) Low side gate on-current selection

MSB LSB

Content - - SRLSON[5:0]

Reset value 0 0 0



Bit Description SRLSON[5:0] : On-switching gate current value

Table 36: Register SRHSOFF (0x26) High side gate off-current selection

MSB LSB

Content - - SRHSOFF[5:0]

Reset value 0 0 0



Bit Description SRHSOFF[5:0] : Off-switching gate current value

Table 37: Register SRLSOFF (0x27) Low side gate off-current selection

MSB LSB

Content - - SRLSOFF[5:0]

Reset value 0 0 0



Bit Description SRLSOFF[5:0] : Off-switching gate current value

6.3.1 Gate Control Input Modes

PWMH1-3 and PWML1-3 input pins can be used in 3 or 6 PWM input mode.

Table 38: PWMH1-3 and PWML1-3 input configuration

Mode Description Depiction Depiction

6 PWM input PWMH input pin controls the high side driver, PWML controls the low side driver independently.

3 PWM input PWMH input pin controls the high side driver, and the low side driver inversely. PWML input pin enables the PWMH driver control. PWML = 'L' switches the motor phase to high-impedance (both high side and low side FETs off), disregarding the level at PWMH.




Table 39: Register BRIDGEMODE (0x20) Bridge mode configuration

MSB LSB

Content - - - - - BM3 BM2 BM1

Reset value 0 0 0 0 0 0 0 0


External access R R R R R R/W R/W R/W

Bit Description BM3 : 1: 3 PWM input mode, 0: 6 PWM input mode motor phase 3BM2 : 1: 3 PWM input mode, 0: 6 PWM input mode motor phase 2BM1 : 1: 3 PWM input mode, 0: 6 PWM input mode motor phase 1

6.3.2 Short Circuit Protection

The drain source voltage of the external low side and high side power FETs in on-state are monitored by the IC. If the motor phase voltage M exceeds a programmable threshold, the gate driver switches the power FETs off imme-diately. Reference for the high side FETs is VBATS sense voltage, for the low side FETs ground.

Figure 23: Short circuit protection block diagram

The thresholds of high side and low side power FETs are programmable in SCTH_HS and SCTH_LS registers. The calculation of the threshold values is given in the following table.

Table 40: Short circuit value calculation

Side Mean value (referred to VGNDSNS) Tolerance (+/-) Minimum BatteryVoltage

High side




Side Mean value (referred to VGNDSNS) Tolerance (+/-) Minimum BatteryVoltage

Low side -

Warning: The short circuit threshold must be set carefully corresponding to power FET parameters and short cir-cuit impedance. If the threshold is chosen too high, the short circuit protection functionality is not available.

Table 41: Short circuit protection registers


SROFFSC 0x23 Low and high side gate off-current selection in case of drain-source short circuit.

SCTH_HS 0x28 High side short circuit threshold selection

SCTH_LS 0x29 Low side short circuit threshold selection

Table 42: Register SROFFSC (0x23) Low and high side gate off-current selection in case of drain-source short cir-cuit.

MSB LSB

Content SROFFSC[5:0]

Reset value 0 0 111111

Internal access R/W R/W R/W


Bit Description SROFFSC[5:0] : Off-switching gate current value in case of short circuit

Table 43: Register SCTH_HS (0x28) High side short circuit threshold selection

MSB LSB

Content - D[6:0]

Reset value 0 0001111

Internal access R R

External access R R/W

Bit Description D[6:0] : Short circuit threshold value (3 ... 80)

Table 44: Register SCTH_LS (0x29) Low side short circuit threshold selection

MSB LSB

Content - D[6:0]

Reset value 0 0001111

Internal access R R

External access R R/W

Bit Description D[6:0] : Short circuit threshold value (3 ... 80)

6.3.2.1 Superior Short Circuit Failure ReactionA superior reaction to a short circuit failure can be configured in SCPCTRL register.




Table 45: Register SCPCTRL (0x0B) Short circuit protection control

MSB LSB

Content - - - SCALL - - SCFCT[1:0]

Reset value 0 0 0 0 0 0 00


External access R R R R/W R R R/W

Bit Description SCALL : 0: Switch off specific FET on short circuit1: Switch off all FETs on short circuitSCFCT[1:0] : See table Table 46

Table 46: Short circuit protection control

SCFCT Error reset condition Depiction

0 Re-try of power FET switching at every rising edge of the corres-pondent input control. Interrupt is thrown after first short circuit failure detection

1 Drivers remain off until interrupt is cleared by the microcontroller

2 One re-try of power FET switching allowed, after that all drivers remain off until interrupt is cleared by the microcontroller

3 Two re-tries of power FET switching allowed, after that all drivers remain off until interrupt is cleared by the microcontroller

1) INTN: low-active interrupt




6.4 Measurement Functions

Measurement of motor current and internal analogue signals is available in the IC.

6.4.1 Motor Current Measurement Amplifier

An integrated high speed operational amplifier with external elements measures the motor current via a low side shunt resistor. Offset and gain of the current measurement amplifier have to be adjusted by external resistors.

The amplifier output IO can be connected to an ADC input of the microcontroller. The maximum output voltage is limited by the internal 3.3V supply VDD.

Figure 24: Motor current measurement amplifier circuitry

The offset of the operational amplifier is calibrated internally by continuous autozero method. The autozero offset calibration can only be successful, if IO output voltage is settled within a valid operating range between the supply rails VDD or GND.

Table 47: Autozero offset calibration description

AMUX = 0 AMUX = 8

Behavioural description when overdriven (positive and neg-ative rail detection)

The autozero offset calibration is paused. If the amplifier remains in this situation formore than 200µs, the autozero offset cal-ibration is forced for about 240µs (force mode). During this period the IO output voltage is VFORCE_CALIB. Detection thresholdis Vth,RAILDET.

The autozero offset calibration is active.

Pulsed measurement charac-teristics example




AMUX = 0 AMUX = 8

Pulsed measurement failures (t < 200µs)

- Undefined offset (loss of calibration)

Static measurement charac-teristics example

Static measurement failures (t > 200µs)

Limitation of output range (VFORCE_CALIB) Undefined offset (loss of calibration)

Other failure possibilities Settling artefacts when entering force mode or when motor current jumps duringforce mode

-

External circuitry recommend-ations

- IO-VCC resistor (current measurement amplifier offset)

6.4.2 Analogue Signal Measurement

The IC is able to provide divided pin potentials and internal analogue signals to the microcontroller. The analogue signals can be switched to IO pin via AMUX register. The observable voltage range at IO pin is limited from 0V to VVDD.

Table 48: Register AMUX (0x17) Analogue signal measurement selection

MSB LSB

Content - - - S4 S[3:0]

Reset value 0 0 0 0 000

Internal access R R R R R

External access R R R R/W R/W

Bit Description S4 : Reserved, bit must be set to 0S[3:0] : Analogue signal selection see below for coding

Table 49: Analogue signal measurement code table

AMUX Analogue signal

0 Current amplifier mode (standard)

1 VVIN

2 VIP

3 VTEMP

4 VVBAT / 12

5 VVG / 5

6 Over current comparator threshold (IOCOMPTHR)

7 Low side power FET short circuit threshold (SCTH_LS)

8 Current amplifier mode (loss of offset autozero calibration when output is driven close to the sup-ply rails GND or VDD)




AMUX register write access is locked, if EACMUX bit in SECURCTRL register is 0.

Security warning: The switching of internal signals to IO pin disables the motor current measurement. The absence of motor over current protection is completely at own risk.

Note: This functionality is disabled by default. The activation is subject to the security rules described in section Ini-tial Configuration and Security (setting EACMUX bit in SECURCTRL register).

Example: A recommended scenario from over current measurement to apply an internal signal to the microcontrol-ler is:• Set EN_OC bit in IRQMSK1 to 0 (disable interrupt flag)• Set IOCOMPTHR register to maximum value (63) to prevent the IC from false over current failure detection• Set AMUX registerExample: A recommended scenario to return to over current measurement is:• Set AMUX register to 0• Set IOCOMPTHR register to proper value• Set EN_OC bit in IRQMSK1 to 1 (enable interrupt flag)

6.5 Monitoring Functions

The IC provides several failure monitoring and protection functions:• Battery over voltage at VBAT pin• VG power FET supply under voltage• VCC microcontroller supply under voltage• Motor over current• IC over temperature• Watchdog

Note: The VCP charge pump voltage is not monitored. After reset of failures or power-up of the IC, a low gate-source voltage at the high side power FETs may cause a short circuit failure.

Table 50: Monitoring functions

Function Failure condition Failure actions Reset condi-tion

Depiction

VBAT over voltage

VVBAT > VVBAT,OV, SAFECTRL[3] = 1

Switch all high side power FETs off, dis-charge VCP charge pump

VVBAT < VVBAT,OV





Depiction

VG over voltage

VVG > VVG,OV, SAFECTRL[2] = 1

Switch all power FETs off

VVG < VVG,OV

VG under voltage

VVG < VVG,UV, SAFECTRL[2] = 1


VVG > VVG,UV

VCC under voltage

VVCC < VVCC,UV Switch all power FETs off, reset of external microcontroller, reset of internal registers except IRQSTAT

VVCC > VVCC,UV, restart of the IC and external microcontroller

Motor over cur-rent

VIO > VDAC,OC, SAFECTRL[4] = 1


VIO < VDAC,OC,cleared interrupt





Depiction

Over temperat-ure with SAFECTRL[1] = 1

TJ > Totemp Switch all power FETs, VCC and VG regulator off, disable BUS, reset ofexternal microcontroller, reset of internal registersexcept IRQSTATx

TJ < Totemp,restart of the IC and external microcontroller

Over temperat-ure with SAFECTRL[1] = 0

TJ > Totemp Switch all power FETs off, disable BUS,

Safety warning: The microcontroller has to switch into low power mode immediately, else the IC might be dam-aged.

TJ < Totemp

Watchdog event

No watchdog triggeror false trigger, WDCTRL[1] = 1

Switch all power FETs off, reset of external microcontroller, reset of internal registers except IRQSTATx

Restart of the ICand external microcontroller

1) INTN: low-active interrupt

The SAFECTRL safety functions register configures the failure reactions of the IC.




Table 51: Register SAFECTRL (0x05) Safety functions configuration

MSB LSB

Content VBATOV_FR[1:0] VGUV6V SOC SVBATO SVG OTVC-COFF

OTSLEEPEN

Reset value 00 0 1 1 1 1 0


External access R/W R/W R/W R/W R/W R/W R/W

Bit Description VBATOV_FR[1:0] : Refer to following tableVGUV6V : VVG under voltage threshold select for VVBAT > 7V (0) or VVBAT > 6V (1)SOC : Safety function on over currentSVBATO : Safety function on VBAT over voltageSVG : Safety function on VG over or under voltageOTVCCOFF : Disable VCC supply on over temperature. This bit is redundant when OTSLEEP is1 (VCC is always off in sleep mode).OTSLEEPEN : IC shut down on over temperature

Table 52: VBAT over voltage failure reaction code table

SAFECTRL[7:6] VBAT over voltage failure reaction

0 All LS-FETs are switched on, all HS-FETs are switched off automatically

1 All FETs are switched off automatically

2 All HS-FETs are switched off automatically, switching of LS-FETs allowed

6.5.1 Motor Over Current

The motor current measurement amplifier output at IO pin is monitored by the IC. If the voltage exceeds a program-mable threshold, a motor over current is detected. The threshold value is calculated to:

Figure 25: Motor over current circuitry

If CMUX register is written accordingly, the motor over current functionality can be applied to other internal ana-logue signals.




Security warning: The deactivation of motor over current monitoring is completely at own risk. This is disabled by default. The activation is subject to the security rules described in section Initial Configuration and Security (setting EACMUX bit in SECURCTRL register).

Table 53: Motor over current registers


IOCOMPTHR 0x16 Motor over current threshold

CMUX 0x18 IO comparator input signal select

Table 54: Register IOCOMPTHR (0x16) Motor over current threshold

MSB LSB

Content - - D[5:0]

Reset value 0 0 000000

Internal access R R R


Bit Description D[5:0] : Motor over current threshold value

Table 55: Register CMUX (0x18) IO comparator input signal select

MSB LSB

Content - - - S4 S[3:0]



External access R R R R/W R/W

Bit Description S4 : Reserved, bit must be 0S[3:0] : Motor over current comparator configuration, see below for coding

Table 56: Motor over current comparator input signal code table

CMUX Analogue signal

0 Current amplifier mode (standard)

1 VVIN

2 VIP

3 VTEMP

4 VVBAT / 12

5 VVG / 5

6 Over current comparator threshold (IOCOMPTHR)

7 Low side power FET short circuit threshold (SCTH_LS)

Note: CMUX register write access is locked, if EACMUX bit in SECURCTRL register is 0.

6.5.2 Watchdog

The register watchdog can be configured in WDCTRL register within the first open window. It can be triggered by SPI access to WDTRIG register or a rising edge at PWML3 input pin.

Standard watchdog (WDUSECW = 0): The next trigger command has to be sent within WDT,OW.




Window watchdog (WDUSECW = 1): The next trigger command has to be sent after WDT,CW and before WDT,CW + WDT,OW.

Table 57: Watchdog registers


WDCTRL 0x10 Watchdog control

WDTRIG 0x11 Watchdog trigger

Table 58: Register WDCTRL (0x10) Watchdog control

MSB LSB

Content WDUSECW

PINTRIG WDTOW[1:0] WDFOW WDTEST REG-WDEN

-

Reset value 1 0 11 - - 1 0


External access R/W R/W R/W R R R/W R

Bit Description WDUSECW : Use closed window for register watchdog (WDT,CW)PINTRIG : 1: Register watchdog is triggered on PWML3 rising edge, 0: Register watchdog is triggered via WDTRIG register (SPI access)WDTOW[1:0] : Register watchdog open window time selection (WDT,OW)WDFOW : Register watchdog is in first open windowWDTEST : 1: Register watchdog is stopped (T pin = 'H'), 0: Register watchdog is runningREGWDEN : Enable register watchdog

Table 59: Register WDTRIG (0x11) Watchdog trigger

MSB LSB

Content - - - - - - - TRIG

Reset value 0 0 0 0 0 0 0 0


External access R R R R R R R R/W

Bit Description TRIG : Value has to be toggled on each write access in order to trigger the watchdog

For debugging purposes and software upload only, the watchdog can be stopped by setting T pin to VCC level.

6.5.3 Interrupt

The interrupt bits in IRQSTAT1 and IRQSTAT2 registers are set in case of the accordant failure event. Although there is no dedicated interrupt pin, an interrupt can be signalized to the microcontroller.

Table 60: Interrupt output configuration possibilities

Output Pin Mode Configuration Signal direction Shared functionalitywith

VSEL 1) VVCC = 3.3V IOCFG[1] = 1, IOCFG[0] = 1

High active VCC regulator voltageselection

VSEL 1) VVCC = 5V IOCFG[1] = 1, IOCFG[0] = 1

Low active VCC regulator voltageselection




Output Pin Mode Configuration Signal direction Shared functionalitywith

SO 2) - IOCFG[1] = 0, IOCFG[0] = 1

Low active SPI interface

1) Shared functionality with VSEL pin: Only available in run mode, since VSEL is used for VCC regulator voltage selection in power-up mode.2) Shared functionality with SO pin: If CSB = 'L', SO is used as SPI data output in any configuration.

An interrupt can only be cleared, when the failure situation is over. The interrupt bit is cleared by writing 1 to the interrupt bit in IRQSTAT registers or after power-up (applying battery voltage). It is not cleared during sleep mode.

The interrupt mask bits in IRQMSK1 and IRQMSK2 registers mask the effect of the interrupt bits in IRQSTAT registers on the selected interrupt output pin (VSEL or SO).

Warning: If shared functionality at SO pin is used, a SPI command causes events at the interrupt line, to be masked by the microcontroller.

Note: Even if the failure reaction is disabled in SAFECTRL register, the interrupt bits are set.

Note: A wired-or interrupt line at SO pin is not allowed.

Note: After finishing initial configuration the VG under voltage interrupt is likely set, since the VG voltage regulator needs some time to power-up.

Table 61: Interrupt Registers


IRQMSK1 0x12 Interrupt mask register

IRQSTAT1 0x13 Interrupt status register



Table 62: Register IRQMSK1 (0x12) Interrupt mask register

MSB LSB

Content EN_OT EN_OC EN_SC_HS3

EN_SC_HS2

EN_SC_HS1

EN_SC_LS3

EN_SC_LS2

EN_SC_LS1

Reset value 0 0 0 0 0 0 0 0


External access R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description EN_OT : Enable over temperatur interruptEN_OC : Enable motor over current interrupt / CMUX multiplexer interruptEN_SC_HS3 : Enable HS 3 short circuit interruptEN_SC_HS2 : Enable HS 2 short circuit interruptEN_SC_HS1 : Enable HS 1 short circuit interruptEN_SC_LS3 : Enable LS 3 short circuit interruptEN_SC_LS2 : Enable LS 2 short circuit interruptEN_SC_LS1 : Enable LS 1 short circuit interrupt




Table 63: Register IRQSTAT1 (0x13) Interrupt status register

MSB LSB

Content OT OC SC_HS3 SC_HS2 SC_HS1 SC_LS3 SC_LS2 SC_LS1

Reset value 0 0 0 0 0 0 0 0

Internal access R/W R/W R/W R/W R/W R/W R/W R/W

External access R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description OT : Over temperature interrupt flagOC : Over current interrupt flag / motor over current interrupt / CMUX multiplexer interrupt flagSC_HS3 : HS 3 short circuit interrupt flagSC_HS2 : HS 2 short circuit interrupt flagSC_HS1 : HS 1 short circuit interrupt flagSC_LS3 : LS 3 short circuit interrupt flagSC_LS2 : LS 2 short circuit interrupt flagSC_LS1 : LS 1 short circuit interrupt flag

Table 64: Register IRQMSK2 (0x14) Interrupt mask register

MSB LSB

Content - - - EN_REG_WD

EN_VBAT_OV

EN_VG_OV

EN_VG_UV

EN_VCC_UV

Reset value 0 0 0 0 0 0 0 0


External access R R R R/W R/W R/W R/W R/W

Bit Description EN_REG_WD : Enable register watchdog interruptEN_VBAT_OV : Enable VBAT over voltage interruptEN_VG_OV : Enable VG over voltage interruptEN_VG_UV : Enable VG under voltage interruptEN_VCC_UV : Enable VCC under voltage interrupt

Table 65: Register IRQSTAT2 (0x15) Interrupt status register

MSB LSB

Content - - - REG_WD VBAT_OV VG_OV VG_UV VCC_UV

Reset value 0 0 0 0 0 0 0 0

Internal access R R R R/W R/W R/W R/W R/W

External access R R R R/W R/W R/W R/W R/W

Bit Description REG_WD : Register watchdog interrupt flagVBAT_OV : VBAT over voltage interrupt flagVG_OV : VG over voltage interrupt flagVG_UV : VG under voltage interrupt flagVCC_UV : VCC under voltage interrupt flag

6.5.4 Internal Digital Signal Monitoring

Internal digital signals, e. g. monitoring comparator outputs or digital input pin levels, can be monitored by the microcontroller. They can be switched to SO pin transparently via DMUX register or read via SPI in DMON1-2 register. DMUX register write access is locked, if EDMUX bit in SECURCTRL register is 0.




Table 66: Register for output of additional internal values


DMUX 0x19 Digital value output SO selection

DMON1 0x1A Digital value monitoring

DMON2 0x1B Digital value monitoring

Table 67: Register DMON1 (0x1A) Digital value monitoring

MSB LSB

Content OT OC SC_HS3 SC_HS2 SC_HS1 SC_LS3 SC_LS2 SC_LS1

Reset value - - - - - - - -


External access R R R R R R R R

Bit Description OT : Over temperature comparator levelOC : Motor over current comparator levelSC_HS3 : High side 3 short circuit comparator levelSC_HS2 : High side 2 short circuit comparator levelSC_HS1 : High side 1 short circuit comparator levelSC_LS3 : Low side 3 short circuit comparator levelSC_LS2 : Low side 2 short circuit comparator levelSC_LS1 : Low side 1 short circuit comparator level

Table 68: Register DMON2 (0x1B) Digital value monitoring

MSB LSB

Content S - - - VBAT_OV VG_OV VG_UV -

Reset value - - - - - - - 0


External access R R R R R R R R

Bit Description S : S Pin input comparator levelVBAT_OV : VBAT over voltage comparator levelVG_OV : VG over voltage comparator levelVG_UV : VG under voltage comparator level

Table 69: Register DMUX (0x19) Digital value output SO selection

MSB LSB

Content - - - - S[3:0]



External access R R R R R/W

Bit Description S[3:0] : SO pin digital signal output selection, see below for coding

Table 70: Digital value output code table

DMUX Value at pin SO

0 No internal digital signal output

1 VSEL pin level

2 S pin level




DMUX Value at pin SO

3 T pin level

4 Motor over current comparator level

5 Over temperature comparator level

9 VG under voltage comparator level

6.6 Communication Interfaces

6.6.1 Bus Interface (PWM)

The BUS interface is a bidirectional, single wire, high voltage, low active interface. It can be used as a transceiver for PWM control with error feedback.

Figure 26: BUS block diagram

The BUS interface can be used as master or slave. The transmission data on TXD pin is converted into the BUS signal through a current limited, wave-shaping low side driver. The receiver converts the data stream from BUS to RXD pin.

Note: It may be neccessary to protect the BUS terminal against EME and ESD on PCB according to requirements.

Figure 27: BUS transceiver transmit timing




Figure 28: BUS transceiver receive timing

Table 71: Register IOCFG (0x06) Interfaces configuration

MSB LSB

Content TXDTO_EN

LIN_FLASH

- - - - VSELDIR EINT

Reset value 1 0 0 0 0 0 0 0


External access R/W R/W R R R R R/W R/W

Bit Description TXDTO_EN : Enable TXD dominant clamping time-outLIN_FLASH : Enable LIN flash modeVSELDIR : 1: VSEL is interrupt output, 0: SO is interrupt outputEINT : Enable shared functionality at VSEL or SO pin (interrupt output)

6.6.1.1 Flash-mode and TXD Time-OutA flash mode allows an increasing of the transmit baud rate up to tbd and the receive baud rate up to tbd. The flashmode can be activated by setting IOCFG[6] = 1.

In order to prevent the BUS from being permanent dominant in case of permanent low level at TXD pin, a TXD time-out timer switches BUS to recessive mode after approximately 8ms. The timer is triggered by a negative TXD edge and reset by a positive TXD edge. This function can be deactivated by writing IOCFG[7] = 0.

6.6.2 SPI

The SPI interface is used for data transfer between the microcontroller and the IC. The SPI clock is high active (CPOL = 0). The data is sampled with second clock edge (CPHA = 1). The SPI output pin SO is switched to high impedance, if CSB = 'H' (SPI inactive).

Note: It is recommended to re-read every SPI write command to ensure a correct configuration of the IC.




Figure 29: SPI write command

Figure 30: SPI read command

Figure 31: SPI timing diagram

A[6:0]: register address, D[7:0]: register data




7 Register Table

Table 72: Register Table


CHIPCTRL 0x02 Chip control

SLEEPCTRL 0x03 Sleep mode control

SECURCTRL 0x04 Security configuration

SAFECTRL 0x05 Safety functions configuration

IOCFG 0x06 Interfaces configuration

VREGCTRL 0x07 Supply control

SCPCTRL 0x0B Short circuit protection control

WDCTRL 0x10 Watchdog control

WDTRIG 0x11 Watchdog trigger





IOCOMPTHR 0x16 Motor over current threshold

AMUX 0x17 Analogue signal measurement selection

CMUX 0x18 IO comparator input signal select

DMUX 0x19 Digital value output SO selection

DMON1 0x1A Digital value monitoring

DMON2 0x1B Digital value monitoring

BRIDGEMODE 0x20 Bridge mode configuration

SROFFSC 0x23 Low and high side gate off-current selection in case of drain-source short circuit.

SRHSON 0x24 High side gate on-current selection

SRLSON 0x25 Low side gate on-current selection

SRHSOFF 0x26 High side gate off-current selection

SRLSOFF 0x27 Low side gate off-current selection

SCTH_HS 0x28 High side short circuit threshold selection

SCTH_LS 0x29 Low side short circuit threshold selection

Table 73: Restricted register table

Register Comment

SECURCTRL

SAFECTRL Writeable if ESAFECTRL bit in SECURCTRL register is set.Bit SOC also writeable if EACMUX is set.

SCPCTRL

WDCTRL

VREGCTRL

CHIPCTRL

AMUX Writeable if EACMUX bit in SECURCTRL register is set.

CMUX Writeable if EACMUX bit in SECURCTRL register is set.

DMUX Writeable if EDMUX bit in SECURCTRL register is set.

After setting bit ESECURE in SECURCTRL register the registers listed in this table are read-only.




8 ESD, Latchup and EMC

8.1 Electro Static Discharge (ESD)

Table 74: ESD on IC Level, Human Body Model (HBM)

Standard AEC-Q100-002

Model Human Body Model

Capacitance 100 pF

Resistance Ω1,5 k

Minimum withstand Voltage +/- 2 kV

Table 75: ESD Test on IC Level for pin S and VIN

Optional ESD Test Test equipment similar to AEC-Q100-002

Test point Pins S, VIN, BUS to system ground

Capacitance 100 pF

Resistance Ω1,5 k

Minimum withstand Voltage +/- 4 kV

Table 76: ESD on IC Level, Charged Device Model (CDM)

Standard AEC-Q100-011

Model Charged Device Model

Resistance Ω1

Minimum withstand Voltage +/- 750 V for edge pins

+/- 500 V for all other pins

Pulse rise time (10%-90%) <400 ps

8.2 Latch-up

Latch-up performance is validated according JEDEC standard JESD 78 in its valid revision.




9 Marking

9.1 Top Side

Table 77: Top Side

E L M O S (Logo)

52310A

XXXXU

YWW*#

where

Table 78: Marking of the Devices

Explanation Signature

ELMOS project number 52310

ELMOS project revision code A

Production lot number XXXX

Assembler code U

Year and week of assembly YWW

ELMOS internal code *

ELMOS internal code #

9.2 Bottom Side

No marking.




10 General

10.1 Disclaimer

WARNING – Life Support Applications PolicyElmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless,semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physicalstress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products, to observe standards of safety, andto avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product could cause loss of human life, bodyinjury or damage to property. In the development of your design, please ensure that Elmos Semiconductor AG products areused within specified operating ranges as set forth in the most recent product specifications.

General DisclaimerInformation furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsibility isassumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which mayresult from its use. No license is granted by implication or otherwise under any patent or patent rights of Elmos SemiconductorAG. Elmos Semiconductor AG reserves the right to make changes to this document or the products contained therein withoutprior notice, to improve performance, reliability, or manufacturability.

Application DisclaimerCircuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means ofillustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given.The information in the application examples has been carefully checked and is believed to be entirely reliable. However, noresponsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of thesemiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others.

10.1.1 Contact Information

HeadquartersElmos Semiconductor AG

Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany) ℡: +492317549100 �: [email protected] �: www.elmos.com

Sales and Application Support Office North AmericaElmos NA. Inc.32255 Northwestern Highway • Suite 220 Farmington Hills

MI 48334 (USA) ℡: +12488653200 �: [email protected]

Sales and Application Support Office ChinaElmos Semiconductor Technology (Shanghai) Co., Ltd.Unit 16B, 16F Zhao Feng World Trade Building, No. 369 Jiang Su Road, Chang Ning District,

Shanghai, PR China, 200050 ℡: +86216210 0908 �: [email protected]

Sales and Application Support Office KoreaElmos KoreaB-1007, U-Space 2, #670 Daewangpangyo-ro, Sampyoung-dong, Bunddang-gu, Sungnam-si

Kyounggi-do 463-400 Korea ℡: +82317141131 �: [email protected]

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Tokyo 108-0023 Japan ℡: +81334517101 �: [email protected]

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#09-13 ICON@IBP • 609935 Singapore ℡: +65 6908 1261 �: [email protected]

© Elmos Semiconductor AG, 2015. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.




11 Record of Revisions

Table 79: Record of Revisions

Chapter Rev. Description of change Date Who

- 00 Initial version 05.11.15 HHAU / KFH




12 Index

Table of Content1 Package and Pinout...................................................................................................................................................2

1.1 Pin Description...................................................................................................................................................21.2 Package Reference............................................................................................................................................41.3 Package Pinout..................................................................................................................................................4

2 Typical Application......................................................................................................................................................53 Block Diagram............................................................................................................................................................84 Operating Conditions..................................................................................................................................................9

4.1 Absolute Maximum Ratings................................................................................................................................94.2 Recommended Operating Conditions..............................................................................................................10

5 Detailed Electrical Specification...............................................................................................................................125.1 Power Supply and Management......................................................................................................................12

5.1.1 VCC Microcontroller Supply.....................................................................................................................125.1.2 VG Power FET Gate Driver Supply.........................................................................................................125.1.3 Charge Pump Driver................................................................................................................................125.1.4 Internal Supply.........................................................................................................................................135.1.5 Reset........................................................................................................................................................135.1.6 Chip Control.............................................................................................................................................13

5.2 Power FET Gate Driver....................................................................................................................................145.2.1 Short Circuit Protection............................................................................................................................15

5.3 Measurement Functions...................................................................................................................................155.3.1 Motor Current Measurement Amplifier.....................................................................................................155.3.2 Analogue Signal Measurement................................................................................................................16

5.4 Monitoring Functions........................................................................................................................................165.4.1 Motor Over Current..................................................................................................................................175.4.2 Watchdog.................................................................................................................................................17

5.5 Communication Interfaces................................................................................................................................185.5.1 Bus Interface (PWM)................................................................................................................................18

6 Functional Description .............................................................................................................................................196.1 Power Supply and Management......................................................................................................................19

6.1.1 VCC Microcontroller Supply.....................................................................................................................196.1.2 VG Power FET Gate Driver Supply.........................................................................................................216.1.3 Charge Pump Driver................................................................................................................................216.1.4 Internal Supply.........................................................................................................................................226.1.5 Reset........................................................................................................................................................226.1.6 Chip Control.............................................................................................................................................22

6.1.6.1 Power-up..........................................................................................................................................236.1.6.2 Shut-down and Sleep Mode.............................................................................................................236.1.6.3 Wake-up...........................................................................................................................................24

6.1.7 Board Level Protection.............................................................................................................................266.2 Initial Configuration and Security.....................................................................................................................266.3 Power FET Gate Driver....................................................................................................................................27

6.3.1 Gate Control Input Modes........................................................................................................................306.3.2 Short Circuit Protection............................................................................................................................31

6.3.2.1 Superior Short Circuit Failure Reaction...........................................................................................326.4 Measurement Functions...................................................................................................................................34

6.4.1 Motor Current Measurement Amplifier.....................................................................................................346.4.2 Analogue Signal Measurement................................................................................................................35

6.5 Monitoring Functions........................................................................................................................................366.5.1 Motor Over Current..................................................................................................................................396.5.2 Watchdog.................................................................................................................................................406.5.3 Interrupt....................................................................................................................................................416.5.4 Internal Digital Signal Monitoring.............................................................................................................43




6.6 Communication Interfaces................................................................................................................................456.6.1 Bus Interface (PWM)................................................................................................................................45

6.6.1.1 Flash-mode and TXD Time-Out.......................................................................................................466.6.2 SPI............................................................................................................................................................46

7 Register Table..........................................................................................................................................................488 ESD, Latchup and EMC...........................................................................................................................................49

8.1 Electro Static Discharge (ESD)........................................................................................................................498.2 Latch-up............................................................................................................................................................49

9 Marking.....................................................................................................................................................................509.1 Top Side...........................................................................................................................................................509.2 Bottom Side......................................................................................................................................................50

10 General...................................................................................................................................................................5110.1 Disclaimer.......................................................................................................................................................51

10.1.1 Contact Information................................................................................................................................5111 Record of Revisions...............................................................................................................................................5212 Index.......................................................................................................................................................................53

Illustration IndexFigure 1: Typical Application.........................................................................................................................................1Figure 2: IC pin clamping diagram................................................................................................................................3Figure 3: QFN44L7 pin configuration, transparent top view, not to scale.....................................................................4Figure 4: Typical application..........................................................................................................................................5Figure 5: Proposal of 1-stage charge pump..................................................................................................................6Figure 6: Proposal of 2-stage charge pump..................................................................................................................7Figure 7: Proposal of 3-stage charge pump..................................................................................................................7Figure 8: Block Diagram................................................................................................................................................8Figure 9: VBAT recommended operating condition functional overview (not to scale)..............................................11Figure 10: Power supply block diagram......................................................................................................................19Figure 11: VCC regulator block diagram, case microcontroller supply is 3.3V, VREGCTRL[2] to be set to 0...........20Figure 12: VCC regulator block diagram, case microcontroller supply is 5V, VREGCTRL[2] to be set to 1..............20Figure 13: VCC block diagram, case external VCC boost transistor..........................................................................20Figure 14: Proposal of short circuit protection at microcontroller supply, when using an external boost transistor...21Figure 15: VG regulator block diagram.......................................................................................................................21Figure 16: Charge pump driver block diagram............................................................................................................22Figure 17: IC states diagram.......................................................................................................................................22Figure 18: Power up timing diagram, typical scenario................................................................................................23Figure 19: Shut-down timing diagram.........................................................................................................................24Figure 20: IC states diagram, case VIN used for emergency shut-off........................................................................27Figure 21: Power FET gate driver block diagram........................................................................................................28Figure 22: Power FET gate driver transfer characteristic timing diagram...................................................................29Figure 23: Short circuit protection block diagram .......................................................................................................31Figure 24: Motor current measurement amplifier circuitry...........................................................................................34Figure 25: Motor over current circuitry........................................................................................................................39Figure 26: BUS block diagram.....................................................................................................................................45Figure 27: BUS transceiver transmit timing.................................................................................................................45Figure 28: BUS transceiver receive timing..................................................................................................................46Figure 29: SPI write command....................................................................................................................................47Figure 30: SPI read command.....................................................................................................................................47Figure 31: SPI timing diagram.....................................................................................................................................47



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