AC 2008-1410: PRACTICAL EXERCISE FOR EFFICIENT EDUCATION OFCOMPUTER SYSTEM ARCHITECTURE

Soonghwan Ro, Kongju University, Rep. of KoreaHe received an B.S., M.S. and PhD degrees from the Department of Electronics Engineering atKorea University in 1987, 1989, and 1993 respectively. He was a research engineer of Electronicsand Telecommunications Research Institute and University of Birmingham in 1997 and 2003repectively. Since March 1994 he has been an professor at Kongju National University, Korea.His research interests include pervasive computing, embedded systems and mobilecommunication.

© American Society for Engineering Education, 2008

Page 13.989.1

Practical Exercise for Efficient Education of Computer System Architecture

Abstract

Computer System Architecture, written by M. Morris Mano, has been the most widely used

teaching material for training and understanding computer operation since its publication. This

teaching material provides an understanding of computer operation, assembly language and

assemblers, and enhances ability in hardware design and software programming.

However, it is very difficult for students to learn this subject through theoretical lectures alone.

Therefore, in order to help students to understand, the lessons were followed with the design

project “A Simple Computer,” which was introduced in the teaching material. However, not

many students could have completed the above term project during the period when this subject

was taught. Those who succeeded learned a lot, but others maintained a lack of understanding of

the subject regardless of the time they invested.

DigiCom, which operates in the same manner as the system introduced in the teaching material,

was designed. DigiCom was developed with VHDL using the ALTERA design software Quartus

II and implemented on the ALTERA Cyclone FPGA. This kit is a not general digital design kit,

but it has the same features that “A Simple Computer” introduced in Computer System

Architecture.

DigiCom was utilized in the 2007 term. The learning performance and improvements of the

students were analyzed by comparing the course evaluation, examination marks and term project

results between the year 2007 and previous years.

The effectiveness of the new kit could be confirmed by quantitative analysis, and also

qualitatively in the class. It could also be seen that the students’ interest in the course improved.

1. Overview

Computer System Architecture, [1]

written by M. Morris Mano, has been the most widely used

teaching material for training and understanding computer operation since its publication. This

teaching material provides an understanding of computer operation, assembly language and

assemblers, and enhances ability in hardware design and software programming.

However, it is very difficult for students to learn this subject through theoretical lectures alone.

Therefore, in order to help students to understand, a term project to design and implement “A

Simple Computer (ASC)” was assigned according to the following process:

- Design and implement “A Simple Computer” into the teaching material with VHDL

- Program an assembler to assemble the example program.

- Assemble the example program with the developed assembler and run that on the

developed “A Simple Computer.”

Page 13.989.2

Fortunately, since the text describes all of the instructions and micro-operations in detail and free

design software such as the QuartusII[5]

WebEdition of ALTERA and the ISE Webpac[7]

of

Xilnx are available, the above design and practice are possible.

However, not many students were able to complete the term project during the period when this

subject was taught. Those who succeeded would have learned a lot, but it was found that the

others maintained a lack of understanding on the subject, regardless of time they invested.

It was concluded that another teaching method was necessary, and DigiCom[2]

, which operates in

the same manner as the system introduced in the teaching material, was designed and developed.

DigiCom was developed with VHDL[3, 4]

using the ALTERA design software Quartus II and

implemented on the ALTERA Cyclone FPGA[6]

. This kit is not a general digital design kit, but it

has the same features that “A Simple Computer (ASC) [1]

” introduced in Computer System

Architecture.

DigiCom was utilized in the 2007 term. The learning performance and improvements of the

students were analyzed by comparing the course evaluation, examination marks and term project

result between the year 2007 and the previous years.

The rest of the paper is organized as follows. Section 2 provides the result of analysis on the

learning performance before 2007 and the motivation for developing DigiCom. Then, in section

3, we discuss the general features of the educational kit to improve the educational effect. In

section 4, we describe the implementation and operation of DigiCom, and we analyze the

learning performance when DigiCom is utilized during the course work in section 5. Finally we

conclude this paper in section 6.

2. Analysis of the learning performance during previous courses

The learning objective and contents of the “Computer Architecture” course are “to understand

the basic structure and operational principle of a computer system, the concept of assembly

language, and the process of software execution by a computer system.” In order to accomplish

the goals of this course, the term project of implementing “A Simple Computer (ASC)” and the

programming of an assembler were conducted after the intermediate examination, in addition to

the lectures on theory. The process of the term project included design with VHDL using the

ALTERA QuartusII software, verifying the design by simulation, downloading to the digital

design kit and execution. The assembler was programmed in Windows or Linux OS. The

assembly program was converted by the assembler, and executable binary code was included in

the ASC memory as the initialization data for execution.

The evaluation result of the term project was classified into 4 grades, each of which was as

follows:

Grade 1: the assembly program can be executed on the kit

Grade 2: design was finished but the assembly program cannot be executed, and debugging

was not completed

Grade 3: functional blocks were implemented, but not integrated

Grade 4: even functional blocks were not implemented

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In the above Grades, Grade 1 includes the case that design can execute the assembly program,

though not perfectly, and the students who achieved Grade 1 were considered to fully understand

ASC and to have performed their tasks successfully. Table 1 below presents the ratio of students

with Grade 1 for several years.

Table 1. The success rate of term project

Year 2001 2002 2004 2005 2006

Success Rate (%) 11 12 12 13 20

As shown in Table 1, many students were unsuccessful in completing the above term project

during the period when this subject was taught. Those who succeeded would have learned a lot.

However, others still lacked understanding despite the amount of time spent on the term project.

To analyze the learning performance of the students of the subject before 2007, the marks of the

students of all the terms with the course were classified into the 4 Grades above, and the average

marks of the students of each Grade in the final exam after the term project were compared.

Table 2 presents the analysis results.

Table 2. The average marks of final exam classified into 4 Grades by year

Year

Grade 2001 2002 2004 2005 2006

1st grade group 73.2 70.6 45.6 63.0 61.3

2nd

grade group 43.4 42.2 32.5 36.5 47.5

3rd

grade group 42.0 40.8 24.0 41.5 22.5

4th

grade group 16.0 28.0 11.1 20.0 20.8

As shown in the Table 2, the differences in the marks between 1st grade groups and other groups

are large. This means that the deviation between the students who succeeded in the term project

and those who did not is large. In the course evaluation, the suggestions of the students on the

improvement of the lesson were surveyed. Several students commented that the term project was

too difficult.

It was concluded that another teaching method was necessary, and DigiCom, which operates

similarly to the system, was introduced into the teaching material and was designed and

implemented.

3. Features of the general educational kit to improve educational effect

Generally, educational kits are developed to be available for multiple courses. They may look

economical, but they are not desirable for learning efficiency. In this course, in order to execute

ASC after implementing it with VHDL, it must be downloaded to FPGA. At this time, general

digital design kits using FPGA can be used. For this course, the term project had been conducted

using a general digital design kit before using the DigiCom.

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The general purpose digital design kit was developed to be useful in all the courses where digital

circuitry is used, which means it is used for 3-4 courses on average. However, not all

departments have a course where the kit can be used. In my department, it is used partially in the

“Digital Engineering” and “Computer Architecture” courses, which are theory-centered courses.

Therefore, it cannot be utilized 100%. Due to its diversified functions, it takes time for students

to learn how to use a general purpose kit, and students cannot focus on the course study.

Furthermore, its high price compels several students to use one kit. Finally, its physical heavy

weight is also a problem because students cannot carry it for the practice at hand.

The following were taken into consideration, on the basis of the results of the comparison above,

in the development of the DigiCom to improve learning performance.

� Same functionalities as the ASC

The most important consideration was that the developed kit functions in the same way as the

ASC introduced in Computer System Architecture. This concept is based on the fact that a

beginner can understand software programming easily by executing well-programmed

software. “Computer Architecture” can be understood easily by running the ASC.

� Economy

In the economic consideration, as shown in the above comparison, a kit can be used in

multiple courses with diversified functionalities, even though it is expensive. In addition, it

is not guaranteed that all courses that can utilize the kit will utilize it. Because the structure

of DigiCom is very simple, the manufacturing cost is inexpensive.

� Ease of use

Conventional kits could not be carried by students due to their large volume. The volume of

DigiCom is one tenth of conventional kits, enabling portability. The power is supplied via a

USB port; therefore, it can be used anywhere a desktop or laptop PC is available.

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4. Development and operation of DigiCom

4.1. ASC and hardware structure

The ASC structure is shown in Fig. 1 and implemented in the ALTERA Cyclone device.

LD(TR), LD(AR), INR(AR), CLR(AR), LD(PC), INR(PC), CLR(PC)

LD(DR), INR(DR), LD(AC), INR(AC), CLR(AC), LD(IR)

X[ 7..0]

T[15..0]

CB[15..0]

AC_IN[ 15..0]

M_EN, M_RD, M_WR

AND, ADD, DR, INPR, COM,

SHR, SHL, E_CLR, E_CME, INR

CB[ 7..0]

INTERRUPT

AC[ 15..0] , DR[ 15..0]

SC_CLR

SC_STOP

AC[ 15..0] , DR[ 15..0] , IR[ 15..0]

CARRY

FGI, FGO

IR[ 14..12]ENABLE_DECODE

R, T[ 15..0]

RESET, CLK

R, T[ 15..0]

T[ 15..0]

M_CLK

AR[ 11..0]

RESET input

Clock input

RESET

CLK_IN

CLK

M_T[15..0]

S_bit

M_CLK

INDIRECT

DEBOUNCE_CLK

OUTR_LD, INP_RD, I_EN, I_DI

RESET, CLK

RESET, CLK

FGO_SW KEY_IN(0~ F)

INP_REG[ 7..0]

7SEG_OUT[ a~ g]

INP_REG[ 7..0]

INP_REG[ 7..0]

RESET, CLK

SELECT_SW AC[ 15..0] , DR[ 15..0] , IR[ 15..0] , TR[ 15..0] , PC[ 11..0] , AR[ 11..0]

REG_OUT[31..0]

FF_OUT[7..0]

RESET, CLK

Fig. 1. Structure of “A Simple Computer” implemented in Cyclone FPGA

Each component is designed with VHDL in functional units, and designed functional units are

created into BSFs (Block Symbol Files). Created BSFs are called by the QuartusII Block Editor

and integrated into ASC. DigiCom was implemented using Cyclone FPGA, in which ASC was

configured. The structure and implemented DigiCom are shown in Fig. 2.

Page 13.989.6

FPGA

0 1 2 3

4 5 6 7

8 9 A B

C D E F

0 ~ F

a ~ g

switch

Run

Step by instruction

Step by clock

Flip-flops(LEDs)

I, S, E, R, IEN, FGI, FGOclock

FGO

switch

Output 7-Seg.

Register 7-Seg.

(AR, PC, DR, AC, INPR, IR, TR, OUTR)

(a) Structure of DigiCom (b) Implemented DigiCom

Fig. 2. DigiCom

The hardware consists of the FPGA, including ASC; 7-segment LEDs which display output and

register values; LEDs which show each flip-flop that stores the internal states of the ASC; and

the switches that control the running mode. The switches control the program execution by the

program unit, the instruction unit, or the clock unit. The ASC has 8 registers. Many 7-segment

LEDs are required to display all of these register values; therefore, four 7-segment LEDs display

register values sequentially by the switch operation.

The input device is a 16-keyboard from 0 to F in hexadecimal and the output device is two 7-

segments which display 8-bit unit output register. However, when the ASC output is continuous,

the value is transmitted to the output buffer when the output flag (FGO) is set. Therefore,

continuous output is made by setting the FGO by pressing the external switch.

This kit is not a general digital design kit, but it has the same features that “A Simple Computer”

introduced in “Computer System Architecture”. Because of the following features, the developed

system is expected to help students to more fully understand computer architecture. The key

features of DigiCom are as follows;

- Assembly programs can be executed by clock step or instruction step mode. Register and

flag values can be monitored.

- Since it was developed on a functional block unit basis, functionalities can be verified by

implementing partial functions for practice.

- New commands can be developed and applied in the circuit for improvement.

4.2. Practice

How to use the implemented kit is described step by step. The description below is for the

understanding of ASC operation. It is important to learn how to use the kit and the concept of

assembly program executed by the processor before carrying out the following instructions.

4.2.1. Understanding of micro-operation

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In this practice step, students run a simple assembly program which sums two operands in the

memory and saves the sum into the memory. After executing each instruction in instruction step

mode, students fill the register-flipflop table shown in Table 3.

Table 3. The example program and result of instruction step mode operation

After the execution in the instruction step mode, the same program is executed in the clock step

mode. After each T-clock unit execution, students fill the register-flipflop table shown in Table 4.

Table 4. Result of clock step mode operation Register & Flip Flops

Instruction Micro operations AR PC DR AC INPR IR TR OUTR I S E R IEN FGI

FGO

ORG 100 0 100 0 0 0 0 0 0 0 0 0 0 0 0 1

R’T0 : AR←PC 100 100 0 0 0 0 0 0 0 0 0 0 0 0 1

R’T1 : IR←M[AR], PC←PC +1 100 101 0 0 0 2104 0 0 0 0 0 0 0 0 1

R’T2 : D0, …,D7←Decode IR (12-14)

AR←IR(0-11), I←IR(15)

104 101 0 0 0 2104 0 0 0 0 0 0 0 0 1

D’7IT3 : AR←M[AR] 104 101 0 0 0 2104 0 0 0 0 0 0 0 0 1

D2T4 : DR←M[AR] 104 101 53 0 0 2104 0 0 0 0 0 0 0 0 1

LDA A

D2T5 : AC←DR, SC←0 104 101 53 53 0 2104 0 0 0 0 0 0 0 0 1

R’T0 : AR←PC 101 101 53 53 0 2104 0 0 0 0 0 0 0 0 1

R’T1 : IR←M[AR], PC←PC +1 101 102 53 53 0 1105 0 0 0 0 0 0 0 0 1

R’T2 : D0, …,D7←Decode IR(12-14)

AR←IR(0-11), I←IR(15)

105 102 53 53 0 1105 0 0 0 0 0 0 0 0 1

D’7IT3 : AR←M[AR] 105 102 53 53 0 1105 0 0 0 0 0 0 0 0 1

D1T4 : DR←M[AR] 105 102 FFE9 53 0 1105 0 0 0 0 0 0 0 0 1

ADD B

D1T5 : AC← AC+DR, E←Cout, SC←0 105 102 FFE9 3C 0 1105 0 0 0 0 1 0 0 0 1

R’T0 : AR←PC 102 102 FFE9 3C 0 1105 0 0 0 0 1 0 0 0 1

R’T1 : IR←M[AR], PC← C +1 102 103 FFE9 3C 0 3106 0 0 0 0 1 0 0 0 1

R’T2 : D0, …,D7←Decode IR (12-14)

AR←IR(0-11), I←IR(15)

106 103 FFE9 3C 0 3106 0 0 0 0 1 0 0 0 1

D’7IT3 : AR←M[AR] 106 103 FFE9 3C 0 3106 0 0 0 0 1 0 0 0 1

STA C

D3T4 : M[AR]←AC, SC←0 106 103 FFE9 3C 0 3106 0 0 0 0 1 0 0 0 1

R’T0 : AR←PC 103 103 FFE9 3C 0 3106 0 0 0 0 1 0 0 0 1

R’T1 : IR←M[AR], PC←PC +1 103 104 FFE9 3C 0 7001 0 0 0 0 1 0 0 0 1

R’T2 : D0, …,D7←DecodeIR(12-14)

AR←IR(0-11), I←IR(15)

1 104 FFE9 3C 0 7001 0 0 0 0 1 0 0 0 1 HLT

rB0 : S←0 1 104 FFE9 3C 0 7001 0 0 0 0 1 0 0 0 1

While students fill the register-flipflop table, they find the VHDL code in which a control signal

is generated, which enables a corresponding micro-operation at each T-cycle in ASC VHDL

design. For example, the instruction “STA C” in the example program of Table 3 consists of 5 T-

clocks. Memory-write and memory-enable signals have to be generated to save the result of the

summation at the last T4 clock, and the signal which clears the SC must be generated to initialize

the SC (Sequence Counter). By repeating this practice, the micro-operation can be easily

understood.

Register(HEX) Flip Flop Register,FF Instruction AR PC DR AC INPR IR TR OUTR I S E R IEN FGI FGO

ORG 100 000 100 0000 0000 00 0000 0000 00 0 0 0 0 0 0 1

LDA A 104 101 0053 0053 00 2104 0000 00 0 0 0 0 0 0 1

ADD B 105 102 FFE9 003C 00 1105 0000 00 0 0 1 0 0 0 1

STA C 106 103 FFE9 003C 00 3106 0000 00 0 0 1 0 0 0 1

HLT 001 104 FFE9 003C 00 7001 0000 00 0 0 1 0 0 0 1

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Table 5. VHDL code which generate control signals at T4 clock of “STA C” instruction M[AR]←AC M_write <= (int_R and M_t1 and clk2) -- interrupt cycle

or (d(3) and M_t4 and clk2) -- memory STA

or (d(5) and M_t4 and clk2) -- memory BSA

or (d(6) and M_t6 and clk2); -- memory ISZ

M_enable <= (M_t1 and clk2) -- interrupt cycle

or (d(3) and M_t4 and clk2) -- memory STA

or (d(5) and M_t4 and clk2) -- memory BSA

or (d(6) and M_t6 and clk2) -- memory ISZ

or (not d(7) and i and M_t3 and clk2) -- decode

or (d(0) and M_t4 and clk2) -- memory AND

or (d(1) and M_t4 and clk2) -- memory ADD

or (d(2) and M_t4 and clk2) -- memory LDA

or (d(6) and M_t4 and clk2); -- memory ISZ

SC←0 sc_clr <= p_buf -- I/O reference instruction

or r_buf -- register reference instruction

or (int_R and t(2)) -- interrupt cycle

or (d(0) and t(5)) -- memory AND

or (d(1) and t(5)) -- memory ADD

or (d(2) and t(5)) -- memory LDA

or (d(3) and t(4)) -- memory STA

or (d(4) and t(4)) -- memory BUN

or (d(5) and t(5)) -- memory BSA

or (d(6) and t(6)); -- memory ISZ

4.2.2. Adding new instructions

As described in the Chapter 5 problems in the text, the existing instructions are replaced with

new memory-reference instructions, as listed in Table 6. In order to replace existing instructions,

students should define the micro-operations for that instruction, modify the VHDL code, and run

it on the kit with a simple program to confirm the result.

Table 6. New memory-reference instructions which replace existing instructions(Problem 5-13) Symbol Opcode Symbolic designation Description in words

XOR

ADM

SUB

XCH

SEQ

BPA

000

001

010

011

100

101

AC�AC XOR M[EA]

M[EA]�M[EA] + AC

AC�AC – M[EA]

AC�M[EA], M[EA]�AC

If(M[EA]=AC) then (PC�PC + 1)

If(AC > 0) then (PC�EA)

Exclusive-OR to AC

Add AC to memory

Subtract memory from AC

Exchange AC and memory

Skip on equal

Branch if AC positive and non-zero

For example, among the instructions above, one might replace the existing instruction with a new

one which performs the exchange of the two operands stored in AC and memory. The micro-

operation is defined as shown below. The STA instruction corresponding to the opcode “011”

with the XCH instruction in the instruction set must be replaced, and the register transfer

statement has to be defined for each T-clock as shown in Table 7.

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Table 7. Definition of register transfer statement for XCH instruction

Instruction Register Transfer Statement

XCH

R’T0 : AR←PC

R’T1 : IR←M[AR], PC←PC +1

R’T2 : D0, …,D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)

D3T4 : DR � M[AR]

D3T5 : M[AR] � AC, AC � DR, SC � 0

To verify the micro-operation defined above after implementation with VHDL, a simple program

which can confirm the operation of the instruction is prepared and executed on the kit. To repeat

this practice, the software has to be programmed, assembled, and included in memory as initial

data. Next, the VHDL code has to be compiled and downloaded repeatedly. The binary machine

code can be created by a manual assemble with the defined instruction set; however, this takes

time and may lead to an error while assembling. Therefore, an assembler was developed to

simplify the execution of the program. Since the QuartusII design can include memory which

can be initialized with executable binary machine code, memory can easily be initialized by

making the developed assembler have the same output format as that of the QuartusII memory

initialization file (MIF). Fig. 3 shows the simple program assembled by the assembler to test the

XCH instruction.

(a) Source program (b) Assembled result with MIF format

Fig. 3. Test program XCH and assembled result with MIF format

4.2.3. ASC design

As mentioned in the introduction, designing the whole system will be of great help for

understanding computer operation principle and practicing VHDL. With the practice described

above, understanding of the execution procedure of instructions in processor and computer

system operation can be greatly enhanced. However, it will take too much time to acquire the

desired learning performance for this course. For the students who have great interest in this

course, an optional term project which implements a new ASC was conducted.

4.3. Other kinds of practices for improving learning performance

We surveyed other teachers who use the same teaching material by email and phone calls to

investigate other methods to improve learning performance. We found that some are teaching a

Page 13.989.10

purely theoretical course because their departments are software-based or they believe the term

design project is too difficult for students to perform. In addition to theoretical lectures, there are

other methods.

� Designing ASC and executing on a general digital training kit:

After designing ASC with VHDL or schematic, the designed ASC is executed on a general

digital training kit. The problem with this method is that the difference in the learning

performance between the students who succeeded in the term project and those who did not

is large, as mentioned in section 2. Also the implementation and interworking method of

external I/O are not described in the text in detail. In some cases, the ASC cannot be

implemented on the kit because the FPGA is too small.

� Designing ASC and confirm the operation by simulation:

The operation of ASC is confirmed by simulation. If memory is not designed, execution of

only one instruction can be simulated, but if the design includes memory, one program can

be simulated. In order to verify the result of simulation one should observe waveforms and

this is very boring. Also, because it is impossible to interwork with the external I/O device,

it is difficult to execute I/O instructions.

� Theoretical lecture and practice with commercial processors:

Because ASC differs greatly from currently used processors, practice is given with

commercial processors like AVR[8]

or PIC[9]

. In this case, students can be confused because

the theory they learned in lecture and the practice are different.

5. Effectiveness analysis

In order to evaluate the effectiveness of the developed DigiCom in education, the course

evaluation carried out after the completion of the term, examination papers and term project

results were analyzed by comparison. The course evaluation term was from 2004 to 2007, and

the exam paper and term project analysis term were from 2001 to 2007, excluding 2003.

5.1. Survey analysis

The course evaluation is to be entered after the term before knowing the credit for the

corresponding course. Ten common questions are provided for all the courses. Among these

questions, the questions with which the quality of the course in relation with the kit can be

evaluated are as follows:

Q1. Were the contents and level of the teaching materials appropriate for the object of the

course?

Q2. Were the lectures material and substantial?

Q3. Were the guides and instruction for experiment/practice substantial?

Q4. Did the professor proceed with the experiment/practice in efficient manner?

Q5. Through the experiment/practice, could principles and methodology be understood and

could the ability of operating equipments/devices be enhanced?

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The highest point of each question is 5. The Table 8 below presents the marks of above

questions by year.

Table 8. Marks of survey questions

Year

Questions 2004 2005 2006

Average

(2004~2006) 2007

Q1 4.38 3.81 3.95 4.05 3.92

Q2 4.42 3.78 4.00 4.07 4.08

Q3 4.35 3.63 3.95 3.98 4.00

Q4 4.31 3.59 3.68 3.86 4.08

Q5 4.23 3.67 3.74 3.88 4.08

Table 8 shows that average marks between 2004 and 2006 increased compared to those of 2007

excluding Q1.

In addition to above questions, a question reading “Was it helpful for understanding the lectures

to use the DigiCom in the class?” was evaluated in 2007. The mark was 4.35/5 which was higher

than the other questions. However, comparative evaluation was not possible since the question

was given in 2007 for the first time.

5.2. Comparative analysis of the examination papers

Of the exam questions given in the 2007 term, the types of the questions which can be

considered to reflect the effectiveness of the practice, by comparing with those in the previous

terms, are as follows. The exam questions below are similar types, but the same questions were

not always given.

Table 9. Questions for exam used for analysis

Number Question type Years

Question 1 The initial values of registers are as follows. Which values

will be stored after execution of following micro operations.

2001, 2002,

2004, 2005, 2006

Question 2 Explain why each of the following micro operations cannot

be executed during a single clock pulse.

2001, 2002, 2006

Question 3 Give the sequence of register transfer statement needed to

execute each of the listed instructions.

2001, 2002, 2005

The marks of each year were normalized to a maximum of 10 and averaged. The results are

described in Table 10.

Table 10. Normalized marks of each questions by year

Year

Number 2001 2002 2004 2005 2006

Average

(2001~2006) 2007

Question 1 6.63 6.86 6.43 6.28 6.47 6.53 7.26

Question 2 4.38 4.01 - - 3.97 4.12 4,80

Question 3 2.56 2.04 - 2.53 - 2.38 2.49

Page 13.989.12

Table 10 shows that the marks on Q1 and Q2 were improved greatly, but Q3 was still difficult

for students. In particular, the average mark on Q2 was improved more than Q1. One of reason

may be that students could make a mistake while they wrote the exam paper. Q1 required the

exact answer, while Q2 did not.

5.3. Analysis on the term project result

Since all the already-implemented VHDL are open in the course of the practice, the optional

term project, which implements a new ASC, was conducted by the students who have great

interest in this course. Table 11 shows the evaluation result of the term project classified into 4

grades.

Table 11. The success rate of term project classified into 4 grades (%)

Year

Grade 2001 2002 2004 2005 2006

Average

(2001~2006) 2007

1st grade group 11.4 10.7 11.5 13.6 20 13.44 16.7

2nd

grade group 27.2 27.3 26.0 18.2 20 23.74 25.0

3rd

grade group 29.0 21.9 30.4 12.8 30 24.82 16.7

4th

grade group 32.4 40.1 32.1 55.4 30 38 41.6

However, the percentage of the 1st grade group was not increased compared to the year 2006

term, although it was improved compared to the average percentage from 2001 to 2006. Because

new exercises had been added into the course as mentioned above, the term project had not been

provided with sufficient time, and the result does not show great improvement. However, the

reason for an unimproved success rate was not that the understandings of the students on the

computer architecture were not improved.

The most important reasons of the failure in the improvement of the success rate were: first, the

duration of the term project was too short; second, the lack of techniques in using the VHDL

casts large influence on the process of completion.

The following are the technical factors required for the students in the course of implementing

the ASC. The success rate is expected to be improved by providing students with the solutions

and a longer time period to complete the project.

� VHDL data type conversion: it is often required to convert some data types into the port

signal type after processing the declared integer type. The type conversion examples are

provided, such as integer to signal data type conversion.

� Bi-directional bus implementation: the memory data bus should be a bidirectional bus to

enable read and write. A method of implementing a bi-directional bus in VHDL is

provided.

� QuartusII memory implementation: a method of including the memory provided by the

QuartusII into design is provided, in addition to the method of initializing memory using

MIF file.

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We cannot conclude that the developed DigiCom contributed greatly with only the analyses

above, because it was applied during only one term and the variations of assessments is were too

large before the 2007 term. In order to observe the effectiveness of a newly developed teaching

method, the learning performance should be traced for several years and collected from many

lecturers.

6. Conclusion

M. Morris Mano’s Computer System Architecture is a good teaching material for learning

computer operation principles and has been used for a long time. However, it is not easy for

students to learn through theoretical lectures. To this end, DigiCom, which has the same

operational principles as “A Simple Computer” in the text, was developed exclusively for this

course and is different from other digital design kits.

To evaluate the effectiveness of the DigiCom in learning, the course evaluation carried out after

the completion of the term, examination papers and project results from the term which made use

of the kit were compared with those of the terms which did not. The effectiveness of the new kit

could be confirmed by quantitative analysis, and also qualitatively in the class. It could also be

seen that the students’ interests in the course were improved.

However, further analyses would be required to confirm the effectiveness, since the new kit was

used in 2007 for the first time and only one term’s data was available.

7. Acknowledgements

This work was supported by the MIC (Ministry of Information and Communication, Korea),

under the NEXT(Nurturing Excellent engineers in information Technology) supervised by the

IITA (Institute of Information Technology Advancement).

Bibliography

1. M. Morris Mano, “Computer System Architecture 3

rd Edition,” Prentice Hall.

2. S. Ro, “The Training Kit for Computer Architecture,” Project Report, Korea Research Foundation, 2007. 10.

3. Douglas L. Perry, “VHDL 2nd

Edition,” McGraw-Hill, 1994.

4. Jean Michel Berge, et al., “ VHDL Designer’s Reference,” Kluwer Academic Publishers, 1992.

5. “Quartus II Development Software Handbook v7.2,” ALTERA, 2007.

6. “Cyclone Device Handbook,” ALTERA, Jan., 2007.

7. “Xilinx ISE 9.2i Software Manuals and Help,” http://www.xilinx.com. 8. “AVR® 8-bit RISC,” http://www.atmel.com. 9. “8-bit PIC

® Microcontrollers,” http://www.microchip.com.

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