Digital Systems - 2

Pere Pala - Alexis Lopez

iTIC http://itic.cat

February 2015

Numeric Basics

I Coding of numeric information:

I Decimal system: 3710 means 3 × 101 + 7 × 100.

I Decimal system: 20310 means 2 × 102 + 0 × 101 + 3 × 100.

I 3710 = 1 × 25 + 0 × 24 + 0 × 23 + 1 × 22 + 0 × 21 + 1 × 20 .

I 3710 = 1001012.

I n bits : 0 · · · 2n − 1.

I To represent 0 · · ·N − 1 we need log2N bits.

Unsigned Integers

I Declaration: signal s_unsig : unsigned(3 downto 0);

Assignments

Legal: s_unsig <= "1110";

Illegal: s_unsig <= 0;

Legal: s_unsig_dest <= s_unsig+1;

Conversions

I my_slv <= std_logic_vector(my_unsigned);

I my_unsigned <= unsigned(my_slv);

A VHDL type test examplelibrary ieee; use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity num_tb is

end num_tb ;

architecture behav of num_tb is

signal s_logic : std_logic_vector (3 downto 0) ;

signal s_unsig : unsigned (3 downto 0);

begin

s_logic <= std_logic_vector(s_unsig );

process

begin

s_unsig <= "1110";

wait for 1 sec;

s_unsig <= s_unsig +1;

wait for 1 sec;

s_unsig <= s_unsig +1;

wait for 1 sec;

s_unsig <= s_unsig +1;

wait for 1 sec;

wait;

end process ;

end behav ;

Assignments

Resizing an unsigned integer

signal a : unsigned (3 downto 0);

signal b : unsigned (7 downto 0);

b <= "0000" & a;

a <= b(3 downto 0);

I Concatenation operator: &

I Only in the right hand of assignments!

Alternate way

signal a : unsigned (3 downto 0);

signal b : unsigned (7 downto 0);

b <= resize(a,8);

a <= resize(b,4);

Adding Unsigned Integers

Algorithm

1 1 1 1 1 0 0 0

0 0 1 1 1 0 0 11 1 0 0 1 1 0 0

1 0 0 0 0 0 1 0 1

Implementation

fulladder

xi

ci

ci+1

yi

fulladder

x0

c0

c1

y0

fulladder

x1

c2

y1

fulladder

xn–1

cn–1

cn

yn–1

si

s0

s1

sn–1

sn

c_out <= (a and b) or (c_in and (a xor b)); This is slooow!

Adders

Fast-carry-chain adder

I Carry kill: ki = not xi and not yi

I Carry propagate: pi = xi xor yi

I Carry generate: gi = xi and yi

si = pi xor c_in;

co = gi or pi and c_in;

Carry-lookahed generator

I Example for 4 bits

c4 = g3 or (p3 and g 2)

or (p3 and p2 and g1)

or (p3 and p2 and p1 and g 0)

or (p3 and p2 and p1 and p0 and c0)

xi

pi

yi

iii yxp ⊕=

si

ci

ci+1

0

1

iii cps ⊕=iiii cpgc ⋅+=+1

iii yxg ⋅=gi

x0

g0p0

y0

x1

g1p1

y1

x2

g2p2

y2

x3

g3p3

y3

p3

s3

c0

c3

c4

p2

s2

c2 p

1

s1

c1 p

0

s0

carry-lookahead generator

Adder in VHDL

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

...

signal a,b,s : unsigned (3 downto 0);

...

s <= a + b;

I Do not specifiy the equations!

I The software automatically detects the best type of adder.

I This is dependent on the technology and the requirements ofthe designer (speed, area).

Adder with Carry Out

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

...

signal a,b,s : unsigned (7 downto 0);

signal temp : unsigned (8 downto 0); --MSB:carry

signal c_out : std_logic;

...

temp <= (’0’ & a) + (’0’ & b); -- compute sum with 9 bits

s <= temp(7 downto 0); -- true sum is in LSBs

c_out <= temp (8); -- carry is the MSB

Comparing unsigned integers

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity ...

port temp : in unsigned (7 downto 0);

port target : in unsigned (7 downto 0);

port heat : out std_logic;

architecture ...

heat <= ’1’ when temp < target - 5 else ’0’;

I Synthesis software will implement the function.

xn–1

gtxn–1> y

n–1

xn–1= y

n–1

xn–2> y

n–2

yn–1

xn–2

y x > yxn–2= y

n–2

yn–2

x1> y

1

x1…0> y

1…0

xn–2…0

> yn–2…0

x1= y

1

x1

y1

x0> y

0x0

y0

…… …

Comparing unsigned integers

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity ...

port temp : in unsigned (7 downto 0);

port target : in unsigned (7 downto 0);

port heat : out std_logic;

architecture ...

heat <= ’1’ when temp < target - 5 else ’0’;

I Synthesis software will implement the function.

xn–1

gtxn–1> y

n–1

xn–1= y

n–1

xn–2> y

n–2

yn–1

xn–2

y x > yxn–2= y

n–2

yn–2

x1> y

1

x1…0> y

1…0

xn–2…0

> yn–2…0

x1= y

1

x1

y1

x0> y

0x0

y0

…… …